2024-06-13 14:52:23 +02:00
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#include <msp430g2553.h>
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#define DATA_REGISTER r13
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#define CHIP_ID_REGISTER r12
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#define PORT_REG P1OUT
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#define PORT_SID_BIT BIT0
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#define PORT_SCK_BIT BIT1
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#define PORT_LATI0_BIT BIT2
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#define PORT_LATI1_BIT BIT3
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2024-06-13 15:04:55 +02:00
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.altmacro
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2024-06-13 14:52:23 +02:00
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.macro set_data_bit
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bic #PORT_SID_BIT, &PORT_REG
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.endm
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.macro clear_data_bit
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bis #PORT_SID_BIT, &PORT_REG
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.endm
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.macro clock_cycle
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bic #PORT_SCK_BIT, &PORT_REG
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bis #PORT_SCK_BIT, &PORT_REG
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.endm
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.macro lati_cycle chip
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bic #\chip\(), &PORT_REG
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bis #\chip\(), &PORT_REG
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.endm
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.macro data_cycle id
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genShifter_\id\():
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2024-06-13 15:10:23 +02:00
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rra.w DATA_REGISTER
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2024-06-13 14:52:23 +02:00
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jnc genShifter_false_\id\()
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set_data_bit
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jmp genShifter_clock_\id\()
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genShifter_false_\id\():
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clear_data_bit
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genShifter_clock_\id\():
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clock_cycle
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.endm
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.section ".text","ax",@progbits
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.global genShifter
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genShifter:
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// arguments
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// R12 aka CHIP_ID_REGISTER: chip id, 0 or 1
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// R13 aka DATA_REGISTER: frequency code, full 16 bit
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2024-06-13 15:04:55 +02:00
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.set counter, 0
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.rept 16
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data_cycle %counter
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.set counter, counter + 1
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.endr
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2024-06-13 14:52:23 +02:00
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tst.w CHIP_ID_REGISTER
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jnz genShifter_chip_1
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lati_cycle PORT_LATI0_BIT
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genShifter_chip_1:
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lati_cycle PORT_LATI1_BIT
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ret
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