#include #define DATA_REGISTER r13 #define CHIP_ID_REGISTER r12 #define PORT_REG P1OUT #define PORT_SID_BIT BIT0 #define PORT_SCK_BIT BIT1 #define PORT_LATI0_BIT BIT2 #define PORT_LATI1_BIT BIT3 .altmacro .macro set_data_bit bic #PORT_SID_BIT, &PORT_REG .endm .macro clear_data_bit bis #PORT_SID_BIT, &PORT_REG .endm .macro clock_cycle bic #PORT_SCK_BIT, &PORT_REG bis #PORT_SCK_BIT, &PORT_REG .endm .macro lati_cycle chip bic #\chip\(), &PORT_REG bis #\chip\(), &PORT_REG .endm .macro data_cycle id genShifter_\id\(): rra.w DATA_REGISTER jnc genShifter_false_\id\() set_data_bit jmp genShifter_clock_\id\() genShifter_false_\id\(): clear_data_bit genShifter_clock_\id\(): clock_cycle .endm .section ".text","ax",@progbits .global genShifter genShifter: // arguments // R12 aka CHIP_ID_REGISTER: chip id, 0 or 1 // R13 aka DATA_REGISTER: frequency code, full 16 bit .set counter, 0 .rept 16 data_cycle %counter .set counter, counter + 1 .endr tst.w CHIP_ID_REGISTER jnz genShifter_chip_1 lati_cycle PORT_LATI0_BIT genShifter_chip_1: lati_cycle PORT_LATI1_BIT ret