150 lines
3.3 KiB
C
150 lines
3.3 KiB
C
#include <msp430g2553.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "psg.h"
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#include "scheduler.h"
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const uint16_t frequencyCodes[8][12] = {
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// C, Cis, D, Dis, E, F, Fis, G, Gis, A, Ais, H
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{ 06535, 06234, 05747, 05474, 05233, 05002, 04563, 04353, 04153, 03762, 03600, 03424 }, // Octave 1
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{ 03256, 03116, 02764, 02636, 02515, 02401, 02271, 02165, 02065, 01771, 01700, 01612 }, // Octave 2
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{ 01527, 01447, 01372, 01317, 01247, 01201, 01135, 01073, 01033, 00774, 00740, 00705 }, // Octave 3
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{ 00654, 00624, 00575, 00550, 00523, 00500, 00456, 00435, 00415, 00376, 00360, 00342 }, // Octave 4
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{ 00326, 00312, 00276, 00264, 00252, 00240, 00227, 00217, 00207, 00177, 00170, 00161 }, // Octave 5
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{ 00153, 00145, 00137, 00132, 00125, 00120, 00114, 00107, 00103, 00100, 00074, 00071 }, // Octave 6
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{ 00065, 00062, 00060, 00055, 00052, 00050, 00046, 00044, 00042, 00040, 00036, 00034 }, // Octave 7
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{ 00033, 00031, 00030, 00026, 00025, 00024, 00023, 00022, 00021, 00020, 00017, 00016 } // Octave 8
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};
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#define ADDR_DATA_REG P2OUT
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#define BUS_CTRL_REG P1OUT
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#define BC1 BIT3
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#define BDIR BIT1
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#define R0 0
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R10 010
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#define R11 011
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#define R12 012
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#define R13 013
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#define R14 014
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#define R15 015
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uint8_t psgShadowRegisters[14];
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inline static void BUS_OP_NACT() {
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BUS_CTRL_REG &= ~(BDIR | BC1);
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}
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inline static void BUS_OP_INTAK() {
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BUS_CTRL_REG |= BDIR | BC1;
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}
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inline static void BUS_OP_DWS() {
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BUS_CTRL_REG |= BDIR;
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BUS_CTRL_REG &= ~BC1;
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}
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static void delay() {
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asm volatile (
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"push r12\n"
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"mov.w #5, r12\n"
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"loop:\n"
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"dec.w r12\n"
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"jnz loop\n"
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"pop r12\n"
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);
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}
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uint8_t psgReadShadow(uint8_t address) {
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return psgShadowRegisters[address];
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}
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void psgWrite(uint8_t address, uint8_t data) {
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psgShadowRegisters[address] = data;
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// according to "State Timing" (p. 15) of datasheet
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// put bus into inactive state
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BUS_OP_NACT();
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// put address on bus
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ADDR_DATA_REG = address;
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// address latch mode
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BUS_OP_INTAK();
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// latch address
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BUS_OP_NACT();
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// put data on bus
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ADDR_DATA_REG = data;
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// set write to psg
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BUS_OP_DWS();
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// set inactive again
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BUS_OP_NACT();
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}
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void psgWriteFrequency(uint8_t channel, uint16_t frequencyCode) {
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psgWrite(R0 + (channel * 2), (frequencyCode & 0x00ff));
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psgWrite(R1 + (channel * 2), ((frequencyCode >> 8) & 0x000f));
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}
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void psgPlayTone(uint8_t channel, t_octave octave, t_note note) {
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if (note == e_Pause) {
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psgWrite(R7, psgReadShadow(R7) | (1 << channel));
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} else {
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psgWrite(R7, psgReadShadow(R7) & ~(1 << channel));
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psgWriteFrequency(channel, frequencyCodes[octave][note]);
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}
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}
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void psgAmplitude(uint8_t channel, uint8_t volume) {
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psgWrite(R10 + channel, volume);
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}
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void psgInit() {
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// address/data bus
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P2DIR = 0xff;
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P2SEL = 0;
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P2SEL2 = 0;
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// sound chip reset
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// BIT2: /RST
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P1DIR |= BIT2;
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// put sound chip into reset state
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P1OUT &= ~BIT2;
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delay();
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delay();
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delay();
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// bus control lines
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// BIT3: BC1
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// BIT1: BDIR
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P1DIR |= BIT1 | BIT3;
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// put bus into inactive state
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BUS_CTRL_REG &= ~(BDIR | BC1);
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// release sound chip from reset state
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P1OUT |= BIT2;
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delay();
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delay();
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delay();
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// disable everything
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psgWrite(R7, 0xff);
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}
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