wn/tetris
wn/tetris
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refactor names, 4

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This commit is contained in:
Wolfgang Hottgenroth 2024-02-27 17:48:22 +01:00
parent e1b7c328f8
commit c829a76273
2 changed files with 6 additions and 3 deletions
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2
colors.S
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@ -3,7 +3,7 @@
.section ".rodata","a"
screendata_tmpl:
.global screendata_tmpl
.byte _blue
.byte _red
.byte _off
.byte _yellow
screendataend_tmpl:

7
main.S
View File

@ -15,6 +15,7 @@
#define NEXT_DATA_REGISTER r9
#define BIT_COUNTER_REGISTER r6
#define BIT_COUNTER_INIT_VALUE 0x01
.section ".data"
@ -50,6 +51,8 @@ _start:
;; ----------------------------------------------
;; load data from template area in rom into ram
;; uses arbitrary register before loading registers
;; for later use
mov.w #screendata, r7
mov.w #screendataend, r8
mov.w #screendata_tmpl, r9
@ -83,7 +86,7 @@ init:
mov.w #OUTMOD_7,&TA1CCTL2
;; initialize bit-counter for isr
mov.b #0x01, BIT_COUNTER_REGISTER
mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER
;; initialize isr-sync register, signal BYTE_DONE for the first start
mov.b #0x01, SIGNAL_REGISTER
@ -180,7 +183,7 @@ timer1_a0_isr_end:
jnc timer1_a0_isr_exit
;; reset bit-counter
mov.b #0x01, BIT_COUNTER_REGISTER
mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER
;; signal byte done
bis #0x01, SIGNAL_REGISTER