dead code dropped
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36d3b2f735
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@ -13,7 +13,7 @@ CFLAGS+= -g3 -ggdb -gdwarf-2
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LDFLAGS=-mmcu=$(MCU) -L $(TOOLCHAIN_PREFIX)/include
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$(ARTIFACT).elf: main.o scheduler.o spi.o spi_init.o sequencer.o melody_tetris.o melody_tusch1.o ay_3_8913.o mute.o
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$(ARTIFACT).elf: main.o scheduler.o spi.o spi_init.o sequencer.o melody_tetris.o melody_tusch1.o psg.o mute.o
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$(CC) -o $@ $(LDFLAGS) $^
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$(OBJDUMP) -D $(ARTIFACT).elf > $(ARTIFACT).txt
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@ -6,7 +6,9 @@
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void muteInit() {
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// BIT6: MuteCtrl
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P1DIR |= BIT6;
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P1OUT &= ~BIT6;
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// initially, mute
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P1OUT |= BIT6;
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}
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void mute() {
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@ -1,171 +0,0 @@
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#include <msp430g2553.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include "psg.h"
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#include "scheduler.h"
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// generated using utils/calc-76489an.py
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const uint16_t frequencyCodes[8][12] = {
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{ 3420, 3229, 3047, 2876, 2715, 2562, 2419, 2283, 2155, 2034, 1920, 1812 },
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{ 1710, 1614, 1524, 1438, 1357, 1281, 1209, 1141, 1077, 1017, 960, 906 },
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{ 855, 807, 762, 719, 679, 641, 605, 571, 539, 508, 480, 453 },
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{ 428, 404, 381, 360, 339, 320, 302, 285, 269, 254, 240, 226 },
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{ 214, 202, 190, 180, 170, 160, 151, 143, 135, 127, 120, 113 },
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{ 107, 101, 95, 90, 85, 80, 76, 71, 67, 64, 60, 57 },
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{ 53, 50, 48, 45, 42, 40, 38, 36, 34, 32, 30, 28 },
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{ 27, 25, 24, 22, 21, 20, 19, 18, 17, 16, 15, 14 }
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};
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#define ADDR_DATA_REG P2OUT
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#define BUS_CTRL_REG P1OUT
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#define BUS_CTRL_IN_REG P1IN
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#define _CS0 BIT0
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#define _CS1 BIT1
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#define _WE BIT2
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#define READY BIT3
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#define CHANNEL_A_PERIOD_ADDR 0
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#define CHANNEL_A_ATTEN_ADDR 1
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#define CHANNEL_B_PERIOD_ADDR 2
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#define CHANNEL_B_ATTEN_ADDR 3
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#define CHANNEL_C_PERIOD_ADDR 4
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#define CHANNEL_C_ATTEN_ADDR 5
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#define IGNORE_OCTET 0xff
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uint8_t psgAmplitudeShadowValue[3];
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static void delay() {
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asm volatile (
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"push r12\n"
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"mov.w #5, r12\n"
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"loop:\n"
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"dec.w r12\n"
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"jnz loop\n"
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"pop r12\n"
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);
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}
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inline static void WRITE_CYCLE(uint8_t chipNo) {
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if (chipNo == 0) {
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BUS_CTRL_REG &= ~_CS0;
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} else {
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BUS_CTRL_REG &= ~_CS1;
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}
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BUS_CTRL_REG &= ~_WE;
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delay();
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while ((BUS_CTRL_IN_REG & READY) == 0);
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BUS_CTRL_REG |= _WE;
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if (chipNo == 0) {
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BUS_CTRL_REG |= _CS0;
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} else {
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BUS_CTRL_REG |= _CS1;
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}
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delay();
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}
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static void psgWrite(uint8_t chipNo, uint8_t value) {
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ADDR_DATA_REG = value;
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WRITE_CYCLE(chipNo);
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}
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static void psgWriteFrequency(uint8_t channel, uint16_t frequencyCode) {
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uint8_t chipNo = channel / 3;
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uint8_t regAddr = (channel % 3) * 2;
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// bit order in frequncyCode and order in octet on data bus are reversed
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// see datacheat cp. 1 and cp. 6
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uint8_t firstOctet = 0x01;
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firstOctet |= ((regAddr & 0x04) > 1);
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firstOctet |= ((regAddr & 0x02) < 1);
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firstOctet |= ((regAddr & 0x01) < 3);
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uint8_t lowerPart = frequencyCode & 0x0f;
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firstOctet |= ((lowerPart & 0x08) << 1);
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firstOctet |= ((lowerPart & 0x04) << 3);
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firstOctet |= ((lowerPart & 0x02) << 5);
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firstOctet |= ((lowerPart & 0x01) << 7);
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uint8_t secondOctet = 0;
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uint8_t upperPart = (frequencyCode & 0x03f0) >> 4;
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secondOctet |= ((upperPart & 0x20) >> 3);
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secondOctet |= ((upperPart & 0x10) >> 1);
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secondOctet |= ((upperPart & 0x08) << 1);
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secondOctet |= ((upperPart & 0x04) << 3);
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secondOctet |= ((upperPart & 0x02) << 5);
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secondOctet |= ((upperPart & 0x01) << 7);
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ADDR_DATA_REG = firstOctet;
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WRITE_CYCLE(chipNo);
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ADDR_DATA_REG = secondOctet;
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WRITE_CYCLE(chipNo);
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}
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void psgAmplitude(uint8_t channel, uint8_t volume) {
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psgAmplitudeShadowValue[channel] = volume;
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uint8_t chipNo = channel / 3;
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uint8_t regAddr = ((channel % 3) * 2) + 1;
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uint8_t attenuation = 15 - volume;
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uint8_t firstOctet = 0x01;
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firstOctet |= ((regAddr & 0x04) >> 1);
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firstOctet |= ((regAddr & 0x02) << 1);
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firstOctet |= ((regAddr & 0x01) << 3);
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firstOctet |= ((attenuation & 0x01) << 7);
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firstOctet |= ((attenuation & 0x02) << 5);
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firstOctet |= ((attenuation & 0x04) << 3);
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firstOctet |= ((attenuation & 0x08) << 1);
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ADDR_DATA_REG = firstOctet;
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WRITE_CYCLE(chipNo);
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}
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void psgPlayTone(uint8_t channel, uint8_t volume, t_octave octave, t_note note) {
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if (note == e_Pause) {
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psgAmplitude(channel, 0);
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} else {
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// if (psgAmplitudeShadowValue[channel] == 0) {
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psgAmplitude(channel, volume);
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// }
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psgWriteFrequency(channel, frequencyCodes[octave][note]);
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}
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}
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void psgInit() {
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// address/data bus
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P2DIR = 0xff;
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P2SEL = 0;
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P2SEL2 = 0;
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// bus control lines
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// output:
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// BIT0: /CS chip 0
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// BIT1: /CS chip 1
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// BIT2: /WE
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// input:
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// BIT3: READY
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P1DIR |= BIT0 | BIT1 | BIT2;
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P1DIR &= ~BIT3;
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// immediately disable all outputs, all are active low
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P1OUT |= BIT0 | BIT1 | BIT2;
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// shutdown all channels including noise
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psgWrite(0, 0b11111001);
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psgWrite(0, 0b11111101);
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psgWrite(0, 0b11111011);
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psgWrite(0, 0b11111111);
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// psgPlayTone(0, 5, e_O_3, e_A);
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psgAmplitude(0, 3);
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}
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