register numbering is octal!

sound-driver/main.c

@@ -3,6 +3,43 @@
 #include <stdlib.h>
 
 
+#define ADDR_DATA_REG P2OUT
+#define BUS_CTRL_REG P1OUT
+#define BC1 BIT0
+#define BDIR BIT1
+#define _CS BIT3
+
+#define R0 0
+#define R1 1
+#define R2 2
+#define R3 3
+#define R4 4
+#define R5 5
+#define R6 6
+#define R7 7
+#define R10 010
+#define R11 011
+#define R12 012
+#define R13 013
+#define R14 014
+#define R15 015
+
+inline static void BUS_OP_ENABLE_CS() {
+  BUS_CTRL_REG &= ~_CS;
+}
+inline static void BUS_OP_DISABLE_CS() {
+  BUS_CTRL_REG |= _CS;
+}
+inline static void BUS_OP_NACT() {
+  BUS_CTRL_REG &= ~(BDIR | BC1);
+}
+inline static void BUS_OP_INTAK() {
+  BUS_CTRL_REG |= BDIR | BC1;
+}
+inline static void BUS_OP_DWS() {
+  BUS_CTRL_REG |= BDIR;
+  BUS_CTRL_REG &= ~BC1;
+}
 
 void __attribute__ ((interrupt (USCIAB0RX_VECTOR))) receive() {
   if (UC0IFG & UCB0RXIFG) {
@@ -11,6 +48,60 @@ void __attribute__ ((interrupt (USCIAB0RX_VECTOR))) receive() {
 }
 
 
+static void delay() {
+asm volatile (
+    "push r12\n"
+    "mov.w #5, r12\n"
+    "loop:\n"
+    "dec.w r12\n"
+    "jnz loop\n"
+    "pop r12\n"
+);
+}
+
+static void writePSG(uint8_t address, uint8_t data) {
+  // according to "State Timing" (p. 15) of datasheet
+
+  // select chip
+  //BUS_OP_ENABLE_CS();
+
+  // put bus into inactive state
+  BUS_OP_NACT();
+
+  delay();
+
+  // put address on bus
+  ADDR_DATA_REG = address;
+
+  delay();
+
+  // address latch mode
+  BUS_OP_INTAK();
+
+  delay();
+
+  // latch address
+  BUS_OP_NACT();
+
+  delay();
+
+  // put data on bus
+  ADDR_DATA_REG = data;
+  
+  delay();
+
+  // set write to psg
+  BUS_OP_DWS();
+
+  delay();
+
+  // set inactive again
+  BUS_OP_NACT();
+
+  // deselect chip
+  //BUS_OP_DISABLE_CS();
+}
+
 int main() {
   WDTCTL = WDTPW | WDTHOLD;
 
@@ -35,9 +126,49 @@ int main() {
   // enable RX interrupt
   UC0IE |= UCB0RXIE;
 
+  // address/data bus
+  P2DIR = 0xff;
+  P2SEL = 0;
+  P2SEL2 = 0;
+
+  // sound chip reset
+  // BIT2: /RST
+  P1DIR |= BIT2;
+
+  // put sound chip into reset state
+  P1OUT &= ~BIT2;
+  delay();
+  delay();
+  delay();
+  
+  // bus control lines
+  // BIT0: BC1
+  // BIT1: BDIR
+  // BIT3: /CS
+  P1DIR |= BIT0 | BIT1 | BIT3;
+
+  // put bus into inactive state
+  BUS_CTRL_REG &= ~(BDIR | BC1);
+  BUS_CTRL_REG |= _CS;
+  
+  // release sound chip from reset state
+  P1OUT |= BIT2;
+  delay();
+  delay();
+  delay();
+  
 
   __enable_interrupt();
 
+
+  BUS_OP_ENABLE_CS();
+  writePSG(R0, 0376);
+  writePSG(R1, 0);
+  writePSG(R7, 076);
+  writePSG(R10, 03);
+  BUS_OP_DISABLE_CS();
+
+
   while (1) {
   }
 }