2024-03-25 13:28:33 +01:00
|
|
|
#include <msp430g2553.h>
|
|
|
|
#include <stdint.h>
|
|
|
|
#include <stdlib.h>
|
|
|
|
|
2024-03-26 14:43:02 +01:00
|
|
|
#include "psg.h"
|
2024-03-26 10:44:23 +01:00
|
|
|
#include "scheduler.h"
|
2024-03-26 15:58:45 +01:00
|
|
|
#include "sequencer.h"
|
2024-03-26 10:44:23 +01:00
|
|
|
|
2024-03-25 13:28:33 +01:00
|
|
|
void __attribute__ ((interrupt (USCIAB0RX_VECTOR))) receive() {
|
|
|
|
if (UC0IFG & UCB0RXIFG) {
|
|
|
|
// receive an octet
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int main() {
|
|
|
|
WDTCTL = WDTPW | WDTHOLD;
|
|
|
|
|
|
|
|
__disable_interrupt();
|
|
|
|
|
|
|
|
// highest possible system clock
|
|
|
|
DCOCTL = DCO0 | DCO1 | DCO2;
|
|
|
|
BCSCTL1 = XT2OFF | RSEL0 | RSEL1 | RSEL2 | RSEL3;
|
|
|
|
BCSCTL2 = 0;
|
|
|
|
BCSCTL3 = 0;
|
|
|
|
|
|
|
|
// SPI slave
|
|
|
|
// BIT4: UCB0STE
|
|
|
|
// BIT5: UCB0CLK
|
|
|
|
// BIT6: UCB0SOMI
|
|
|
|
// BIT7: UCB0SIMO
|
|
|
|
P1SEL |= BIT4 | BIT5 | BIT6 | BIT7;
|
|
|
|
P1SEL2 |= BIT4 | BIT5 | BIT6 | BIT7;
|
|
|
|
// most significant bit first, enable STE
|
|
|
|
UCB0CTL0 = UCSYNC | UCMSB | UCMODE_2;
|
|
|
|
UCB0CTL1 = 0x00;
|
|
|
|
// enable RX interrupt
|
|
|
|
UC0IE |= UCB0RXIE;
|
|
|
|
|
|
|
|
|
2024-03-26 10:44:23 +01:00
|
|
|
schInit();
|
|
|
|
|
2024-03-26 14:43:02 +01:00
|
|
|
psgInit();
|
2024-03-26 15:58:45 +01:00
|
|
|
sequencerInit();
|
2024-03-25 23:13:33 +01:00
|
|
|
|
2024-03-26 14:43:02 +01:00
|
|
|
__enable_interrupt();
|
2024-03-25 22:11:15 +01:00
|
|
|
|
|
|
|
|
2024-03-25 13:28:33 +01:00
|
|
|
while (1) {
|
2024-03-26 10:44:23 +01:00
|
|
|
schExec();
|
2024-03-25 13:28:33 +01:00
|
|
|
}
|
|
|
|
}
|