wn/stm32_test1
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

renamed project

Browse Source
This commit is contained in:
Wolfgang Hottgenroth
2020-10-06 13:33:17 +02:00
parent ec90e3a2dc
commit f5831e083f
81 changed files with 86194 additions and 75934 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
cube/.mxproject Normal file
View File

@ -0,0 +1,31 @@
[PreviousLibFiles]
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
[PreviousUsedMakefileFiles]
SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\adc.c;Core\Src\usart.c;Core\Src\stm32f1xx_it.c;Core\Src\stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Core\Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Core\Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;;
HeaderPath=Drivers\STM32F1xx_HAL_Driver\Inc;Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F1xx\Include;Drivers\CMSIS\Include;Core\Inc;
CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
[PreviousGenFiles]
AdvancedFolderStructure=true
HeaderFileListSize=6
HeaderFiles#0=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/gpio.h
HeaderFiles#1=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/adc.h
HeaderFiles#2=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/usart.h
HeaderFiles#3=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/stm32f1xx_it.h
HeaderFiles#4=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/stm32f1xx_hal_conf.h
HeaderFiles#5=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc/main.h
HeaderFolderListSize=1
HeaderPath#0=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Inc
HeaderFiles=;
SourceFileListSize=6
SourceFiles#0=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/gpio.c
SourceFiles#1=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/adc.c
SourceFiles#2=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/usart.c
SourceFiles#3=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/stm32f1xx_it.c
SourceFiles#4=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/stm32f1xx_hal_msp.c
SourceFiles#5=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src/main.c
SourceFolderListSize=1
SourcePath#0=C:/Users/dehottgw/workspaces/workspace-private/stm32_test1/cube/Core/Src
SourceFiles=;

58
cube/Core/Inc/adc.h Normal file
View File

@ -0,0 +1,58 @@
/**
******************************************************************************
* File Name : ADC.h
* Description : This file provides code for the configuration
* of the ADC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __adc_H
#define __adc_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern ADC_HandleTypeDef hadc1;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_ADC1_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ adc_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

114
stm32_test1/Core/Inc/gpio.h → cube/Core/Inc/gpio.h
View File

@ -1,57 +1,57 @@
/** /**
****************************************************************************** ******************************************************************************
* File Name : gpio.h * File Name : gpio.h
* Description : This file contains all the functions prototypes for * Description : This file contains all the functions prototypes for
* the gpio * the gpio
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __gpio_H #ifndef __gpio_H
#define __gpio_H #define __gpio_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* USER CODE BEGIN Private defines */ /* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */ /* USER CODE END Private defines */
void MX_GPIO_Init(void); void MX_GPIO_Init(void);
/* USER CODE BEGIN Prototypes */ /* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */ /* USER CODE END Prototypes */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /*__ pinoutConfig_H */ #endif /*__ pinoutConfig_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

173
stm32_test1/Core/Inc/main.h → cube/Core/Inc/main.h
View File

@ -1,77 +1,96 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file : main.h * @file : main.h
* @brief : Header for main.c file. * @brief : Header for main.c file.
* This file contains the common defines of the application. * This file contains the common defines of the application.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H #ifndef __MAIN_H
#define __MAIN_H #define __MAIN_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */ /* USER CODE BEGIN ET */
/* USER CODE END ET */ /* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */ /* USER CODE BEGIN EC */
/* USER CODE END EC */ /* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
/* USER CODE END EM */ /* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/ /* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void); void Error_Handler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/
#define LED_Green_Pin GPIO_PIN_13 #define LED_Heartbeat_Pin GPIO_PIN_13
#define LED_Green_GPIO_Port GPIOC #define LED_Heartbeat_GPIO_Port GPIOC
#define LED_Red_Pin GPIO_PIN_14 #define LED_Error_Pin GPIO_PIN_14
#define LED_Red_GPIO_Port GPIOC #define LED_Error_GPIO_Port GPIOC
#define LED_Blue_Pin GPIO_PIN_15 #define LED_Operation_Pin GPIO_PIN_15
#define LED_Blue_GPIO_Port GPIOC #define LED_Operation_GPIO_Port GPIOC
/* USER CODE BEGIN Private defines */ #define Frontend_In_Pin GPIO_PIN_1
#define Frontend_In_GPIO_Port GPIOA
/* USER CODE END Private defines */ #define Debug_TX_Pin GPIO_PIN_10
#define Debug_TX_GPIO_Port GPIOC
#ifdef __cplusplus #define Debug_RX_Pin GPIO_PIN_11
} #define Debug_RX_GPIO_Port GPIOC
#endif #define Meterbus_Tx_Pin GPIO_PIN_12
#define Meterbus_Tx_GPIO_Port GPIOC
#endif /* __MAIN_H */ #define Meterbus_RX_Pin GPIO_PIN_2
#define Meterbus_RX_GPIO_Port GPIOD
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ #define Frontend_Out_Pin GPIO_PIN_3
#define Frontend_Out_GPIO_Port GPIOD
#define Loop_Disable_Pin GPIO_PIN_6
#define Loop_Disable_GPIO_Port GPIOD
#define Loop_Enable_Pin GPIO_PIN_7
#define Loop_Enable_GPIO_Port GPIOD
#define Loop_Status_Pin GPIO_PIN_3
#define Loop_Status_GPIO_Port GPIOB
#define Loop_Status_EXTI_IRQn EXTI3_IRQn
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif /* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

782
stm32_test1/Core/Inc/stm32f1xx_hal_conf.h → cube/Core/Inc/stm32f1xx_hal_conf.h
View File

@ -1,391 +1,391 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_conf.h * @file stm32f1xx_hal_conf.h
* @brief HAL configuration file. * @brief HAL configuration file.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H #ifndef __STM32F1xx_HAL_CONF_H
#define __STM32F1xx_HAL_CONF_H #define __STM32F1xx_HAL_CONF_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */ /* ########################## Module Selection ############################## */
/** /**
* @brief This is the list of modules to be used in the HAL driver * @brief This is the list of modules to be used in the HAL driver
*/ */
#define HAL_MODULE_ENABLED #define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */ #define HAL_ADC_MODULE_ENABLED
/*#define HAL_CRYP_MODULE_ENABLED */ /*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */ /*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CAN_LEGACY_MODULE_ENABLED */ /*#define HAL_CAN_LEGACY_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */ /*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CORTEX_MODULE_ENABLED */ /*#define HAL_CORTEX_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */ /*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */ /*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DMA_MODULE_ENABLED */ /*#define HAL_DMA_MODULE_ENABLED */
/*#define HAL_ETH_MODULE_ENABLED */ /*#define HAL_ETH_MODULE_ENABLED */
/*#define HAL_FLASH_MODULE_ENABLED */ /*#define HAL_FLASH_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED
/*#define HAL_I2C_MODULE_ENABLED */ /*#define HAL_I2C_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */ /*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */ /*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */ /*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */ /*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_PCCARD_MODULE_ENABLED */ /*#define HAL_PCCARD_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */ /*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_PWR_MODULE_ENABLED */ /*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_RCC_MODULE_ENABLED */ /*#define HAL_RCC_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */ /*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_UART_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_CORTEX_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/ /* ########################## Oscillator Values adaptation ####################*/
/** /**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency * This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
* @brief Internal High Speed oscillator (HSI) value. * @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency * This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL). * (when HSI is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/** /**
* @brief Internal Low Speed oscillator (LSI) value. * @brief Internal Low Speed oscillator (LSI) value.
*/ */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature. */ in voltage and temperature. */
/** /**
* @brief External Low Speed oscillator (LSE) value. * @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency * This value is used by the UART, RTC HAL module to compute the system frequency
*/ */
#if !defined (LSE_VALUE) #if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/ #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT) #if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */ #endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */ === you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */ /* ########################### System Configuration ######################### */
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */ #define TICK_INT_PRIORITY 0U /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 1U #define PREFETCH_ENABLE 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ #define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
/* ########################## Assert Selection ############################## */ /* ########################## Assert Selection ############################## */
/** /**
* @brief Uncomment the line below to expanse the "assert_param" macro in the * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code * HAL drivers code
*/ */
/* #define USE_FULL_ASSERT 1U */ /* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */ /* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */ /* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U #define MAC_ADDR0 2U
#define MAC_ADDR1 0U #define MAC_ADDR1 0U
#define MAC_ADDR2 0U #define MAC_ADDR2 0U
#define MAC_ADDR3 0U #define MAC_ADDR3 0U
#define MAC_ADDR4 0U #define MAC_ADDR4 0U
#define MAC_ADDR5 0U #define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */ /* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_RXBUFNB 8U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */ /* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/ /* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U #define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY 0x000000FFU #define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */ /* PHY Configuration delay */
#define PHY_CONFIG_DELAY 0x00000FFFU #define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU #define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */ /* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ #define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */ /* Section 4: Extended PHY Registers */
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ #define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ #define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver /* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver * Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver * Deactivated: CRC code cleaned from driver
*/ */
#define USE_SPI_CRC 0U #define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
/** /**
* @brief Include module's header file * @brief Include module's header file
*/ */
#ifdef HAL_RCC_MODULE_ENABLED #ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f1xx_hal_rcc.h" #include "stm32f1xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */ #endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h" #include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED #ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f1xx_hal_exti.h" #include "stm32f1xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */ #endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED #ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h" #include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */ #endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED #ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f1xx_hal_eth.h" #include "stm32f1xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */ #endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED #ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h" #include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */ #endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED #ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "Legacy/stm32f1xx_hal_can_legacy.h" #include "Legacy/stm32f1xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED #ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f1xx_hal_cec.h" #include "stm32f1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */ #endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED #ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f1xx_hal_cortex.h" #include "stm32f1xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */ #endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED #ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f1xx_hal_adc.h" #include "stm32f1xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */ #endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED #ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f1xx_hal_crc.h" #include "stm32f1xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */ #endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED #ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f1xx_hal_dac.h" #include "stm32f1xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */ #endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED #ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f1xx_hal_flash.h" #include "stm32f1xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */ #endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED #ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f1xx_hal_sram.h" #include "stm32f1xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */ #endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED #ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f1xx_hal_nor.h" #include "stm32f1xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */ #endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED #ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f1xx_hal_i2c.h" #include "stm32f1xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */ #endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED #ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f1xx_hal_i2s.h" #include "stm32f1xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */ #endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED #ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f1xx_hal_iwdg.h" #include "stm32f1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */ #endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED #ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f1xx_hal_pwr.h" #include "stm32f1xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */ #endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED #ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f1xx_hal_rtc.h" #include "stm32f1xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */ #endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED #ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h" #include "stm32f1xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */ #endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED #ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h" #include "stm32f1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */ #endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED #ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f1xx_hal_nand.h" #include "stm32f1xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */ #endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED #ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h" #include "stm32f1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */ #endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED #ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f1xx_hal_tim.h" #include "stm32f1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */ #endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED #ifdef HAL_UART_MODULE_ENABLED
#include "stm32f1xx_hal_uart.h" #include "stm32f1xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */ #endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED #ifdef HAL_USART_MODULE_ENABLED
#include "stm32f1xx_hal_usart.h" #include "stm32f1xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */ #endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED #ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f1xx_hal_irda.h" #include "stm32f1xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */ #endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED #ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f1xx_hal_smartcard.h" #include "stm32f1xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ #endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED #ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f1xx_hal_wwdg.h" #include "stm32f1xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */ #endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED #ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f1xx_hal_pcd.h" #include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */ #endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED #ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h" #include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */ #endif /* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED #ifdef HAL_MMC_MODULE_ENABLED
#include "stm32f1xx_hal_mmc.h" #include "stm32f1xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */ #endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT #ifdef USE_FULL_ASSERT
/** /**
* @brief The assert_param macro is used for function's parameters check. * @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function * @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source * which reports the name of the source file and the source
* line number of the call that failed. * line number of the call that failed.
* If expr is true, it returns no value. * If expr is true, it returns no value.
* @retval None * @retval None
*/ */
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */ /* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line); void assert_failed(uint8_t* file, uint32_t line);
#else #else
#define assert_param(expr) ((void)0U) #define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */ #endif /* USE_FULL_ASSERT */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_CONF_H */ #endif /* __STM32F1xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

142
stm32_test1/Core/Inc/stm32f1xx_it.h → cube/Core/Inc/stm32f1xx_it.h
View File

@ -1,69 +1,73 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_it.h * @file stm32f1xx_it.h
* @brief This file contains the headers of the interrupt handlers. * @brief This file contains the headers of the interrupt handlers.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_IT_H #ifndef __STM32F1xx_IT_H
#define __STM32F1xx_IT_H #define __STM32F1xx_IT_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */ /* USER CODE BEGIN ET */
/* USER CODE END ET */ /* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */ /* USER CODE BEGIN EC */
/* USER CODE END EC */ /* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
/* USER CODE END EM */ /* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/ /* Exported functions prototypes ---------------------------------------------*/
void NMI_Handler(void); void NMI_Handler(void);
void HardFault_Handler(void); void HardFault_Handler(void);
void MemManage_Handler(void); void MemManage_Handler(void);
void BusFault_Handler(void); void BusFault_Handler(void);
void UsageFault_Handler(void); void UsageFault_Handler(void);
void SVC_Handler(void); void SVC_Handler(void);
void DebugMon_Handler(void); void DebugMon_Handler(void);
void PendSV_Handler(void); void PendSV_Handler(void);
void SysTick_Handler(void); void SysTick_Handler(void);
/* USER CODE BEGIN EFP */ void EXTI3_IRQHandler(void);
void ADC1_2_IRQHandler(void);
/* USER CODE END EFP */ void UART4_IRQHandler(void);
void UART5_IRQHandler(void);
#ifdef __cplusplus /* USER CODE BEGIN EFP */
}
#endif /* USER CODE END EFP */
#endif /* __STM32F1xx_IT_H */ #ifdef __cplusplus
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ #endif
#endif /* __STM32F1xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

60
cube/Core/Inc/usart.h Normal file
View File

@ -0,0 +1,60 @@
/**
******************************************************************************
* File Name : USART.h
* Description : This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __usart_H
#define __usart_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
extern UART_HandleTypeDef huart4;
extern UART_HandleTypeDef huart5;
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
void MX_UART4_Init(void);
void MX_UART5_Init(void);
/* USER CODE BEGIN Prototypes */
/* USER CODE END Prototypes */
#ifdef __cplusplus
}
#endif
#endif /*__ usart_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

106
cube/Core/Src/adc.c Normal file
View File

@ -0,0 +1,106 @@
/**
******************************************************************************
* File Name : ADC.c
* Description : This file provides code for the configuration
* of the ADC instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "adc.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
ADC_HandleTypeDef hadc1;
/* ADC1 init function */
void MX_ADC1_Init(void)
{
/** Common config
*/
hadc1.Instance = ADC1;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.ContinuousConvMode = ENABLE;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc1.Init.NbrOfConversion = 1;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
Error_Handler();
}
}
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(adcHandle->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* ADC1 clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**ADC1 GPIO Configuration
PA1 ------> ADC1_IN1
*/
GPIO_InitStruct.Pin = Frontend_In_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
HAL_GPIO_Init(Frontend_In_GPIO_Port, &GPIO_InitStruct);
/* ADC1 interrupt Init */
HAL_NVIC_SetPriority(ADC1_2_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(ADC1_2_IRQn);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)
{
if(adcHandle->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC1_CLK_DISABLE();
/**ADC1 GPIO Configuration
PA1 ------> ADC1_IN1
*/
HAL_GPIO_DeInit(Frontend_In_GPIO_Port, Frontend_In_Pin);
/* ADC1 interrupt Deinit */
HAL_NVIC_DisableIRQ(ADC1_2_IRQn);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

151
stm32_test1/Core/Src/gpio.c → cube/Core/Src/gpio.c
View File

@ -1,64 +1,87 @@
/** /**
****************************************************************************** ******************************************************************************
* File Name : gpio.c * File Name : gpio.c
* Description : This file provides code for the configuration * Description : This file provides code for the configuration
* of all used GPIO pins. * of all used GPIO pins.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "gpio.h" #include "gpio.h"
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/* Configure GPIO */ /* Configure GPIO */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
/** Configure pins as /** Configure pins as
* Analog * Analog
* Input * Input
* Output * Output
* EVENT_OUT * EVENT_OUT
* EXTI * EXTI
*/ */
void MX_GPIO_Init(void) void MX_GPIO_Init(void)
{ {
GPIO_InitTypeDef GPIO_InitStruct = {0}; GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/*Configure GPIO pin Output Level */ __HAL_RCC_GPIOD_CLK_ENABLE();
HAL_GPIO_WritePin(GPIOC, LED_Green_Pin|LED_Red_Pin|LED_Blue_Pin, GPIO_PIN_RESET); __HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pins : PCPin PCPin PCPin */ /*Configure GPIO pin Output Level */
GPIO_InitStruct.Pin = LED_Green_Pin|LED_Red_Pin|LED_Blue_Pin; HAL_GPIO_WritePin(GPIOC, LED_Heartbeat_Pin|LED_Error_Pin|LED_Operation_Pin, GPIO_PIN_RESET);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; /*Configure GPIO pin Output Level */
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_WritePin(GPIOD, Frontend_Out_Pin|Loop_Disable_Pin|Loop_Enable_Pin, GPIO_PIN_RESET);
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pins : PCPin PCPin PCPin */
} GPIO_InitStruct.Pin = LED_Heartbeat_Pin|LED_Error_Pin|LED_Operation_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
/* USER CODE BEGIN 2 */ GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
/* USER CODE END 2 */ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /*Configure GPIO pins : PDPin PDPin PDPin */
GPIO_InitStruct.Pin = Frontend_Out_Pin|Loop_Disable_Pin|Loop_Enable_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = Loop_Status_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(Loop_Status_GPIO_Port, &GPIO_InitStruct);
/* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI3_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(EXTI3_IRQn);
}
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

372
stm32_test1/Core/Src/main.c → cube/Core/Src/main.c
View File

@ -1,180 +1,192 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file : main.c * @file : main.c
* @brief : Main program body * @brief : Main program body
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
#include "gpio.h" #include "adc.h"
#include "usart.h"
/* Private includes ----------------------------------------------------------*/ #include "gpio.h"
/* USER CODE BEGIN Includes */
#include <stdint.h> /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */ #include "main2.h";
/* Private typedef -----------------------------------------------------------*/ /* USER CODE END Includes */
/* USER CODE BEGIN PTD */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE END PTD */ /* USER CODE BEGIN PTD */
/* Private define ------------------------------------------------------------*/ /* USER CODE END PTD */
/* USER CODE BEGIN PD */
/* USER CODE END PD */ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* Private macro -------------------------------------------------------------*/ /* USER CODE END PD */
/* USER CODE BEGIN PM */
/* Private macro -------------------------------------------------------------*/
/* USER CODE END PM */ /* USER CODE BEGIN PM */
/* Private variables ---------------------------------------------------------*/ /* USER CODE END PM */
/* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */ /* USER CODE BEGIN PV */
/* Private function prototypes -----------------------------------------------*/ /* USER CODE END PV */
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE END PFP */ /* USER CODE BEGIN PFP */
/* Private user code ---------------------------------------------------------*/ /* USER CODE END PFP */
/* USER CODE BEGIN 0 */
/* Private user code ---------------------------------------------------------*/
/* USER CODE END 0 */ /* USER CODE BEGIN 0 */
/** /* USER CODE END 0 */
* @brief The application entry point.
* @retval int /**
*/ * @brief The application entry point.
int main(void) * @retval int
{ */
/* USER CODE BEGIN 1 */ int main(void)
{
/* USER CODE END 1 */ /* USER CODE BEGIN 1 */
my_setup_1();
/* MCU Configuration--------------------------------------------------------*/
/* USER CODE END 1 */
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init(); /* MCU Configuration--------------------------------------------------------*/
/* USER CODE BEGIN Init */ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE END Init */
/* USER CODE BEGIN Init */
/* Configure the system clock */
SystemClock_Config(); /* USER CODE END Init */
/* USER CODE BEGIN SysInit */ /* Configure the system clock */
SystemClock_Config();
/* USER CODE END SysInit */
/* USER CODE BEGIN SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init(); /* USER CODE END SysInit */
/* USER CODE BEGIN 2 */
/* Initialize all configured peripherals */
uint32_t x = 2; MX_GPIO_Init();
MX_ADC1_Init();
/* USER CODE END 2 */ MX_UART4_Init();
MX_UART5_Init();
/* Infinite loop */ /* USER CODE BEGIN 2 */
/* USER CODE BEGIN WHILE */ my_setup_2();
while (1)
{ /* USER CODE END 2 */
/* USER CODE END WHILE */
/* Infinite loop */
/* USER CODE BEGIN 3 */ /* USER CODE BEGIN WHILE */
while (1)
x += 1; {
/* USER CODE END WHILE */
}
/* USER CODE END 3 */ /* USER CODE BEGIN 3 */
} my_loop();
}
/** /* USER CODE END 3 */
* @brief System Clock Configuration }
* @retval None
*/ /**
void SystemClock_Config(void) * @brief System Clock Configuration
{ * @retval None
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; */
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; void SystemClock_Config(void)
{
/** Initializes the RCC Oscillators according to the specified parameters RCC_OscInitTypeDef RCC_OscInitStruct = {0};
* in the RCC_OscInitTypeDef structure. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
*/ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /** Initializes the RCC Oscillators according to the specified parameters
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; * in the RCC_OscInitTypeDef structure.
RCC_OscInitStruct.HSIState = RCC_HSI_ON; */
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) RCC_OscInitStruct.HSIState = RCC_HSI_ON;
{ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Error_Handler(); RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
} RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
/** Initializes the CPU, AHB and APB buses clocks if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
*/ {
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK Error_Handler();
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; }
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /** Initializes the CPU, AHB and APB buses clocks
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; */
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
{ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
Error_Handler(); RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
}
} if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
/* USER CODE BEGIN 4 */ Error_Handler();
}
/* USER CODE END 4 */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
/** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
* @brief This function is executed in case of error occurrence. {
* @retval None Error_Handler();
*/ }
void Error_Handler(void) }
{
/* USER CODE BEGIN Error_Handler_Debug */ /* USER CODE BEGIN 4 */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END 4 */
/* USER CODE END Error_Handler_Debug */
} /**
* @brief This function is executed in case of error occurrence.
#ifdef USE_FULL_ASSERT * @retval None
/** */
* @brief Reports the name of the source file and the source line number void Error_Handler(void)
* where the assert_param error has occurred. {
* @param file: pointer to the source file name /* USER CODE BEGIN Error_Handler_Debug */
* @param line: assert_param error line source number my_errorHandler();
* @retval None /* User can add his own implementation to report the HAL error return state */
*/
void assert_failed(uint8_t *file, uint32_t line) /* USER CODE END Error_Handler_Debug */
{ while(1) { };
/* USER CODE BEGIN 6 */ }
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ #ifdef USE_FULL_ASSERT
/* USER CODE END 6 */ /**
} * @brief Reports the name of the source file and the source line number
#endif /* USE_FULL_ASSERT */ * where the assert_param error has occurred.
* @param file: pointer to the source file name
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ * @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

186
cube/Core/Src/main.c-bak Normal file
View File

@ -0,0 +1,186 @@
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "adc.h"
#include "usart.h"
#include "gpio.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_ADC1_Init();
MX_UART4_Init();
MX_UART5_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

176
stm32_test1/Core/Src/stm32f1xx_hal_msp.c → cube/Core/Src/stm32f1xx_hal_msp.c
View File

@ -1,88 +1,88 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* File Name : stm32f1xx_hal_msp.c * File Name : stm32f1xx_hal_msp.c
* Description : This file provides code for the MSP Initialization * Description : This file provides code for the MSP Initialization
* and de-Initialization codes. * and de-Initialization codes.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* USER CODE BEGIN TD */
/* USER CODE END TD */ /* USER CODE END TD */
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */ /* USER CODE BEGIN Define */
/* USER CODE END Define */ /* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */ /* USER CODE BEGIN Macro */
/* USER CODE END Macro */ /* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
/* USER CODE END PV */ /* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
/* External functions --------------------------------------------------------*/ /* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */ /* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */ /* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
/** /**
* Initializes the Global MSP. * Initializes the Global MSP.
*/ */
void HAL_MspInit(void) void HAL_MspInit(void)
{ {
/* USER CODE BEGIN MspInit 0 */ /* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */ /* USER CODE END MspInit 0 */
__HAL_RCC_AFIO_CLK_ENABLE(); __HAL_RCC_AFIO_CLK_ENABLE();
__HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE();
/* System interrupt init*/ /* System interrupt init*/
/** DISABLE: JTAG-DP Disabled and SW-DP Disabled /** DISABLE: JTAG-DP Disabled and SW-DP Disabled
*/ */
__HAL_AFIO_REMAP_SWJ_DISABLE(); __HAL_AFIO_REMAP_SWJ_DISABLE();
/* USER CODE BEGIN MspInit 1 */ /* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */ /* USER CODE END MspInit 1 */
} }
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

464
stm32_test1/Core/Src/stm32f1xx_it.c → cube/Core/Src/stm32f1xx_it.c
View File

@ -1,203 +1,261 @@
/* USER CODE BEGIN Header */ /* USER CODE BEGIN Header */
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_it.c * @file stm32f1xx_it.c
* @brief Interrupt Service Routines. * @brief Interrupt Service Routines.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* USER CODE END Header */ /* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
#include "stm32f1xx_it.h" #include "stm32f1xx_it.h"
/* Private includes ----------------------------------------------------------*/ /* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */ /* USER CODE BEGIN TD */
/* USER CODE END TD */ /* USER CODE END TD */
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */ /* USER CODE BEGIN PD */
/* USER CODE END PD */ /* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */ /* USER CODE BEGIN PM */
/* USER CODE END PM */ /* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
/* USER CODE END PV */ /* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/ /* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
/* External variables --------------------------------------------------------*/ /* External variables --------------------------------------------------------*/
extern ADC_HandleTypeDef hadc1;
/* USER CODE BEGIN EV */ extern UART_HandleTypeDef huart4;
extern UART_HandleTypeDef huart5;
/* USER CODE END EV */ /* USER CODE BEGIN EV */
/******************************************************************************/ /* USER CODE END EV */
/* Cortex-M3 Processor Interruption and Exception Handlers */
/******************************************************************************/ /******************************************************************************/
/** /* Cortex-M3 Processor Interruption and Exception Handlers */
* @brief This function handles Non maskable interrupt. /******************************************************************************/
*/ /**
void NMI_Handler(void) * @brief This function handles Non maskable interrupt.
{ */
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ void NMI_Handler(void)
{
/* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 1 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
}
/* USER CODE END NonMaskableInt_IRQn 1 */
/** }
* @brief This function handles Hard fault interrupt.
*/ /**
void HardFault_Handler(void) * @brief This function handles Hard fault interrupt.
{ */
/* USER CODE BEGIN HardFault_IRQn 0 */ void HardFault_Handler(void)
{
/* USER CODE END HardFault_IRQn 0 */ /* USER CODE BEGIN HardFault_IRQn 0 */
while (1)
{ /* USER CODE END HardFault_IRQn 0 */
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ while (1)
/* USER CODE END W1_HardFault_IRQn 0 */ {
} /* USER CODE BEGIN W1_HardFault_IRQn 0 */
} /* USER CODE END W1_HardFault_IRQn 0 */
}
/** }
* @brief This function handles Memory management fault.
*/ /**
void MemManage_Handler(void) * @brief This function handles Memory management fault.
{ */
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ void MemManage_Handler(void)
{
/* USER CODE END MemoryManagement_IRQn 0 */ /* USER CODE BEGIN MemoryManagement_IRQn 0 */
while (1)
{ /* USER CODE END MemoryManagement_IRQn 0 */
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ while (1)
/* USER CODE END W1_MemoryManagement_IRQn 0 */ {
} /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
} /* USER CODE END W1_MemoryManagement_IRQn 0 */
}
/** }
* @brief This function handles Prefetch fault, memory access fault.
*/ /**
void BusFault_Handler(void) * @brief This function handles Prefetch fault, memory access fault.
{ */
/* USER CODE BEGIN BusFault_IRQn 0 */ void BusFault_Handler(void)
{
/* USER CODE END BusFault_IRQn 0 */ /* USER CODE BEGIN BusFault_IRQn 0 */
while (1)
{ /* USER CODE END BusFault_IRQn 0 */
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ while (1)
/* USER CODE END W1_BusFault_IRQn 0 */ {
} /* USER CODE BEGIN W1_BusFault_IRQn 0 */
} /* USER CODE END W1_BusFault_IRQn 0 */
}
/** }
* @brief This function handles Undefined instruction or illegal state.
*/ /**
void UsageFault_Handler(void) * @brief This function handles Undefined instruction or illegal state.
{ */
/* USER CODE BEGIN UsageFault_IRQn 0 */ void UsageFault_Handler(void)
{
/* USER CODE END UsageFault_IRQn 0 */ /* USER CODE BEGIN UsageFault_IRQn 0 */
while (1)
{ /* USER CODE END UsageFault_IRQn 0 */
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ while (1)
/* USER CODE END W1_UsageFault_IRQn 0 */ {
} /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
} /* USER CODE END W1_UsageFault_IRQn 0 */
}
/** }
* @brief This function handles System service call via SWI instruction.
*/ /**
void SVC_Handler(void) * @brief This function handles System service call via SWI instruction.
{ */
/* USER CODE BEGIN SVCall_IRQn 0 */ void SVC_Handler(void)
{
/* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 1 */ /* USER CODE BEGIN SVCall_IRQn 1 */
}
/* USER CODE END SVCall_IRQn 1 */
/** }
* @brief This function handles Debug monitor.
*/ /**
void DebugMon_Handler(void) * @brief This function handles Debug monitor.
{ */
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ void DebugMon_Handler(void)
{
/* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 1 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */
}
/* USER CODE END DebugMonitor_IRQn 1 */
/** }
* @brief This function handles Pendable request for system service.
*/ /**
void PendSV_Handler(void) * @brief This function handles Pendable request for system service.
{ */
/* USER CODE BEGIN PendSV_IRQn 0 */ void PendSV_Handler(void)
{
/* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 1 */ /* USER CODE BEGIN PendSV_IRQn 1 */
}
/* USER CODE END PendSV_IRQn 1 */
/** }
* @brief This function handles System tick timer.
*/ /**
void SysTick_Handler(void) * @brief This function handles System tick timer.
{ */
/* USER CODE BEGIN SysTick_IRQn 0 */ void SysTick_Handler(void)
{
/* USER CODE END SysTick_IRQn 0 */ /* USER CODE BEGIN SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
/* USER CODE END SysTick_IRQn 1 */ /* USER CODE BEGIN SysTick_IRQn 1 */
}
/* USER CODE END SysTick_IRQn 1 */
/******************************************************************************/ }
/* STM32F1xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */ /******************************************************************************/
/* For the available peripheral interrupt handler names, */ /* STM32F1xx Peripheral Interrupt Handlers */
/* please refer to the startup file (startup_stm32f1xx.s). */ /* Add here the Interrupt Handlers for the used peripherals. */
/******************************************************************************/ /* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32f1xx.s). */
/* USER CODE BEGIN 1 */ /******************************************************************************/
/* USER CODE END 1 */ /**
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ * @brief This function handles EXTI line3 interrupt.
*/
void EXTI3_IRQHandler(void)
{
/* USER CODE BEGIN EXTI3_IRQn 0 */
/* USER CODE END EXTI3_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
/* USER CODE BEGIN EXTI3_IRQn 1 */
/* USER CODE END EXTI3_IRQn 1 */
}
/**
* @brief This function handles ADC1 and ADC2 global interrupts.
*/
void ADC1_2_IRQHandler(void)
{
/* USER CODE BEGIN ADC1_2_IRQn 0 */
/* USER CODE END ADC1_2_IRQn 0 */
HAL_ADC_IRQHandler(&hadc1);
/* USER CODE BEGIN ADC1_2_IRQn 1 */
/* USER CODE END ADC1_2_IRQn 1 */
}
/**
* @brief This function handles UART4 global interrupt.
*/
void UART4_IRQHandler(void)
{
/* USER CODE BEGIN UART4_IRQn 0 */
/* USER CODE END UART4_IRQn 0 */
HAL_UART_IRQHandler(&huart4);
/* USER CODE BEGIN UART4_IRQn 1 */
/* USER CODE END UART4_IRQn 1 */
}
/**
* @brief This function handles UART5 global interrupt.
*/
void UART5_IRQHandler(void)
{
/* USER CODE BEGIN UART5_IRQn 0 */
/* USER CODE END UART5_IRQn 0 */
HAL_UART_IRQHandler(&huart5);
/* USER CODE BEGIN UART5_IRQn 1 */
/* USER CODE END UART5_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

816
stm32_test1/Core/Src/system_stm32f1xx.c → cube/Core/Src/system_stm32f1xx.c
View File

@ -1,408 +1,408 @@
/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32f1xx.c * @file system_stm32f1xx.c
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* *
* 1. This file provides two functions and one global variable to be called from * 1. This file provides two functions and one global variable to be called from
* user application: * user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings). * factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and * This function is called at startup just after reset and
* before branch to main program. This call is made inside * before branch to main program. This call is made inside
* the "startup_stm32f1xx_xx.s" file. * the "startup_stm32f1xx_xx.s" file.
* *
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick * by the user application to setup the SysTick
* timer or configure other parameters. * timer or configure other parameters.
* *
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed * be called whenever the core clock is changed
* during program execution. * during program execution.
* *
* 2. After each device reset the HSI (8 MHz) is used as system clock source. * 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
* configure the system clock before to branch to main program. * configure the system clock before to branch to main program.
* *
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
* the product used), refer to "HSE_VALUE". * the product used), refer to "HSE_VALUE".
* When HSE is used as system clock source, directly or through PLL, and you * When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own * are using different crystal you have to adapt the HSE value to your own
* configuration. * configuration.
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f1xx_system /** @addtogroup stm32f1xx_system
* @{ * @{
*/ */
/** @addtogroup STM32F1xx_System_Private_Includes /** @addtogroup STM32F1xx_System_Private_Includes
* @{ * @{
*/ */
#include "stm32f1xx.h" #include "stm32f1xx.h"
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_Defines /** @addtogroup STM32F1xx_System_Private_Defines
* @{ * @{
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */ This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */ This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */ /*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */ /* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/* Note: Following vector table addresses must be defined in line with linker /* Note: Following vector table addresses must be defined in line with linker
configuration. */ configuration. */
/*!< Uncomment the following line if you need to relocate the vector table /*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */ remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */ /* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table /*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */ in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */ /* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM) #if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#else #else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */ This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */ #endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/ /******************************************************************************/
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_Macros /** @addtogroup STM32F1xx_System_Private_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_Variables /** @addtogroup STM32F1xx_System_Private_Variables
* @{ * @{
*/ */
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 16000000; uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
* @{ * @{
*/ */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void); static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F1xx_System_Private_Functions /** @addtogroup STM32F1xx_System_Private_Functions
* @{ * @{
*/ */
/** /**
* @brief Setup the microcontroller system * @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the * Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable. * SystemCoreClock variable.
* @note This function should be used only after reset. * @note This function should be used only after reset.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit (void) void SystemInit (void)
{ {
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl(); SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif #endif
/* Configure the Vector Table location -------------------------------------*/ /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
} }
/** /**
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can * The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure * be used by the user application to setup the SysTick timer or configure
* other parameters. * other parameters.
* *
* @note Each time the core clock (HCLK) changes, this function must be called * @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration * to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect. * based on this variable will be incorrect.
* *
* @note - The system frequency computed by this function is not the real * @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source: * constant and the selected clock source:
* *
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
* *
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
* *
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors. * or HSI_VALUE(*) multiplied by the PLL factors.
* *
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations * 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature. * in voltage and temperature.
* *
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure * 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used. * that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result. * Otherwise, this function may have wrong result.
* *
* - The result of this function could be not correct when using fractional * - The result of this function could be not correct when using fractional
* value for HSE crystal. * value for HSE crystal.
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC) #if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
#endif /* STM32F105xC */ #endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t prediv1factor = 0U; uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */ #endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/ /* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS; tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp) switch (tmp)
{ {
case 0x00U: /* HSI used as system clock */ case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
case 0x04U: /* HSE used as system clock */ case 0x04U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE; SystemCoreClock = HSE_VALUE;
break; break;
case 0x08U: /* PLL used as system clock */ case 0x08U: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/ /* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC) #if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = ( pllmull >> 18U) + 2U; pllmull = ( pllmull >> 18U) + 2U;
if (pllsource == 0x00U) if (pllsource == 0x00U)
{ {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
} }
else else
{ {
#if defined(STM32F100xB) || defined(STM32F100xE) #if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else #else
/* HSE selected as PLL clock entry */ /* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */ {/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
} }
else else
{ {
SystemCoreClock = HSE_VALUE * pllmull; SystemCoreClock = HSE_VALUE * pllmull;
} }
#endif #endif
} }
#else #else
pllmull = pllmull >> 18U; pllmull = pllmull >> 18U;
if (pllmull != 0x0DU) if (pllmull != 0x0DU)
{ {
pllmull += 2U; pllmull += 2U;
} }
else else
{ /* PLL multiplication factor = PLL input clock * 6.5 */ { /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13U / 2U; pllmull = 13U / 2U;
} }
if (pllsource == 0x00U) if (pllsource == 0x00U)
{ {
/* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
} }
else else
{/* PREDIV1 selected as PLL clock entry */ {/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */ /* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
if (prediv1source == 0U) if (prediv1source == 0U)
{ {
/* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
} }
else else
{/* PLL2 clock selected as PREDIV1 clock entry */ {/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */ /* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
} }
} }
#endif /* STM32F105xC */ #endif /* STM32F105xC */
break; break;
default: default:
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
break; break;
} }
/* Compute HCLK clock frequency ----------------*/ /* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */ /* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */ /* HCLK clock frequency */
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/** /**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main * before jump to __main
* @param None * @param None
* @retval None * @retval None
*/ */
#ifdef DATA_IN_ExtSRAM #ifdef DATA_IN_ExtSRAM
/** /**
* @brief Setup the external memory controller. * @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main. * Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL * This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program * board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack). * data memory (including heap and stack).
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit_ExtMemCtl(void) void SystemInit_ExtMemCtl(void)
{ {
__IO uint32_t tmpreg; __IO uint32_t tmpreg;
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */ required, then adjust the Register Addresses */
/* Enable FSMC clock */ /* Enable FSMC clock */
RCC->AHBENR = 0x00000114U; RCC->AHBENR = 0x00000114U;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0U; RCC->APB2ENR = 0x000001E0U;
/* Delay after an RCC peripheral clock enabling */ /* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
(void)(tmpreg); (void)(tmpreg);
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/ /*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/ /*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BBU; GPIOD->CRL = 0x44BB44BBU;
GPIOD->CRH = 0xBBBBBBBBU; GPIOD->CRH = 0xBBBBBBBBU;
GPIOE->CRL = 0xB44444BBU; GPIOE->CRL = 0xB44444BBU;
GPIOE->CRH = 0xBBBBBBBBU; GPIOE->CRH = 0xBBBBBBBBU;
GPIOF->CRL = 0x44BBBBBBU; GPIOF->CRL = 0x44BBBBBBU;
GPIOF->CRH = 0xBBBB4444U; GPIOF->CRH = 0xBBBB4444U;
GPIOG->CRL = 0x44BBBBBBU; GPIOG->CRL = 0x44BBBBBBU;
GPIOG->CRH = 0x444B4B44U; GPIOG->CRH = 0x444B4B44U;
/*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4U] = 0x00001091U; FSMC_Bank1->BTCR[4U] = 0x00001091U;
FSMC_Bank1->BTCR[5U] = 0x00110212U; FSMC_Bank1->BTCR[5U] = 0x00110212U;
} }
#endif /* DATA_IN_ExtSRAM */ #endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

185
cube/Core/Src/usart.c Normal file
View File

@ -0,0 +1,185 @@
/**
******************************************************************************
* File Name : USART.c
* Description : This file provides code for the configuration
* of the USART instances.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "usart.h"
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
UART_HandleTypeDef huart4;
UART_HandleTypeDef huart5;
/* UART4 init function */
void MX_UART4_Init(void)
{
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
Error_Handler();
}
}
/* UART5 init function */
void MX_UART5_Init(void)
{
huart5.Instance = UART5;
huart5.Init.BaudRate = 2400;
huart5.Init.WordLength = UART_WORDLENGTH_8B;
huart5.Init.StopBits = UART_STOPBITS_1;
huart5.Init.Parity = UART_PARITY_EVEN;
huart5.Init.Mode = UART_MODE_TX_RX;
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart5.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart5) != HAL_OK)
{
Error_Handler();
}
}
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(uartHandle->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspInit 0 */
/* USER CODE END UART4_MspInit 0 */
/* UART4 clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/**UART4 GPIO Configuration
PC10 ------> UART4_TX
PC11 ------> UART4_RX
*/
GPIO_InitStruct.Pin = Debug_TX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(Debug_TX_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = Debug_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(Debug_RX_GPIO_Port, &GPIO_InitStruct);
/* UART4 interrupt Init */
HAL_NVIC_SetPriority(UART4_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(UART4_IRQn);
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
else if(uartHandle->Instance==UART5)
{
/* USER CODE BEGIN UART5_MspInit 0 */
/* USER CODE END UART5_MspInit 0 */
/* UART5 clock enable */
__HAL_RCC_UART5_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**UART5 GPIO Configuration
PC12 ------> UART5_TX
PD2 ------> UART5_RX
*/
GPIO_InitStruct.Pin = Meterbus_Tx_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(Meterbus_Tx_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Pin = Meterbus_RX_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(Meterbus_RX_GPIO_Port, &GPIO_InitStruct);
/* UART5 interrupt Init */
HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(UART5_IRQn);
/* USER CODE BEGIN UART5_MspInit 1 */
/* USER CODE END UART5_MspInit 1 */
}
}
void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
{
if(uartHandle->Instance==UART4)
{
/* USER CODE BEGIN UART4_MspDeInit 0 */
/* USER CODE END UART4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART4_CLK_DISABLE();
/**UART4 GPIO Configuration
PC10 ------> UART4_TX
PC11 ------> UART4_RX
*/
HAL_GPIO_DeInit(GPIOC, Debug_TX_Pin|Debug_RX_Pin);
/* UART4 interrupt Deinit */
HAL_NVIC_DisableIRQ(UART4_IRQn);
/* USER CODE BEGIN UART4_MspDeInit 1 */
/* USER CODE END UART4_MspDeInit 1 */
}
else if(uartHandle->Instance==UART5)
{
/* USER CODE BEGIN UART5_MspDeInit 0 */
/* USER CODE END UART5_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_UART5_CLK_DISABLE();
/**UART5 GPIO Configuration
PC12 ------> UART5_TX
PD2 ------> UART5_RX
*/
HAL_GPIO_DeInit(Meterbus_Tx_GPIO_Port, Meterbus_Tx_Pin);
HAL_GPIO_DeInit(Meterbus_RX_GPIO_Port, Meterbus_RX_Pin);
/* UART5 interrupt Deinit */
HAL_NVIC_DisableIRQ(UART5_IRQn);
/* USER CODE BEGIN UART5_MspDeInit 1 */
/* USER CODE END UART5_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

23522
stm32_test1/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h → cube/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
View File

File diff suppressed because it is too large Load Diff

440
stm32_test1/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h → cube/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
View File

@ -1,220 +1,220 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx.h * @file stm32f1xx.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File. * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
* *
* The file is the unique include file that the application programmer * The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains: * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select: * - Configuration section that allows to select:
* - The STM32F1xx device used in the target application * - The STM32F1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e. * - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers * code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by * rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER" * "#define USE_HAL_DRIVER"
* *
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f1xx /** @addtogroup stm32f1xx
* @{ * @{
*/ */
#ifndef __STM32F1XX_H #ifndef __STM32F1XX_H
#define __STM32F1XX_H #define __STM32F1XX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
/** @addtogroup Library_configuration_section /** @addtogroup Library_configuration_section
* @{ * @{
*/ */
/** /**
* @brief STM32 Family * @brief STM32 Family
*/ */
#if !defined (STM32F1) #if !defined (STM32F1)
#define STM32F1 #define STM32F1
#endif /* STM32F1 */ #endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your /* Uncomment the line below according to the target STM32L device used in your
application application
*/ */
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \ #if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \ !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC) !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */ /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */ /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */ /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */ /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */ /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */ /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */ /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */ /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */ /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */ /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */ /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */ /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif #endif
/* Tip: To avoid modifying this file each time you need to switch between these /* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor. devices, you can define the device in your toolchain compiler preprocessor.
*/ */
#if !defined (USE_HAL_DRIVER) #if !defined (USE_HAL_DRIVER)
/** /**
* @brief Comment the line below if you will not use the peripherals drivers. * @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
/*#define USE_HAL_DRIVER */ /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V4.3.2 * @brief CMSIS Device version number V4.3.2
*/ */
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ #define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\ |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC)) |(__STM32F1_CMSIS_VERSION_RC))
/** /**
* @} * @}
*/ */
/** @addtogroup Device_Included /** @addtogroup Device_Included
* @{ * @{
*/ */
#if defined(STM32F100xB) #if defined(STM32F100xB)
#include "stm32f100xb.h" #include "stm32f100xb.h"
#elif defined(STM32F100xE) #elif defined(STM32F100xE)
#include "stm32f100xe.h" #include "stm32f100xe.h"
#elif defined(STM32F101x6) #elif defined(STM32F101x6)
#include "stm32f101x6.h" #include "stm32f101x6.h"
#elif defined(STM32F101xB) #elif defined(STM32F101xB)
#include "stm32f101xb.h" #include "stm32f101xb.h"
#elif defined(STM32F101xE) #elif defined(STM32F101xE)
#include "stm32f101xe.h" #include "stm32f101xe.h"
#elif defined(STM32F101xG) #elif defined(STM32F101xG)
#include "stm32f101xg.h" #include "stm32f101xg.h"
#elif defined(STM32F102x6) #elif defined(STM32F102x6)
#include "stm32f102x6.h" #include "stm32f102x6.h"
#elif defined(STM32F102xB) #elif defined(STM32F102xB)
#include "stm32f102xb.h" #include "stm32f102xb.h"
#elif defined(STM32F103x6) #elif defined(STM32F103x6)
#include "stm32f103x6.h" #include "stm32f103x6.h"
#elif defined(STM32F103xB) #elif defined(STM32F103xB)
#include "stm32f103xb.h" #include "stm32f103xb.h"
#elif defined(STM32F103xE) #elif defined(STM32F103xE)
#include "stm32f103xe.h" #include "stm32f103xe.h"
#elif defined(STM32F103xG) #elif defined(STM32F103xG)
#include "stm32f103xg.h" #include "stm32f103xg.h"
#elif defined(STM32F105xC) #elif defined(STM32F105xC)
#include "stm32f105xc.h" #include "stm32f105xc.h"
#elif defined(STM32F107xC) #elif defined(STM32F107xC)
#include "stm32f107xc.h" #include "stm32f107xc.h"
#else #else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)" #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_types /** @addtogroup Exported_types
* @{ * @{
*/ */
typedef enum typedef enum
{ {
RESET = 0, RESET = 0,
SET = !RESET SET = !RESET
} FlagStatus, ITStatus; } FlagStatus, ITStatus;
typedef enum typedef enum
{ {
DISABLE = 0, DISABLE = 0,
ENABLE = !DISABLE ENABLE = !DISABLE
} FunctionalState; } FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum typedef enum
{ {
SUCCESS = 0U, SUCCESS = 0U,
ERROR = !SUCCESS ERROR = !SUCCESS
} ErrorStatus; } ErrorStatus;
/** /**
* @} * @}
*/ */
/** @addtogroup Exported_macros /** @addtogroup Exported_macros
* @{ * @{
*/ */
#define SET_BIT(REG, BIT) ((REG) |= (BIT)) #define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT)) #define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0)) #define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL)) #define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG)) #define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/** /**
* @} * @}
*/ */
#if defined (USE_HAL_DRIVER) #if defined (USE_HAL_DRIVER)
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* __STM32F1xx_H */ #endif /* __STM32F1xx_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

196
stm32_test1/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h → cube/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
View File

@ -1,98 +1,98 @@
/** /**
****************************************************************************** ******************************************************************************
* @file system_stm32f10x.h * @file system_stm32f10x.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/** @addtogroup CMSIS /** @addtogroup CMSIS
* @{ * @{
*/ */
/** @addtogroup stm32f10x_system /** @addtogroup stm32f10x_system
* @{ * @{
*/ */
/** /**
* @brief Define to prevent recursive inclusion * @brief Define to prevent recursive inclusion
*/ */
#ifndef __SYSTEM_STM32F10X_H #ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H #define __SYSTEM_STM32F10X_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/** @addtogroup STM32F10x_System_Includes /** @addtogroup STM32F10x_System_Includes
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_types /** @addtogroup STM32F10x_System_Exported_types
* @{ * @{
*/ */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Constants /** @addtogroup STM32F10x_System_Exported_Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Macros /** @addtogroup STM32F10x_System_Exported_Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** @addtogroup STM32F10x_System_Exported_Functions /** @addtogroup STM32F10x_System_Exported_Functions
* @{ * @{
*/ */
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /*__SYSTEM_STM32F10X_H */ #endif /*__SYSTEM_STM32F10X_H */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1730
stm32_test1/Drivers/CMSIS/Include/cmsis_armcc.h → cube/Drivers/CMSIS/Include/cmsis_armcc.h
View File

File diff suppressed because it is too large Load Diff

3738
stm32_test1/Drivers/CMSIS/Include/cmsis_armclang.h → cube/Drivers/CMSIS/Include/cmsis_armclang.h
View File

File diff suppressed because it is too large Load Diff

532
stm32_test1/Drivers/CMSIS/Include/cmsis_compiler.h → cube/Drivers/CMSIS/Include/cmsis_compiler.h
View File

@ -1,266 +1,266 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_compiler.h * @file cmsis_compiler.h
* @brief CMSIS compiler generic header file * @brief CMSIS compiler generic header file
* @version V5.0.4 * @version V5.0.4
* @date 10. January 2018 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#ifndef __CMSIS_COMPILER_H #ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H #define __CMSIS_COMPILER_H
#include <stdint.h> #include <stdint.h>
/* /*
* Arm Compiler 4/5 * Arm Compiler 4/5
*/ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#include "cmsis_armcc.h" #include "cmsis_armcc.h"
/* /*
* Arm Compiler 6 (armclang) * Arm Compiler 6 (armclang)
*/ */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h" #include "cmsis_armclang.h"
/* /*
* GNU Compiler * GNU Compiler
*/ */
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
/* /*
* IAR Compiler * IAR Compiler
*/ */
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h> #include <cmsis_iccarm.h>
/* /*
* TI Arm Compiler * TI Arm Compiler
*/ */
#elif defined ( __TI_ARM__ ) #elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h> #include <cmsis_ccs.h>
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __attribute__((packed)) #define __PACKED __attribute__((packed))
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed)) #define __PACKED_STRUCT struct __attribute__((packed))
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed)) #define __PACKED_UNION union __attribute__((packed))
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; }; struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x))) #define __ALIGNED(x) __attribute__((aligned(x)))
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
/* /*
* TASKING Compiler * TASKING Compiler
*/ */
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
/* /*
* The CMSIS functions have been implemented as intrinsics in the compiler. * The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics, * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones. * Including the CMSIS ones.
*/ */
#ifndef __ASM #ifndef __ASM
#define __ASM __asm #define __ASM __asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn)) #define __NO_RETURN __attribute__((noreturn))
#endif #endif
#ifndef __USED #ifndef __USED
#define __USED __attribute__((used)) #define __USED __attribute__((used))
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __attribute__((weak)) #define __WEAK __attribute__((weak))
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED __packed__ #define __PACKED __packed__
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__ #define __PACKED_STRUCT struct __packed__
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__ #define __PACKED_UNION union __packed__
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; }; struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#define __ALIGNED(x) __align(x) #define __ALIGNED(x) __align(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
/* /*
* COSMIC Compiler * COSMIC Compiler
*/ */
#elif defined ( __CSMC__ ) #elif defined ( __CSMC__ )
#include <cmsis_csm.h> #include <cmsis_csm.h>
#ifndef __ASM #ifndef __ASM
#define __ASM _asm #define __ASM _asm
#endif #endif
#ifndef __INLINE #ifndef __INLINE
#define __INLINE inline #define __INLINE inline
#endif #endif
#ifndef __STATIC_INLINE #ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline #define __STATIC_INLINE static inline
#endif #endif
#ifndef __STATIC_FORCEINLINE #ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE #define __STATIC_FORCEINLINE __STATIC_INLINE
#endif #endif
#ifndef __NO_RETURN #ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here // NO RETURN is automatically detected hence no warning here
#define __NO_RETURN #define __NO_RETURN
#endif #endif
#ifndef __USED #ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored. #warning No compiler specific solution for __USED. __USED is ignored.
#define __USED #define __USED
#endif #endif
#ifndef __WEAK #ifndef __WEAK
#define __WEAK __weak #define __WEAK __weak
#endif #endif
#ifndef __PACKED #ifndef __PACKED
#define __PACKED @packed #define __PACKED @packed
#endif #endif
#ifndef __PACKED_STRUCT #ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct #define __PACKED_STRUCT @packed struct
#endif #endif
#ifndef __PACKED_UNION #ifndef __PACKED_UNION
#define __PACKED_UNION @packed union #define __PACKED_UNION @packed union
#endif #endif
#ifndef __UNALIGNED_UINT32 /* deprecated */ #ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; }; @packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif #endif
#ifndef __UNALIGNED_UINT16_WRITE #ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT16_READ #ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __UNALIGNED_UINT32_WRITE #ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif #endif
#ifndef __UNALIGNED_UINT32_READ #ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif #endif
#ifndef __ALIGNED #ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x) #define __ALIGNED(x)
#endif #endif
#ifndef __RESTRICT #ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT #define __RESTRICT
#endif #endif
#else #else
#error Unknown compiler. #error Unknown compiler.
#endif #endif
#endif /* __CMSIS_COMPILER_H */ #endif /* __CMSIS_COMPILER_H */

4170
stm32_test1/Drivers/CMSIS/Include/cmsis_gcc.h → cube/Drivers/CMSIS/Include/cmsis_gcc.h
View File

File diff suppressed because it is too large Load Diff

1870
stm32_test1/Drivers/CMSIS/Include/cmsis_iccarm.h → cube/Drivers/CMSIS/Include/cmsis_iccarm.h
View File

File diff suppressed because it is too large Load Diff

78
stm32_test1/Drivers/CMSIS/Include/cmsis_version.h → cube/Drivers/CMSIS/Include/cmsis_version.h
View File

@ -1,39 +1,39 @@
/**************************************************************************//** /**************************************************************************//**
* @file cmsis_version.h * @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions * @brief CMSIS Core(M) Version definitions
* @version V5.0.2 * @version V5.0.2
* @date 19. April 2017 * @date 19. April 2017
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved. * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef __CMSIS_VERSION_H #ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H #define __CMSIS_VERSION_H
/* CMSIS Version definitions */ /* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif #endif

3836
stm32_test1/Drivers/CMSIS/Include/core_armv8mbl.h → cube/Drivers/CMSIS/Include/core_armv8mbl.h
View File

File diff suppressed because it is too large Load Diff

5854
stm32_test1/Drivers/CMSIS/Include/core_armv8mml.h → cube/Drivers/CMSIS/Include/core_armv8mml.h
View File

File diff suppressed because it is too large Load Diff

1898
stm32_test1/Drivers/CMSIS/Include/core_cm0.h → cube/Drivers/CMSIS/Include/core_cm0.h
View File

File diff suppressed because it is too large Load Diff

2166
stm32_test1/Drivers/CMSIS/Include/core_cm0plus.h → cube/Drivers/CMSIS/Include/core_cm0plus.h
View File

File diff suppressed because it is too large Load Diff

1952
stm32_test1/Drivers/CMSIS/Include/core_cm1.h → cube/Drivers/CMSIS/Include/core_cm1.h
View File

File diff suppressed because it is too large Load Diff

3986
stm32_test1/Drivers/CMSIS/Include/core_cm23.h → cube/Drivers/CMSIS/Include/core_cm23.h
View File

File diff suppressed because it is too large Load Diff

3882
stm32_test1/Drivers/CMSIS/Include/core_cm3.h → cube/Drivers/CMSIS/Include/core_cm3.h
View File

File diff suppressed because it is too large Load Diff

6004
stm32_test1/Drivers/CMSIS/Include/core_cm33.h → cube/Drivers/CMSIS/Include/core_cm33.h
View File

File diff suppressed because it is too large Load Diff

4258
stm32_test1/Drivers/CMSIS/Include/core_cm4.h → cube/Drivers/CMSIS/Include/core_cm4.h
View File

File diff suppressed because it is too large Load Diff

5342
stm32_test1/Drivers/CMSIS/Include/core_cm7.h → cube/Drivers/CMSIS/Include/core_cm7.h
View File

File diff suppressed because it is too large Load Diff

2044
stm32_test1/Drivers/CMSIS/Include/core_sc000.h → cube/Drivers/CMSIS/Include/core_sc000.h
View File

File diff suppressed because it is too large Load Diff

3830
stm32_test1/Drivers/CMSIS/Include/core_sc300.h → cube/Drivers/CMSIS/Include/core_sc300.h
View File

File diff suppressed because it is too large Load Diff

540
stm32_test1/Drivers/CMSIS/Include/mpu_armv7.h → cube/Drivers/CMSIS/Include/mpu_armv7.h
View File

@ -1,270 +1,270 @@
/****************************************************************************** /******************************************************************************
* @file mpu_armv7.h * @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU * @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4 * @version V5.0.4
* @date 10. January 2018 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV7_H #ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value /** MPU Region Base Address Register Value
* *
* \param Region The region to be configured, number 0 to 15. * \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region. * \param BaseAddress The base address for the region.
*/ */
#define ARM_MPU_RBAR(Region, BaseAddress) \ #define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \ ((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk)) (MPU_RBAR_VALID_Msk))
/** /**
* MPU Memory Access Attributes * MPU Memory Access Attributes
* *
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/ */
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/** /**
* MPU Region Attribute and Size Register Value * MPU Region Attribute and Size Register Value
* *
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters. * \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field. * \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K. * \param Size Region size of the region to be configured, for example 4K, 8K.
*/ */
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/** /**
* MPU Memory Access Attribute for strongly ordered memory. * MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b * - TEX: 000b
* - Shareable * - Shareable
* - Non-cacheable * - Non-cacheable
* - Non-bufferable * - Non-bufferable
*/ */
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/** /**
* MPU Memory Access Attribute for device memory. * MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable) * - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Non-cacheable * - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable) * - Bufferable (if shareable) or non-bufferable (if non-shareable)
* *
* \param IsShareable Configures the device memory as shareable or non-shareable. * \param IsShareable Configures the device memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/** /**
* MPU Memory Access Attribute for normal memory. * MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules) * - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable * - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules) * - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules) * - Bufferable or non-bufferable (reflecting inner cacheability rules)
* *
* \param OuterCp Configures the outer cache policy. * \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy. * \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable. * \param IsShareable Configures the memory as shareable or non-shareable.
*/ */
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/** /**
* MPU Memory Access Attribute non-cacheable policy. * MPU Memory Access Attribute non-cacheable policy.
*/ */
#define ARM_MPU_CACHEP_NOCACHE 0U #define ARM_MPU_CACHEP_NOCACHE 0U
/** /**
* MPU Memory Access Attribute write-back, write and read allocate policy. * MPU Memory Access Attribute write-back, write and read allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_WRA 1U #define ARM_MPU_CACHEP_WB_WRA 1U
/** /**
* MPU Memory Access Attribute write-through, no write allocate policy. * MPU Memory Access Attribute write-through, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WT_NWA 2U #define ARM_MPU_CACHEP_WT_NWA 2U
/** /**
* MPU Memory Access Attribute write-back, no write allocate policy. * MPU Memory Access Attribute write-back, no write allocate policy.
*/ */
#define ARM_MPU_CACHEP_WB_NWA 3U #define ARM_MPU_CACHEP_WB_NWA 3U
/** /**
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
} }
/** Disable the MPU. /** Disable the MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable(void) __STATIC_INLINE void ARM_MPU_Disable(void)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
/** Clear and disable the given MPU region. /** Clear and disable the given MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RASR = 0U; MPU->RASR = 0U;
} }
/** Configure an MPU region. /** Configure an MPU region.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{ {
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Configure the given MPU region. /** Configure the given MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rsar Value for RSAR register. * \param rsar Value for RSAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{ {
MPU->RNR = rnr; MPU->RNR = rnr;
MPU->RBAR = rbar; MPU->RBAR = rbar;
MPU->RASR = rasr; MPU->RASR = rasr;
} }
/** Memcopy with strictly ordered memory access, e.g. for register targets. /** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to. * \param dst Destination data is copied to.
* \param src Source data is copied from. * \param src Source data is copied from.
* \param len Amount of data words to be copied. * \param len Amount of data words to be copied.
*/ */
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
} }
/** Load the given number of MPU regions from a table. /** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) { while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES; table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES; cnt -= MPU_TYPE_RALIASES;
} }
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
} }
#endif #endif

666
stm32_test1/Drivers/CMSIS/Include/mpu_armv8.h → cube/Drivers/CMSIS/Include/mpu_armv8.h
View File

@ -1,333 +1,333 @@
/****************************************************************************** /******************************************************************************
* @file mpu_armv8.h * @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU * @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4 * @version V5.0.4
* @date 10. January 2018 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef ARM_MPU_ARMV8_H #ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */ /** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U ) #define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */ /** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner) /** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data. * \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy. * \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/ */
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U) #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U) #define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute /** \brief Memory Attribute
* \param O Outer memory attributes * \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/ */
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */ /** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U) #define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */ /** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U) #define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */ /** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U) #define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions /** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory. * \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/ */
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value /** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region. * \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region. * \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/ */
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \ ((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value /** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region. * \param IDX The attribute index to be associated with this memory region.
*/ */
#define ARM_MPU_RLAR(LIMIT, IDX) \ #define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \ ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk)) (MPU_RLAR_EN_Msk))
/** /**
* Struct for a single MPU Region * Struct for a single MPU Region
*/ */
typedef struct { typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t; } ARM_MPU_Region_t;
/** Enable the MPU. /** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
} }
/** Disable the MPU. /** Disable the MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable(void) __STATIC_INLINE void ARM_MPU_Disable(void)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Enable the Non-secure MPU. /** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions. * \param MPU_Control Default access permissions for unconfigured regions.
*/ */
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
} }
/** Disable the Non-secure MPU. /** Disable the Non-secure MPU.
*/ */
__STATIC_INLINE void ARM_MPU_Disable_NS(void) __STATIC_INLINE void ARM_MPU_Disable_NS(void)
{ {
__DSB(); __DSB();
__ISB(); __ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk #ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif #endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
} }
#endif #endif
/** Set the memory attribute encoding to the given MPU. /** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured. * \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{ {
const uint8_t reg = idx / 4U; const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U); const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos; const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index return; // invalid index
} }
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
} }
/** Set the memory attribute encoding. /** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{ {
ARM_MPU_SetMemAttrEx(MPU, idx, attr); ARM_MPU_SetMemAttrEx(MPU, idx, attr);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU. /** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7] * \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set. * \param attr The attribute value to be set.
*/ */
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{ {
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
} }
#endif #endif
/** Clear and disable the given MPU region of the given MPU. /** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used. * \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{ {
mpu->RNR = rnr; mpu->RNR = rnr;
mpu->RLAR = 0U; mpu->RLAR = 0U;
} }
/** Clear and disable the given MPU region. /** Clear and disable the given MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{ {
ARM_MPU_ClrRegionEx(MPU, rnr); ARM_MPU_ClrRegionEx(MPU, rnr);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region. /** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared. * \param rnr Region number to be cleared.
*/ */
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{ {
ARM_MPU_ClrRegionEx(MPU_NS, rnr); ARM_MPU_ClrRegionEx(MPU_NS, rnr);
} }
#endif #endif
/** Configure the given MPU region of the given MPU. /** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used. * \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
mpu->RNR = rnr; mpu->RNR = rnr;
mpu->RBAR = rbar; mpu->RBAR = rbar;
mpu->RLAR = rlar; mpu->RLAR = rlar;
} }
/** Configure the given MPU region. /** Configure the given MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Configure the given Non-secure MPU region. /** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured. * \param rnr Region number to be configured.
* \param rbar Value for RBAR register. * \param rbar Value for RBAR register.
* \param rlar Value for RLAR register. * \param rlar Value for RLAR register.
*/ */
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{ {
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
} }
#endif #endif
/** Memcopy with strictly ordered memory access, e.g. for register targets. /** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to. * \param dst Destination data is copied to.
* \param src Source data is copied from. * \param src Source data is copied from.
* \param len Amount of data words to be copied. * \param len Amount of data words to be copied.
*/ */
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{ {
uint32_t i; uint32_t i;
for (i = 0U; i < len; ++i) for (i = 0U; i < len; ++i)
{ {
dst[i] = src[i]; dst[i] = src[i];
} }
} }
/** Load the given number of MPU regions from a table to the given MPU. /** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used. * \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) { if (cnt == 1U) {
mpu->RNR = rnr; mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else { } else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase; mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset; uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c; table += c;
cnt -= c; cnt -= c;
rnrOffset = 0U; rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES; rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase; mpu->RNR = rnrBase;
} }
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
} }
} }
/** Load the given number of MPU regions from a table. /** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
ARM_MPU_LoadEx(MPU, rnr, table, cnt); ARM_MPU_LoadEx(MPU, rnr, table, cnt);
} }
#ifdef MPU_NS #ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU. /** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured. * \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table. * \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured. * \param cnt Amount of regions to be configured.
*/ */
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{ {
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
} }
#endif #endif
#endif #endif

140
stm32_test1/Drivers/CMSIS/Include/tz_context.h → cube/Drivers/CMSIS/Include/tz_context.h
View File

@ -1,70 +1,70 @@
/****************************************************************************** /******************************************************************************
* @file tz_context.h * @file tz_context.h
* @brief Context Management for Armv8-M TrustZone * @brief Context Management for Armv8-M TrustZone
* @version V1.0.1 * @version V1.0.1
* @date 10. January 2018 * @date 10. January 2018
******************************************************************************/ ******************************************************************************/
/* /*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved. * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the License); you may * Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License. * not use this file except in compliance with the License.
* You may obtain a copy of the License at * You may obtain a copy of the License at
* *
* www.apache.org/licenses/LICENSE-2.0 * www.apache.org/licenses/LICENSE-2.0
* *
* Unless required by applicable law or agreed to in writing, software * Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT * distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and * See the License for the specific language governing permissions and
* limitations under the License. * limitations under the License.
*/ */
#if defined ( __ICCARM__ ) #if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */ #pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__) #elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */ #pragma clang system_header /* treat file as system include file */
#endif #endif
#ifndef TZ_CONTEXT_H #ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H #define TZ_CONTEXT_H
#include <stdint.h> #include <stdint.h>
#ifndef TZ_MODULEID_T #ifndef TZ_MODULEID_T
#define TZ_MODULEID_T #define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process. /// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t; typedef uint32_t TZ_ModuleId_t;
#endif #endif
/// \details TZ Memory ID identifies an allocated memory slot. /// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t; typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system /// Initialize secure context memory system
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void); uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone /// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode /// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier /// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error /// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch) /// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch) /// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier /// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error) /// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H #endif // TZ_CONTEXT_H

7566
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
View File

File diff suppressed because it is too large Load Diff

716
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
View File

@ -1,358 +1,358 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal.h * @file stm32f1xx_hal.h
* @author MCD Application Team * @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL * @brief This file contains all the functions prototypes for the HAL
* module driver. * module driver.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_H #ifndef __STM32F1xx_HAL_H
#define __STM32F1xx_HAL_H #define __STM32F1xx_HAL_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_conf.h" #include "stm32f1xx_hal_conf.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup HAL /** @addtogroup HAL
* @{ * @{
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants /** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{ * @{
*/ */
/** @defgroup HAL_TICK_FREQ Tick Frequency /** @defgroup HAL_TICK_FREQ Tick Frequency
* @{ * @{
*/ */
typedef enum typedef enum
{ {
HAL_TICK_FREQ_10HZ = 100U, HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U, HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U, HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef; } HAL_TickFreqTypeDef;
/** /**
* @} * @}
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
extern __IO uint32_t uwTick; extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio; extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq; extern HAL_TickFreqTypeDef uwTickFreq;
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros /** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{ * @{
*/ */
/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
* @brief Freeze/Unfreeze Peripherals in Debug mode * @brief Freeze/Unfreeze Peripherals in Debug mode
* Note: On devices STM32F10xx8 and STM32F10xxB, * Note: On devices STM32F10xx8 and STM32F10xxB,
* STM32F101xC/D/E and STM32F103xC/D/E, * STM32F101xC/D/E and STM32F103xC/D/E,
* STM32F101xF/G and STM32F103xF/G * STM32F101xF/G and STM32F103xF/G
* STM32F10xx4 and STM32F10xx6 * STM32F10xx4 and STM32F10xx6
* Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
* debug mode (not accessible by the user software in normal mode). * debug mode (not accessible by the user software in normal mode).
* Refer to errata sheet of these devices for more details. * Refer to errata sheet of these devices for more details.
* @{ * @{
*/ */
/* Peripherals on APB1 */ /* Peripherals on APB1 */
/** /**
* @brief TIM2 Peripherals Debug mode * @brief TIM2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
/** /**
* @brief TIM3 Peripherals Debug mode * @brief TIM3 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
#if defined (DBGMCU_CR_DBG_TIM4_STOP) #if defined (DBGMCU_CR_DBG_TIM4_STOP)
/** /**
* @brief TIM4 Peripherals Debug mode * @brief TIM4 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM5_STOP) #if defined (DBGMCU_CR_DBG_TIM5_STOP)
/** /**
* @brief TIM5 Peripherals Debug mode * @brief TIM5 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM6_STOP) #if defined (DBGMCU_CR_DBG_TIM6_STOP)
/** /**
* @brief TIM6 Peripherals Debug mode * @brief TIM6 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM7_STOP) #if defined (DBGMCU_CR_DBG_TIM7_STOP)
/** /**
* @brief TIM7 Peripherals Debug mode * @brief TIM7 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM12_STOP) #if defined (DBGMCU_CR_DBG_TIM12_STOP)
/** /**
* @brief TIM12 Peripherals Debug mode * @brief TIM12 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM13_STOP) #if defined (DBGMCU_CR_DBG_TIM13_STOP)
/** /**
* @brief TIM13 Peripherals Debug mode * @brief TIM13 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM14_STOP) #if defined (DBGMCU_CR_DBG_TIM14_STOP)
/** /**
* @brief TIM14 Peripherals Debug mode * @brief TIM14 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
#endif #endif
/** /**
* @brief WWDG Peripherals Debug mode * @brief WWDG Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
/** /**
* @brief IWDG Peripherals Debug mode * @brief IWDG Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP) #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
/** /**
* @brief I2C1 Peripherals Debug mode * @brief I2C1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
/** /**
* @brief I2C2 Peripherals Debug mode * @brief I2C2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN1_STOP) #if defined (DBGMCU_CR_DBG_CAN1_STOP)
/** /**
* @brief CAN1 Peripherals Debug mode * @brief CAN1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_CAN2_STOP) #if defined (DBGMCU_CR_DBG_CAN2_STOP)
/** /**
* @brief CAN2 Peripherals Debug mode * @brief CAN2 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP) #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
#endif #endif
/* Peripherals on APB2 */ /* Peripherals on APB2 */
#if defined (DBGMCU_CR_DBG_TIM1_STOP) #if defined (DBGMCU_CR_DBG_TIM1_STOP)
/** /**
* @brief TIM1 Peripherals Debug mode * @brief TIM1 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM8_STOP) #if defined (DBGMCU_CR_DBG_TIM8_STOP)
/** /**
* @brief TIM8 Peripherals Debug mode * @brief TIM8 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM9_STOP) #if defined (DBGMCU_CR_DBG_TIM9_STOP)
/** /**
* @brief TIM9 Peripherals Debug mode * @brief TIM9 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM10_STOP) #if defined (DBGMCU_CR_DBG_TIM10_STOP)
/** /**
* @brief TIM10 Peripherals Debug mode * @brief TIM10 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM11_STOP) #if defined (DBGMCU_CR_DBG_TIM11_STOP)
/** /**
* @brief TIM11 Peripherals Debug mode * @brief TIM11 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM15_STOP) #if defined (DBGMCU_CR_DBG_TIM15_STOP)
/** /**
* @brief TIM15 Peripherals Debug mode * @brief TIM15 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM16_STOP) #if defined (DBGMCU_CR_DBG_TIM16_STOP)
/** /**
* @brief TIM16 Peripherals Debug mode * @brief TIM16 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
#endif #endif
#if defined (DBGMCU_CR_DBG_TIM17_STOP) #if defined (DBGMCU_CR_DBG_TIM17_STOP)
/** /**
* @brief TIM17 Peripherals Debug mode * @brief TIM17 Peripherals Debug mode
*/ */
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP) #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
#endif #endif
/** /**
* @} * @}
*/ */
/** @defgroup HAL_Private_Macros HAL Private Macros /** @defgroup HAL_Private_Macros HAL Private Macros
* @{ * @{
*/ */
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ)) ((FREQ) == HAL_TICK_FREQ_1KHZ))
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions /** @addtogroup HAL_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup HAL_Exported_Functions_Group1 /** @addtogroup HAL_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions ******************************/ /* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void); HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void); void HAL_MspInit(void);
void HAL_MspDeInit(void); void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/** /**
* @} * @}
*/ */
/** @addtogroup HAL_Exported_Functions_Group2 /** @addtogroup HAL_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
void HAL_IncTick(void); void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay); void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void); uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void); uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void); HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void); void HAL_SuspendTick(void);
void HAL_ResumeTick(void); void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void); uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void); uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void); uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void); uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void); uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGSleepMode(void); void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void); void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void); void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void); void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void); void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void); void HAL_DBGMCU_DisableDBGStandbyMode(void);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables /** @defgroup HAL_Private_Variables HAL Private Variables
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup HAL_Private_Constants HAL Private Constants /** @defgroup HAL_Private_Constants HAL Private Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_H */ #endif /* __STM32F1xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1003
cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h Normal file
View File

File diff suppressed because it is too large Load Diff

710
cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h Normal file
View File

@ -0,0 +1,710 @@
/**
******************************************************************************
* @file stm32f1xx_hal_adc_ex.h
* @author MCD Application Team
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_ADC_EX_H
#define __STM32F1xx_HAL_ADC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup ADCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
* @{
*/
/**
* @brief ADC Configuration injected Channel structure definition
* @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
*/
typedef struct
{
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
Refer to errata sheet of these devices for more details. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
This parameter can be a value of @ref ADC_sampling_times
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
To maintain JAUTO always enabled, DMA must be configured in circular mode.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
If set to external trigger source, triggering is on event rising edge.
This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Structure definition of ADC multimode
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
* State of ADCs of the common group must be: disabled.
*/
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
This parameter can be a value of @ref ADCEx_Common_mode
Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
The equivalences are:
- Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
- Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
}ADC_MultiModeTypeDef;
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
* @{
*/
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
* @{
*/
#define ADC_INJECTED_RANK_1 0x00000001U
#define ADC_INJECTED_RANK_2 0x00000002U
#define ADC_INJECTED_RANK_3 0x00000003U
#define ADC_INJECTED_RANK_4 0x00000004U
/**
* @}
*/
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
/**
* @}
*/
/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
* @{
*/
/*!< List of external triggers with generic trigger name, independently of */
/* ADC target, sorted by trigger name: */
/*!< External triggers of regular group for ADC1&ADC2 only */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
#if defined (STM32F103xE) || defined (STM32F103xG)
/*!< External triggers of regular group for ADC3 only */
#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
#endif /* STM32F103xE || defined STM32F103xG */
/*!< External triggers of regular group for all ADC instances */
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
/* To use it on ADC or ADC2, a remap of trigger must be done from */
/* EXTI line 11 to TIM8_TRGO with macro: */
/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
/* Note for internal constant value management: If TIM8_TRGO is available, */
/* its definition is set to value for ADC1&ADC2 by default and changed to */
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
/**
* @}
*/
/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
* @{
*/
/*!< List of external triggers with generic trigger name, independently of */
/* ADC target, sorted by trigger name: */
/*!< External triggers of injected group for ADC1&ADC2 only */
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#if defined (STM32F103xE) || defined (STM32F103xG)
/*!< External triggers of injected group for ADC3 only */
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
#endif /* STM32F103xE || defined STM32F103xG */
/*!< External triggers of injected group for all ADC instances */
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */
/* EXTI line 11 to TIM8_CC4 with macro: */
/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
/* Note for internal constant value management: If TIM8_CC4 is available, */
/* its definition is set to value for ADC1&ADC2 by default and changed to */
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
/**
* @}
*/
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
* @{
*/
#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
/**
* @}
*/
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
* @{
*/
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
* @{
*/
/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
/* instance is available on the selected device). */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
/* External triggers of regular group for ADC3 */
#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
#endif
/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
/**
* @}
*/
/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
* @{
*/
/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
/* instance is available on the selected device). */
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
/* External triggers of injected group for ADC3 */
#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
#endif /* STM32F103xE || defined STM32F103xG */
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
* @{
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */
/**
* @brief For devices with 3 ADCs: Defines the external trigger source
* for regular group according to ADC into common group ADC1&ADC2 or
* ADC3 (some triggers with same source have different value to
* be programmed into ADC EXTSEL bits of CR2 register).
* For devices with 2 ADCs or less: this macro makes no change.
* @param __HANDLE__: ADC handle
* @param __EXT_TRIG_CONV__: External trigger selected for regular group.
* @retval External trigger to be programmed into EXTSEL bits of CR2 register
*/
#if defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \
)? \
( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
)? \
(ADC3_EXTERNALTRIG_T8_TRGO) \
: \
(__EXT_TRIG_CONV__) \
) \
: \
(__EXT_TRIG_CONV__) \
)
#else
#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
(__EXT_TRIG_CONV__)
#endif /* STM32F103xE || STM32F103xG */
/**
* @brief For devices with 3 ADCs: Defines the external trigger source
* for injected group according to ADC into common group ADC1&ADC2 or
* ADC3 (some triggers with same source have different value to
* be programmed into ADC JEXTSEL bits of CR2 register).
* For devices with 2 ADCs or less: this macro makes no change.
* @param __HANDLE__: ADC handle
* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
* @retval External trigger to be programmed into JEXTSEL bits of CR2 register
*/
#if defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
(( (((__HANDLE__)->Instance) == ADC3) \
)? \
( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
)? \
(ADC3_EXTERNALTRIGINJEC_T8_CC4) \
: \
(__EXT_TRIG_INJECTCONV__) \
) \
: \
(__EXT_TRIG_INJECTCONV__) \
)
#else
#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
(__EXT_TRIG_INJECTCONV__)
#endif /* STM32F103xE || STM32F103xG */
/**
* @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
*/
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_DUALMOD) \
: \
(RESET) \
)
#else
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle
* @retval None
*/
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC2) \
)? \
((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
: \
(!RESET) \
)
#else
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
(!RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle
* @retval None
*/
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
(ADC1->CR1 & ADC_CR1_JAUTO) \
: \
(RESET) \
)
#else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
(RESET)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Set handle of the other ADC sharing the common multimode settings
* @param __HANDLE__: ADC handle
* @param __HANDLE_OTHER_ADC__: other ADC handle
* @retval None
*/
#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
((__HANDLE_OTHER_ADC__)->Instance = ADC2)
/**
* @brief Set handle of the ADC slave associated to the ADC master
* On STM32F1 devices, ADC slave is always ADC2 (this can be different
* on other STM32 devices)
* @param __HANDLE_MASTER__: ADC master handle
* @param __HANDLE_SLAVE__: ADC slave handle
* @retval None
*/
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
((__HANDLE_SLAVE__)->Instance = ADC2)
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
((CHANNEL) == ADC_INJECTED_RANK_2) || \
((CHANNEL) == ADC_INJECTED_RANK_3) || \
((CHANNEL) == ADC_INJECTED_RANK_4))
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
* @{
*/
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
/**
* @}
*/
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F101xE)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F101xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined (STM32F101xE)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined (STM32F101xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT) || \
((MODE) == ADC_DUALMODE_INTERLFAST) || \
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
((MODE) == ADC_DUALMODE_ALTERTRIG) )
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup ADCEx_Exported_Functions_Group1
* @{
*/
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @addtogroup ADCEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

820
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h
View File

@ -1,410 +1,410 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_cortex.h * @file stm32f1xx_hal_cortex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of CORTEX HAL module. * @brief Header file of CORTEX HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CORTEX_H #ifndef __STM32F1xx_HAL_CORTEX_H
#define __STM32F1xx_HAL_CORTEX_H #define __STM32F1xx_HAL_CORTEX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup CORTEX /** @addtogroup CORTEX
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types /** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{ * @{
*/ */
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure * @brief MPU Region initialization structure
* @{ * @{
*/ */
typedef struct typedef struct
{ {
uint8_t Enable; /*!< Specifies the status of the region. uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect. uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect. uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level. uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type. uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status. uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef; }MPU_Region_InitTypeDef;
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{ * @{
*/ */
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{ * @{
*/ */
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
4 bits for subpriority */ 4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
3 bits for subpriority */ 3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
2 bits for subpriority */ 2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
1 bits for subpriority */ 1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
0 bits for subpriority */ 0 bits for subpriority */
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{ * @{
*/ */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/** /**
* @} * @}
*/ */
#if (__MPU_PRESENT == 1) #if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{ * @{
*/ */
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{ * @{
*/ */
#define MPU_REGION_ENABLE ((uint8_t)0x01) #define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00) #define MPU_REGION_DISABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{ * @{
*/ */
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{ * @{
*/ */
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{ * @{
*/ */
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{ * @{
*/ */
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{ * @{
*/ */
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{ * @{
*/ */
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{ * @{
*/ */
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/** /**
* @} * @}
*/ */
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{ * @{
*/ */
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/** /**
* @} * @}
*/ */
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Exported Macros -----------------------------------------------------------*/ /* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions /** @addtogroup CORTEX_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup CORTEX_Exported_Functions_Group1 /** @addtogroup CORTEX_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void); void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/** /**
* @} * @}
*/ */
/** @addtogroup CORTEX_Exported_Functions_Group2 /** @addtogroup CORTEX_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void); uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void); void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void); void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{ * @{
*/ */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \ ((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \ ((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4)) ((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1U) #if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE)) ((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2)) ((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \ ((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \ ((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO)) ((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \ ((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \ ((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \ ((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \ ((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \ ((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \ ((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7)) ((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \ ((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \ ((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \ ((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \ ((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \ ((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \ ((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \ ((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \ ((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \ ((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \ ((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \ ((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \ ((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \ ((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \ ((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \ ((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \ ((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \ ((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \ ((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \ ((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \ ((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \ ((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \ ((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \ ((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \ ((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB)) ((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_CORTEX_H */ #endif /* __STM32F1xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

420
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h
View File

@ -1,210 +1,210 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_def.h * @file stm32f1xx_hal_def.h
* @author MCD Application Team * @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and * @brief This file contains HAL common defines, enumeration, macros and
* structures definitions. * structures definitions.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DEF #ifndef __STM32F1xx_HAL_DEF
#define __STM32F1xx_HAL_DEF #define __STM32F1xx_HAL_DEF
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h" #include "stm32f1xx.h"
#include "Legacy/stm32_hal_legacy.h" #include "Legacy/stm32_hal_legacy.h"
#include <stddef.h> #include <stddef.h>
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** /**
* @brief HAL Status structures definition * @brief HAL Status structures definition
*/ */
typedef enum typedef enum
{ {
HAL_OK = 0x00U, HAL_OK = 0x00U,
HAL_ERROR = 0x01U, HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U, HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef; } HAL_StatusTypeDef;
/** /**
* @brief HAL Lock structures definition * @brief HAL Lock structures definition
*/ */
typedef enum typedef enum
{ {
HAL_UNLOCKED = 0x00U, HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U HAL_LOCKED = 0x01U
} HAL_LockTypeDef; } HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U) #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != 0U)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \ do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \ (__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U) } while(0U)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
/** @brief Reset the Handle's State field. /** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle. * @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose: * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter * - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field. * to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function * Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed * HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed). * (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling * - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function * In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware. * HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None * @retval None
*/ */
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U) #if (USE_RTOS == 1U)
/* Reserved for future use */ /* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release" #error "USE_RTOS should be 0 in the current HAL release"
#else #else
#define __HAL_LOCK(__HANDLE__) \ #define __HAL_LOCK(__HANDLE__) \
do{ \ do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \ if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \ { \
return HAL_BUSY; \ return HAL_BUSY; \
} \ } \
else \ else \
{ \ { \
(__HANDLE__)->Lock = HAL_LOCKED; \ (__HANDLE__)->Lock = HAL_LOCKED; \
} \ } \
}while (0U) }while (0U)
#define __HAL_UNLOCK(__HANDLE__) \ #define __HAL_UNLOCK(__HANDLE__) \
do{ \ do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \ (__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U) }while (0U)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif #endif
#ifndef __packed #ifndef __packed
#define __packed __attribute__((packed)) #define __packed __attribute__((packed))
#endif #endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
#ifndef __packed #ifndef __packed
#define __packed __attribute__((__packed__)) #define __packed __attribute__((__packed__))
#endif /* __packed */ #endif /* __packed */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif #endif
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif #endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#else #else
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END #define __ALIGN_END
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/ #if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4) #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */ #elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
#endif /* __CC_ARM */ #endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */ #endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */ #endif /* __GNUC__ */
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6 /* ARM Compiler V4/V5 and V6
-------------------------- --------------------------
RAM functions are defined using the toolchain options. RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module. Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const' Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM. area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target' Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog. dialog.
*/ */
#define __RAM_FUNC #define __RAM_FUNC
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc". RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/ */
#define __RAM_FUNC __ramfunc #define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
/* GNU Compiler /* GNU Compiler
------------ ------------
RAM functions are defined using a specific toolchain attribute RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))". "__attribute__((section(".RamFunc")))".
*/ */
#define __RAM_FUNC __attribute__((section(".RamFunc"))) #define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif #endif
/** /**
* @brief __NOINLINE definition * @brief __NOINLINE definition
*/ */
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler /* ARM V4/V5 and V6 & GNU Compiler
------------------------------- -------------------------------
*/ */
#define __NOINLINE __attribute__ ( (noinline) ) #define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
/* ICCARM Compiler /* ICCARM Compiler
--------------- ---------------
*/ */
#define __NOINLINE _Pragma("optimize = no_inline") #define __NOINLINE _Pragma("optimize = no_inline")
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* ___STM32F1xx_HAL_DEF */ #endif /* ___STM32F1xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

914
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h
View File

@ -1,457 +1,457 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_dma.h * @file stm32f1xx_hal_dma.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of DMA HAL module. * @brief Header file of DMA HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_H #ifndef __STM32F1xx_HAL_DMA_H
#define __STM32F1xx_HAL_DMA_H #define __STM32F1xx_HAL_DMA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup DMA /** @addtogroup DMA
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types /** @defgroup DMA_Exported_Types DMA Exported Types
* @{ * @{
*/ */
/** /**
* @brief DMA Configuration Structure definition * @brief DMA Configuration Structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory. from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */ This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */ This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */ This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width. uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */ This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory @note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */ data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */ This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef; } DMA_InitTypeDef;
/** /**
* @brief HAL DMA State structures definition * @brief HAL DMA State structures definition
*/ */
typedef enum typedef enum
{ {
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
}HAL_DMA_StateTypeDef; }HAL_DMA_StateTypeDef;
/** /**
* @brief HAL DMA Error Code structure definition * @brief HAL DMA Error Code structure definition
*/ */
typedef enum typedef enum
{ {
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef; }HAL_DMA_LevelCompleteTypeDef;
/** /**
* @brief HAL DMA Callback ID structure definition * @brief HAL DMA Callback ID structure definition
*/ */
typedef enum typedef enum
{ {
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
}HAL_DMA_CallbackIDTypeDef; }HAL_DMA_CallbackIDTypeDef;
/** /**
* @brief DMA handle Structure definition * @brief DMA handle Structure definition
*/ */
typedef struct __DMA_HandleTypeDef typedef struct __DMA_HandleTypeDef
{ {
DMA_Channel_TypeDef *Instance; /*!< Register base address */ DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */ DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */ HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */ void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */ __IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */ uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef; } DMA_HandleTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants /** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{ * @{
*/ */
/** @defgroup DMA_Error_Code DMA Error Code /** @defgroup DMA_Error_Code DMA Error Code
* @{ * @{
*/ */
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{ * @{
*/ */
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{ * @{
*/ */
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{ * @{
*/ */
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{ * @{
*/ */
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Memory_data_size DMA Memory data size /** @defgroup DMA_Memory_data_size DMA Memory data size
* @{ * @{
*/ */
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_mode DMA mode /** @defgroup DMA_mode DMA mode
* @{ * @{
*/ */
#define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_Priority_level DMA Priority level /** @defgroup DMA_Priority_level DMA Priority level
* @{ * @{
*/ */
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/** /**
* @} * @}
*/ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{ * @{
*/ */
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/** /**
* @} * @}
*/ */
/** @defgroup DMA_flag_definitions DMA flag definitions /** @defgroup DMA_flag_definitions DMA flag definitions
* @{ * @{
*/ */
#define DMA_FLAG_GL1 0x00000001U #define DMA_FLAG_GL1 0x00000001U
#define DMA_FLAG_TC1 0x00000002U #define DMA_FLAG_TC1 0x00000002U
#define DMA_FLAG_HT1 0x00000004U #define DMA_FLAG_HT1 0x00000004U
#define DMA_FLAG_TE1 0x00000008U #define DMA_FLAG_TE1 0x00000008U
#define DMA_FLAG_GL2 0x00000010U #define DMA_FLAG_GL2 0x00000010U
#define DMA_FLAG_TC2 0x00000020U #define DMA_FLAG_TC2 0x00000020U
#define DMA_FLAG_HT2 0x00000040U #define DMA_FLAG_HT2 0x00000040U
#define DMA_FLAG_TE2 0x00000080U #define DMA_FLAG_TE2 0x00000080U
#define DMA_FLAG_GL3 0x00000100U #define DMA_FLAG_GL3 0x00000100U
#define DMA_FLAG_TC3 0x00000200U #define DMA_FLAG_TC3 0x00000200U
#define DMA_FLAG_HT3 0x00000400U #define DMA_FLAG_HT3 0x00000400U
#define DMA_FLAG_TE3 0x00000800U #define DMA_FLAG_TE3 0x00000800U
#define DMA_FLAG_GL4 0x00001000U #define DMA_FLAG_GL4 0x00001000U
#define DMA_FLAG_TC4 0x00002000U #define DMA_FLAG_TC4 0x00002000U
#define DMA_FLAG_HT4 0x00004000U #define DMA_FLAG_HT4 0x00004000U
#define DMA_FLAG_TE4 0x00008000U #define DMA_FLAG_TE4 0x00008000U
#define DMA_FLAG_GL5 0x00010000U #define DMA_FLAG_GL5 0x00010000U
#define DMA_FLAG_TC5 0x00020000U #define DMA_FLAG_TC5 0x00020000U
#define DMA_FLAG_HT5 0x00040000U #define DMA_FLAG_HT5 0x00040000U
#define DMA_FLAG_TE5 0x00080000U #define DMA_FLAG_TE5 0x00080000U
#define DMA_FLAG_GL6 0x00100000U #define DMA_FLAG_GL6 0x00100000U
#define DMA_FLAG_TC6 0x00200000U #define DMA_FLAG_TC6 0x00200000U
#define DMA_FLAG_HT6 0x00400000U #define DMA_FLAG_HT6 0x00400000U
#define DMA_FLAG_TE6 0x00800000U #define DMA_FLAG_TE6 0x00800000U
#define DMA_FLAG_GL7 0x01000000U #define DMA_FLAG_GL7 0x01000000U
#define DMA_FLAG_TC7 0x02000000U #define DMA_FLAG_TC7 0x02000000U
#define DMA_FLAG_HT7 0x04000000U #define DMA_FLAG_HT7 0x04000000U
#define DMA_FLAG_TE7 0x08000000U #define DMA_FLAG_TE7 0x08000000U
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macros -----------------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros /** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{ * @{
*/ */
/** @brief Reset DMA handle state. /** @brief Reset DMA handle state.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/** /**
* @brief Enable the specified DMA Channel. * @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/** /**
* @brief Disable the specified DMA Channel. * @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
* @brief Enables the specified DMA Channel interrupts. * @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None * @retval None
*/ */
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
/** /**
* @brief Disable the specified DMA Channel interrupts. * @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None * @retval None
*/ */
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
/** /**
* @brief Check whether the specified DMA Channel interrupt is enabled or not. * @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check. * @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET). * @retval The state of DMA_IT (SET or RESET).
*/ */
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** /**
* @brief Return the number of remaining data units in the current DMA Channel transfer. * @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer. * @retval The number of remaining data units in the current DMA Channel transfer.
*/ */
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/** /**
* @} * @}
*/ */
/* Include DMA HAL Extension module */ /* Include DMA HAL Extension module */
#include "stm32f1xx_hal_dma_ex.h" #include "stm32f1xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions /** @addtogroup DMA_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup DMA_Exported_Functions_Group1 /** @addtogroup DMA_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/** @addtogroup DMA_Exported_Functions_Group2 /** @addtogroup DMA_Exported_Functions_Group2
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/** /**
* @} * @}
*/ */
/** @addtogroup DMA_Exported_Functions_Group3 /** @addtogroup DMA_Exported_Functions_Group3
* @{ * @{
*/ */
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros /** @defgroup DMA_Private_Macros DMA Private Macros
* @{ * @{
*/ */
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY)) ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE)) ((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE)) ((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD)) ((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD )) ((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR)) ((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_DMA_H */ #endif /* __STM32F1xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

554
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h
View File

@ -1,277 +1,277 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_dma_ex.h * @file stm32f1xx_hal_dma_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of DMA HAL extension module. * @brief Header file of DMA HAL extension module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_EX_H #ifndef __STM32F1xx_HAL_DMA_EX_H
#define __STM32F1xx_HAL_DMA_EX_H #define __STM32F1xx_HAL_DMA_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup DMAEx DMAEx /** @defgroup DMAEx DMAEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
* @{ * @{
*/ */
/* Interrupt & Flag management */ /* Interrupt & Flag management */
#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ #if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
* @{ * @{
*/ */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5) DMA_FLAG_TC5)
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5) DMA_FLAG_HT5)
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5) DMA_FLAG_TE5)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5) DMA_FLAG_GL5)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__))) (DMA1->ISR & (__FLAG__)))
/** /**
* @brief Clears the DMA Channel pending flags. * @brief Clears the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None * @retval None
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__))) (DMA1->IFCR = (__FLAG__)))
/** /**
* @} * @}
*/ */
#else #else
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
* @{ * @{
*/ */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7) DMA_FLAG_TC7)
/** /**
* @brief Return the current DMA Channel half transfer complete flag. * @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7) DMA_FLAG_HT7)
/** /**
* @brief Return the current DMA Channel transfer error flag. * @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7) DMA_FLAG_TE7)
/** /**
* @brief Return the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7) DMA_FLAG_GL7)
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag. * @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag. * Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/** /**
* @brief Clear the DMA Channel pending flags. * @brief Clear the DMA Channel pending flags.
* @param __HANDLE__: DMA handle * @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag * @arg DMA_FLAG_TEx: Transfer error flag
* @arg DMA_FLAG_GLx: Global interrupt flag * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag. * Where x can be 1_7 to select the DMA Channel flag.
* @retval None * @retval None
*/ */
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/** /**
* @} * @}
*/ */
#endif #endif
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
/* STM32F103xG || STM32F105xC || STM32F107xC */ /* STM32F103xG || STM32F105xC || STM32F107xC */
#endif /* __STM32F1xx_HAL_DMA_H */ #endif /* __STM32F1xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

640
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h
View File

@ -1,320 +1,320 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_exti.h * @file stm32f1xx_hal_exti.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of EXTI HAL module. * @brief Header file of EXTI HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_EXTI_H #ifndef STM32F1xx_HAL_EXTI_H
#define STM32F1xx_HAL_EXTI_H #define STM32F1xx_HAL_EXTI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup EXTI EXTI /** @defgroup EXTI EXTI
* @brief EXTI HAL module driver * @brief EXTI HAL module driver
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types /** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{ * @{
*/ */
/** /**
* @brief HAL EXTI common Callback ID enumeration definition * @brief HAL EXTI common Callback ID enumeration definition
*/ */
typedef enum typedef enum
{ {
HAL_EXTI_COMMON_CB_ID = 0x00U HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef; } EXTI_CallbackIDTypeDef;
/** /**
* @brief EXTI Handle structure definition * @brief EXTI Handle structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t Line; /*!< Exti line number */ uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */ void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef; } EXTI_HandleTypeDef;
/** /**
* @brief EXTI Configuration structure definition * @brief EXTI Configuration structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t Line; /*!< The Exti line to be configured. This parameter uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */ can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core. uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */ This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */ can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */ can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef; } EXTI_ConfigTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants /** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{ * @{
*/ */
/** @defgroup EXTI_Line EXTI Line /** @defgroup EXTI_Line EXTI Line
* @{ * @{
*/ */
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ #define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ #define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ #define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ #define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ #define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ #define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ #define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ #define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ #define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ #define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ #define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ #define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ #define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ #define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ #define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ #define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#if defined(EXTI_IMR_IM18) #if defined(EXTI_IMR_IM18)
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */ #define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Wakeup from suspend event */
#endif /* EXTI_IMR_IM18 */ #endif /* EXTI_IMR_IM18 */
#if defined(EXTI_IMR_IM19) #if defined(EXTI_IMR_IM19)
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#endif /* EXTI_IMR_IM19 */ #endif /* EXTI_IMR_IM19 */
/** /**
* @} * @}
*/ */
/** @defgroup EXTI_Mode EXTI Mode /** @defgroup EXTI_Mode EXTI Mode
* @{ * @{
*/ */
#define EXTI_MODE_NONE 0x00000000u #define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u #define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u #define EXTI_MODE_EVENT 0x00000002u
/** /**
* @} * @}
*/ */
/** @defgroup EXTI_Trigger EXTI Trigger /** @defgroup EXTI_Trigger EXTI Trigger
* @{ * @{
*/ */
#define EXTI_TRIGGER_NONE 0x00000000u #define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u #define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u #define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) #define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/** /**
* @} * @}
*/ */
/** @defgroup EXTI_GPIOSel EXTI GPIOSel /** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief * @brief
* @{ * @{
*/ */
#define EXTI_GPIOA 0x00000000u #define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u #define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u #define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u #define EXTI_GPIOD 0x00000003u
#if defined (GPIOE) #if defined (GPIOE)
#define EXTI_GPIOE 0x00000004u #define EXTI_GPIOE 0x00000004u
#endif /* GPIOE */ #endif /* GPIOE */
#if defined (GPIOF) #if defined (GPIOF)
#define EXTI_GPIOF 0x00000005u #define EXTI_GPIOF 0x00000005u
#endif /* GPIOF */ #endif /* GPIOF */
#if defined (GPIOG) #if defined (GPIOG)
#define EXTI_GPIOG 0x00000006u #define EXTI_GPIOG 0x00000006u
#endif /* GPIOG */ #endif /* GPIOG */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros /** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private constants --------------------------------------------------------*/ /* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants /** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{ * @{
*/ */
/** /**
* @brief EXTI Line property definition * @brief EXTI Line property definition
*/ */
#define EXTI_PROPERTY_SHIFT 24u #define EXTI_PROPERTY_SHIFT 24u
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) #define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) #define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) #define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
/** /**
* @brief EXTI bit usage * @brief EXTI bit usage
*/ */
#define EXTI_PIN_MASK 0x0000001Fu #define EXTI_PIN_MASK 0x0000001Fu
/** /**
* @brief EXTI Mask for interrupt & event mode * @brief EXTI Mask for interrupt & event mode
*/ */
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) #define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/** /**
* @brief EXTI Mask for trigger possibilities * @brief EXTI Mask for trigger possibilities
*/ */
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) #define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/** /**
* @brief EXTI Line number * @brief EXTI Line number
*/ */
#if defined(EXTI_IMR_IM19) #if defined(EXTI_IMR_IM19)
#define EXTI_LINE_NB 20UL #define EXTI_LINE_NB 20UL
#elif defined(EXTI_IMR_IM18) #elif defined(EXTI_IMR_IM18)
#define EXTI_LINE_NB 19UL #define EXTI_LINE_NB 19UL
#else /* EXTI_IMR_IM17 */ #else /* EXTI_IMR_IM17 */
#define EXTI_LINE_NB 18UL #define EXTI_LINE_NB 18UL
#endif /* EXTI_IMR_IM19 */ #endif /* EXTI_IMR_IM19 */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros /** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{ * @{
*/ */
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ #define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ #define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) #define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) #define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (GPIOG) #if defined (GPIOG)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \ ((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG)) ((__PORT__) == EXTI_GPIOG))
#elif defined (GPIOF) #elif defined (GPIOF)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF)) ((__PORT__) == EXTI_GPIOF))
#elif defined (GPIOE) #elif defined (GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE)) ((__PORT__) == EXTI_GPIOE))
#else #else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD)) ((__PORT__) == EXTI_GPIOD))
#endif /* GPIOG */ #endif /* GPIOG */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions /** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions * @brief EXTI Exported Functions
* @{ * @{
*/ */
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions /** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions * @brief Configuration functions
* @{ * @{
*/ */
/* Configuration functions ****************************************************/ /* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/** /**
* @} * @}
*/ */
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions /** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions * @brief IO operation functions
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32F1xx_HAL_EXTI_H */ #endif /* STM32F1xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

656
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h
View File

@ -1,328 +1,328 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_flash.h * @file stm32f1xx_hal_flash.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of Flash HAL module. * @brief Header file of Flash HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_FLASH_H #ifndef __STM32F1xx_HAL_FLASH_H
#define __STM32F1xx_HAL_FLASH_H #define __STM32F1xx_HAL_FLASH_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup FLASH /** @addtogroup FLASH
* @{ * @{
*/ */
/** @addtogroup FLASH_Private_Constants /** @addtogroup FLASH_Private_Constants
* @{ * @{
*/ */
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Private_Macros /** @addtogroup FLASH_Private_Macros
* @{ * @{
*/ */
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1) || \ ((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2)) ((__LATENCY__) == FLASH_LATENCY_2))
#else #else
#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0) #define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** /**
* @} * @}
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types /** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{ * @{
*/ */
/** /**
* @brief FLASH Procedure structure definition * @brief FLASH Procedure structure definition
*/ */
typedef enum typedef enum
{ {
FLASH_PROC_NONE = 0U, FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U, FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U, FLASH_PROC_MASSERASE = 2U,
FLASH_PROC_PROGRAMHALFWORD = 3U, FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U, FLASH_PROC_PROGRAMWORD = 4U,
FLASH_PROC_PROGRAMDOUBLEWORD = 5U FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef; } FLASH_ProcedureTypeDef;
/** /**
* @brief FLASH handle Structure definition * @brief FLASH handle Structure definition
*/ */
typedef struct typedef struct
{ {
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */ __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
HAL_LockTypeDef Lock; /*!< FLASH locking object */ HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code __IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */ This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef; } FLASH_ProcessTypeDef;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{ * @{
*/ */
/** @defgroup FLASH_Error_Codes FLASH Error Codes /** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{ * @{
*/ */
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ #define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
/** /**
* @} * @}
*/ */
/** @defgroup FLASH_Type_Program FLASH Type Program /** @defgroup FLASH_Type_Program FLASH Type Program
* @{ * @{
*/ */
#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/ #define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/ #define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
/** /**
* @} * @}
*/ */
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
/** @defgroup FLASH_Latency FLASH Latency /** @defgroup FLASH_Latency FLASH Latency
* @{ * @{
*/ */
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */ #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
/** /**
* @} * @}
*/ */
#else #else
/** @defgroup FLASH_Latency FLASH Latency /** @defgroup FLASH_Latency FLASH Latency
* @{ * @{
*/ */
#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
/** /**
* @} * @}
*/ */
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features * @brief macros to control FLASH features
* @{ * @{
*/ */
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle /** @defgroup FLASH_Half_Cycle FLASH Half Cycle
* @brief macros to handle FLASH half cycle * @brief macros to handle FLASH half cycle
* @{ * @{
*/ */
/** /**
* @brief Enable the FLASH half cycle access. * @brief Enable the FLASH half cycle access.
* @note half cycle access can only be used with a low-frequency clock of less than * @note half cycle access can only be used with a low-frequency clock of less than
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA) #define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
/** /**
* @brief Disable the FLASH half cycle access. * @brief Disable the FLASH half cycle access.
* @note half cycle access can only be used with a low-frequency clock of less than * @note half cycle access can only be used with a low-frequency clock of less than
8 MHz that can be obtained with the use of HSI or HSE but not of PLL. 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA)) #define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
/** /**
* @} * @}
*/ */
#if defined(FLASH_ACR_LATENCY) #if defined(FLASH_ACR_LATENCY)
/** @defgroup FLASH_EM_Latency FLASH Latency /** @defgroup FLASH_EM_Latency FLASH Latency
* @brief macros to handle FLASH Latency * @brief macros to handle FLASH Latency
* @{ * @{
*/ */
/** /**
* @brief Set the FLASH Latency. * @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency * @param __LATENCY__ FLASH Latency
* The value of this parameter depend on device used within the same series * The value of this parameter depend on device used within the same series
* @retval None * @retval None
*/ */
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) #define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
/** /**
* @brief Get the FLASH Latency. * @brief Get the FLASH Latency.
* @retval FLASH Latency * @retval FLASH Latency
* The value of this parameter depend on device used within the same series * The value of this parameter depend on device used within the same series
*/ */
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/** /**
* @} * @}
*/ */
#endif /* FLASH_ACR_LATENCY */ #endif /* FLASH_ACR_LATENCY */
/** @defgroup FLASH_Prefetch FLASH Prefetch /** @defgroup FLASH_Prefetch FLASH Prefetch
* @brief macros to handle FLASH Prefetch buffer * @brief macros to handle FLASH Prefetch buffer
* @{ * @{
*/ */
/** /**
* @brief Enable the FLASH prefetch buffer. * @brief Enable the FLASH prefetch buffer.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
/** /**
* @brief Disable the FLASH prefetch buffer. * @brief Disable the FLASH prefetch buffer.
* @retval None * @retval None
*/ */
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Include FLASH HAL Extended module */ /* Include FLASH HAL Extended module */
#include "stm32f1xx_hal_flash_ex.h" #include "stm32f1xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions /** @addtogroup FLASH_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup FLASH_Exported_Functions_Group1 /** @addtogroup FLASH_Exported_Functions_Group1
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler function */ /* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void); void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */ /* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Exported_Functions_Group2 /** @addtogroup FLASH_Exported_Functions_Group2
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
void HAL_FLASH_OB_Launch(void); void HAL_FLASH_OB_Launch(void);
/** /**
* @} * @}
*/ */
/** @addtogroup FLASH_Exported_Functions_Group3 /** @addtogroup FLASH_Exported_Functions_Group3
* @{ * @{
*/ */
/* Peripheral State and Error functions ***************************************/ /* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void); uint32_t HAL_FLASH_GetError(void);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private function -------------------------------------------------*/ /* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions /** @addtogroup FLASH_Private_Functions
* @{ * @{
*/ */
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#if defined(FLASH_BANK2_END) #if defined(FLASH_BANK2_END)
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout); HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
#endif /* FLASH_BANK2_END */ #endif /* FLASH_BANK2_END */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_FLASH_H */ #endif /* __STM32F1xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1572
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h
View File

File diff suppressed because it is too large Load Diff

616
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h
View File

@ -1,308 +1,308 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_gpio.h * @file stm32f1xx_hal_gpio.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of GPIO HAL module. * @brief Header file of GPIO HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_GPIO_H #ifndef STM32F1xx_HAL_GPIO_H
#define STM32F1xx_HAL_GPIO_H #define STM32F1xx_HAL_GPIO_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup GPIO /** @addtogroup GPIO
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types /** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{ * @{
*/ */
/** /**
* @brief GPIO Init structure definition * @brief GPIO Init structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */ This parameter can be any value of @ref GPIO_pins_define */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins. uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode_define */ This parameter can be a value of @ref GPIO_mode_define */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull_define */ This parameter can be a value of @ref GPIO_pull_define */
uint32_t Speed; /*!< Specifies the speed for the selected pins. uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */ This parameter can be a value of @ref GPIO_speed_define */
} GPIO_InitTypeDef; } GPIO_InitTypeDef;
/** /**
* @brief GPIO Bit SET and Bit RESET enumeration * @brief GPIO Bit SET and Bit RESET enumeration
*/ */
typedef enum typedef enum
{ {
GPIO_PIN_RESET = 0u, GPIO_PIN_RESET = 0u,
GPIO_PIN_SET GPIO_PIN_SET
} GPIO_PinState; } GPIO_PinState;
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants /** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{ * @{
*/ */
/** @defgroup GPIO_pins_define GPIO pins define /** @defgroup GPIO_pins_define GPIO pins define
* @{ * @{
*/ */
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */ #define GPIO_PIN_MASK 0x0000FFFFu /* PIN mask for assert test */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_mode_define GPIO mode define /** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode * @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ * Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode * - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection * - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event * - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain) * - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog) * - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{ * @{
*/ */
#define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */ #define GPIO_MODE_INPUT 0x00000000u /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_PP 0x00000001u /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */ #define GPIO_MODE_OUTPUT_OD 0x00000011u /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_PP 0x00000002u /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_OD 0x00000012u /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
#define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */ #define GPIO_MODE_ANALOG 0x00000003u /*!< Analog Mode */
#define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_RISING 0x10110000u /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_FALLING 0x10210000u /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING 0x10310000u /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_RISING 0x10120000u /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_FALLING 0x10220000u /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING 0x10320000u /*!< External Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_speed_define GPIO speed define /** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency * @brief GPIO Output Maximum frequency
* @{ * @{
*/ */
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
/** /**
* @} * @}
*/ */
/** @defgroup GPIO_pull_define GPIO pull define /** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation * @brief GPIO Pull-Up or Pull-Down Activation
* @{ * @{
*/ */
#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ #define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ #define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ #define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros /** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{ * @{
*/ */
/** /**
* @brief Checks whether the specified EXTI line flag is set or not. * @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check. * @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/** /**
* @brief Clears the EXTI's line pending flags. * @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/** /**
* @brief Checks whether the specified EXTI line is asserted or not. * @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET). * @retval The new state of __EXTI_LINE__ (SET or RESET).
*/ */
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/** /**
* @brief Clears the EXTI's line pending bits. * @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear. * @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/** /**
* @brief Generates a Software interrupt on selected EXTI line. * @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check. * @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15) * This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None * @retval None
*/ */
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/** /**
* @} * @}
*/ */
/* Include GPIO HAL Extension module */ /* Include GPIO HAL Extension module */
#include "stm32f1xx_hal_gpio_ex.h" #include "stm32f1xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions /** @addtogroup GPIO_Exported_Functions
* @{ * @{
*/ */
/** @addtogroup GPIO_Exported_Functions_Group1 /** @addtogroup GPIO_Exported_Functions_Group1
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/** /**
* @} * @}
*/ */
/** @addtogroup GPIO_Exported_Functions_Group2 /** @addtogroup GPIO_Exported_Functions_Group2
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Private types -------------------------------------------------------------*/ /* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants /** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros /** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{ * @{
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u)) #define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00u) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
((MODE) == GPIO_MODE_AF_PP) ||\ ((MODE) == GPIO_MODE_AF_PP) ||\
((MODE) == GPIO_MODE_AF_OD) ||\ ((MODE) == GPIO_MODE_AF_OD) ||\
((MODE) == GPIO_MODE_IT_RISING) ||\ ((MODE) == GPIO_MODE_IT_RISING) ||\
((MODE) == GPIO_MODE_IT_FALLING) ||\ ((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\ ((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG)) ((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN)) ((PULL) == GPIO_PULLDOWN))
/** /**
* @} * @}
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions GPIO Private Functions /** @defgroup GPIO_Private_Functions GPIO Private Functions
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32F1xx_HAL_GPIO_H */ #endif /* STM32F1xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1788
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h
View File

File diff suppressed because it is too large Load Diff

776
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h
View File

@ -1,388 +1,388 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_pwr.h * @file stm32f1xx_hal_pwr.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of PWR HAL module. * @brief Header file of PWR HAL module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_PWR_H #ifndef __STM32F1xx_HAL_PWR_H
#define __STM32F1xx_HAL_PWR_H #define __STM32F1xx_HAL_PWR_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup PWR /** @addtogroup PWR
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types /** @defgroup PWR_Exported_Types PWR Exported Types
* @{ * @{
*/ */
/** /**
* @brief PWR PVD configuration structure definition * @brief PWR PVD configuration structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */ This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */ This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef; }PWR_PVDTypeDef;
/** /**
* @} * @}
*/ */
/* Internal constants --------------------------------------------------------*/ /* Internal constants --------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants /** @addtogroup PWR_Private_Constants
* @{ * @{
*/ */
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/** /**
* @} * @}
*/ */
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants /** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{ * @{
*/ */
/** @defgroup PWR_PVD_detection_level PWR PVD detection level /** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{ * @{
*/ */
#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
/** /**
* @} * @}
*/ */
/** @defgroup PWR_PVD_Mode PWR PVD Mode /** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{ * @{
*/ */
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{ * @{
*/ */
#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{ * @{
*/ */
#define PWR_MAINREGULATOR_ON 0x00000000U #define PWR_MAINREGULATOR_ON 0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
/** /**
* @} * @}
*/ */
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{ * @{
*/ */
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{ * @{
*/ */
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
/** /**
* @} * @}
*/ */
/** @defgroup PWR_Flag PWR Flag /** @defgroup PWR_Flag PWR Flag
* @{ * @{
*/ */
#define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_PVDO PWR_CSR_PVDO
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros /** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{ * @{
*/ */
/** @brief Check PWR flag is set or not. /** @brief Check PWR flag is set or not.
* @param __FLAG__: specifies the flag to check. * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm * was received from the WKUP pin or from the RTC alarm
* An additional wakeup event is detected if the WKUP pin is enabled * An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high. * (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode. * resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset * For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set. * until the PVDE bit is set.
* @retval The new state of __FLAG__ (TRUE or FALSE). * @retval The new state of __FLAG__ (TRUE or FALSE).
*/ */
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the PWR's pending flags. /** @brief Clear the PWR's pending flags.
* @param __FLAG__: specifies the flag to clear. * @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag * @arg PWR_FLAG_SB: StandBy flag
*/ */
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
/** /**
* @brief Enable interrupt on PVD Exti Line 16. * @brief Enable interrupt on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable interrupt on PVD Exti Line 16. * @brief Disable interrupt on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Enable event on PVD Exti Line 16. * @brief Enable event on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable event on PVD Exti Line 16. * @brief Disable event on PVD Exti Line 16.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set falling edge trigger. * @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Falling Trigger. * @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising edge trigger. * @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief Disable the PVD Extended Interrupt Rising Trigger. * @brief Disable the PVD Extended Interrupt Rising Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/** /**
* @brief PVD EXTI line configuration: set rising & falling edge trigger. * @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/** /**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* This parameter can be: * This parameter can be:
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/** /**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status. * @retval EXTI PVD Line Status.
*/ */
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/** /**
* @brief Clear the PVD EXTI flag. * @brief Clear the PVD EXTI flag.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
/** /**
* @brief Generate a Software interrupt on selected EXTI line. * @brief Generate a Software interrupt on selected EXTI line.
* @retval None. * @retval None.
*/ */
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros /** @defgroup PWR_Private_Macros PWR Private Macros
* @{ * @{
*/ */
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL)) ((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/** /**
* @} * @}
*/ */
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions /** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{ * @{
*/ */
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{ * @{
*/ */
/* Initialization and de-initialization functions *******************************/ /* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void); void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void);
/** /**
* @} * @}
*/ */
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{ * @{
*/ */
/* Peripheral Control functions ************************************************/ /* Peripheral Control functions ************************************************/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
/* #define HAL_PWR_ConfigPVD 12*/ /* #define HAL_PWR_ConfigPVD 12*/
void HAL_PWR_EnablePVD(void); void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void); void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/ /* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/ /* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void); void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void); void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void); void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void); void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void); void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVD_IRQHandler(void); void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void); void HAL_PWR_PVDCallback(void);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* __STM32F1xx_HAL_PWR_H */ #endif /* __STM32F1xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2756
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h
View File

File diff suppressed because it is too large Load Diff

3816
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h
View File

File diff suppressed because it is too large Load Diff

4246
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h
View File

File diff suppressed because it is too large Load Diff

524
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h → cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h
View File

@ -1,262 +1,262 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_tim_ex.h * @file stm32f1xx_hal_tim_ex.h
* @author MCD Application Team * @author MCD Application Team
* @brief Header file of TIM HAL Extended module. * @brief Header file of TIM HAL Extended module.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Define to prevent recursive inclusion -------------------------------------*/ /* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_HAL_TIM_EX_H #ifndef STM32F1xx_HAL_TIM_EX_H
#define STM32F1xx_HAL_TIM_EX_H #define STM32F1xx_HAL_TIM_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h" #include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @addtogroup TIMEx /** @addtogroup TIMEx
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{ * @{
*/ */
/** /**
* @brief TIM Hall sensor Configuration Structure definition * @brief TIM Hall sensor Configuration Structure definition
*/ */
typedef struct typedef struct
{ {
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter. uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef; } TIM_HallSensor_InitTypeDef;
/** /**
* @} * @}
*/ */
/* End of exported types -----------------------------------------------------*/ /* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{ * @{
*/ */
/** @defgroup TIMEx_Remap TIM Extended Remapping /** @defgroup TIMEx_Remap TIM Extended Remapping
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* End of exported constants -------------------------------------------------*/ /* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* End of exported macro -----------------------------------------------------*/ /* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{ * @{
*/ */
/** /**
* @} * @}
*/ */
/* End of private macro ------------------------------------------------------*/ /* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{ * @{
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions * @brief Timer Hall Sensor functions
* @{ * @{
*/ */
/* Timer Hall Sensor functions **********************************************/ /* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */ /* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions
* @{ * @{
*/ */
/* Timer Complementary Output Compare functions *****************************/ /* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */ /* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions * @brief Timer Complementary PWM functions
* @{ * @{
*/ */
/* Timer Complementary PWM functions ****************************************/ /* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */ /* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions
* @{ * @{
*/ */
/* Timer Complementary One Pulse functions **********************************/ /* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions * @brief Peripheral Control functions
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig); TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions * @brief Extended Callbacks functions
* @{ * @{
*/ */
/* Extended Callback **********************************************************/ /* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions * @brief Extended Peripheral State functions
* @{ * @{
*/ */
/* Extended Peripheral State functions ***************************************/ /* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/* End of exported functions -------------------------------------------------*/ /* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */
/* End of private functions --------------------------------------------------*/ /* End of private functions --------------------------------------------------*/
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* STM32F1xx_HAL_TIM_EX_H */ #endif /* STM32F1xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

852
cube/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h Normal file
View File

@ -0,0 +1,852 @@
/**
******************************************************************************
* @file stm32f1xx_hal_uart.h
* @author MCD Application Team
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_UART_H
#define __STM32F1xx_HAL_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UART_Word_Length */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
on STM32F100xx family, so OverSampling parameter should always be set to 16. */
} UART_InitTypeDef;
/**
* @brief HAL UART State structures definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_UART_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
} HAL_UART_StateTypeDef;
/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< UART registers base address */
UART_InitTypeDef Init; /*!< UART communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
} UART_HandleTypeDef;
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL UART Callback ID enumeration definition
*/
typedef enum
{
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
} HAL_UART_CallbackIDTypeDef;
/**
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UART_Exported_Constants UART Exported Constants
* @{
*/
/** @defgroup UART_Error_Code UART Error Code
* @{
*/
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup UART_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B 0x00000000U
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 0x00000000U
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
/**
* @}
*/
/** @defgroup UART_Parity UART Parity
* @{
*/
#define UART_PARITY_NONE 0x00000000U
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
#define UART_HWCONTROL_NONE 0x00000000U
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
/**
* @}
*/
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
/**
* @}
*/
/** @defgroup UART_State UART State
* @{
*/
#define UART_STATE_DISABLE 0x00000000U
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
/**
* @}
*/
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
#define UART_OVERSAMPLING_16 0x00000000U
#if defined(USART_CR1_OVER8)
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
#endif /* USART_CR1_OVER8 */
/**
* @}
*/
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
/**
* @}
*/
/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
/**
* @}
*/
/** @defgroup UART_Flags UART FLags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
/**
* @}
*/
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
* - 0001: CR1 register
* - 0010: CR2 register
* - 0011: CR3 register
* @{
*/
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
/** @brief Reset UART handle gstate & RxState
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
/** @brief Flushes the UART DR register
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
* @arg UART_FLAG_LBD: LIN Break detection flag
* @arg UART_FLAG_TXE: Transmit data register empty flag
* @arg UART_FLAG_TC: Transmission Complete flag
* @arg UART_FLAG_RXNE: Receive data register not empty flag
* @arg UART_FLAG_IDLE: Idle Line detection flag
* @arg UART_FLAG_ORE: Overrun Error flag
* @arg UART_FLAG_NE: Noise Error flag
* @arg UART_FLAG_FE: Framing Error flag
* @arg UART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
* @arg UART_FLAG_LBD: LIN Break detection flag.
* @arg UART_FLAG_TC: Transmission Complete flag.
* @arg UART_FLAG_RXNE: Receive data register not empty flag.
*
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clears the UART PE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00U; \
tmpreg = (__HANDLE__)->Instance->SR; \
tmpreg = (__HANDLE__)->Instance->DR; \
UNUSED(tmpreg); \
} while(0U)
/** @brief Clears the UART FE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART NE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART ORE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clears the UART IDLE pending flag.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Checks whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @param __IT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
* @arg UART_IT_LBD: LIN Break detection interrupt
* @arg UART_IT_TXE: Transmit Data Register empty interrupt
* @arg UART_IT_TC: Transmission complete interrupt
* @arg UART_IT_RXNE: Receive Data register not empty interrupt
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_ERR: Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
/** @brief Enable CTS flow control
* @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
} while(0U)
/** @brief Disable CTS flow control
* @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
} while(0U)
/** @brief Enable RTS flow control
* This macro allows to enable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
} while(0U)
/** @brief Disable RTS flow control
* This macro allows to disable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
} while(0U)
#if defined(USART_CR3_ONEBIT)
/** @brief Macro to enable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the UART's one bit sample method
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
#endif /* UART_ONE_BIT_SAMPLE_Feature */
/** @brief Enable UART
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions
* @{
*/
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UART_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
/** @brief UART interruptions flag mask
*
*/
#define UART_IT_MASK 0x0000FFFFU
#define UART_CR1_REG_INDEX 1U
#define UART_CR2_REG_INDEX 2U
#define UART_CR3_REG_INDEX 3U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
((STOPBITS) == UART_STOPBITS_2))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
((PARITY) == UART_PARITY_EVEN) || \
((PARITY) == UART_PARITY_ODD))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HWCONTROL_NONE) || \
((CONTROL) == UART_HWCONTROL_RTS) || \
((CONTROL) == UART_HWCONTROL_CTS) || \
((CONTROL) == UART_HWCONTROL_RTS_CTS))
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
((STATE) == UART_STATE_ENABLE))
#if defined(USART_CR1_OVER8)
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
((SAMPLING) == UART_OVERSAMPLING_8))
#endif /* USART_CR1_OVER8 */
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4500000U)
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup UART_Private_Functions UART Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_HAL_UART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1212
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
View File

File diff suppressed because it is too large Load Diff

2417
cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c Normal file
View File

File diff suppressed because it is too large Load Diff

1323
cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c Normal file
View File

File diff suppressed because it is too large Load Diff

1010
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
View File

File diff suppressed because it is too large Load Diff

1798
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
View File

File diff suppressed because it is too large Load Diff

1118
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c
View File

File diff suppressed because it is too large Load Diff

1934
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
View File

File diff suppressed because it is too large Load Diff

2254
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
View File

File diff suppressed because it is too large Load Diff

1174
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
View File

File diff suppressed because it is too large Load Diff

254
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
View File

@ -1,127 +1,127 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32f1xx_hal_gpio_ex.c * @file stm32f1xx_hal_gpio_ex.c
* @author MCD Application Team * @author MCD Application Team
* @brief GPIO Extension HAL module driver. * @brief GPIO Extension HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral. * functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
* + Extended features functions * + Extended features functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### GPIO Peripheral extension features ##### ##### GPIO Peripheral extension features #####
============================================================================== ==============================================================================
[..] GPIO module on STM32F1 family, manage also the AFIO register: [..] GPIO module on STM32F1 family, manage also the AFIO register:
(+) Possibility to use the EVENTOUT Cortex feature (+) Possibility to use the EVENTOUT Cortex feature
##### How to use this driver ##### ##### How to use this driver #####
============================================================================== ==============================================================================
[..] This driver provides functions to use EVENTOUT Cortex feature [..] This driver provides functions to use EVENTOUT Cortex feature
(#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (#) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
(#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (#) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
(#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() (#) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h" #include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver /** @addtogroup STM32F1xx_HAL_Driver
* @{ * @{
*/ */
/** @defgroup GPIOEx GPIOEx /** @defgroup GPIOEx GPIOEx
* @brief GPIO HAL module driver * @brief GPIO HAL module driver
* @{ * @{
*/ */
#ifdef HAL_GPIO_MODULE_ENABLED #ifdef HAL_GPIO_MODULE_ENABLED
/** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions /** @defgroup GPIOEx_Exported_Functions GPIOEx Exported Functions
* @{ * @{
*/ */
/** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions /** @defgroup GPIOEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions * @brief Extended features functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Extended features functions ##### ##### Extended features functions #####
============================================================================== ==============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout() (+) Configure EVENTOUT Cortex feature using the function HAL_GPIOEx_ConfigEventout()
(+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout() (+) Activate EVENTOUT Cortex feature using the HAL_GPIOEx_EnableEventout()
(+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout() (+) Deactivate EVENTOUT Cortex feature using the HAL_GPIOEx_DisableEventout()
@endverbatim @endverbatim
* @{ * @{
*/ */
/** /**
* @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
* @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal. * @param GPIO_PortSource Select the port used to output the Cortex EVENTOUT signal.
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PORT.
* @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal. * @param GPIO_PinSource Select the pin used to output the Cortex EVENTOUT signal.
* This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN. * This parameter can be a value of @ref GPIOEx_EVENTOUT_PIN.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource) void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource)
{ {
/* Verify the parameters */ /* Verify the parameters */
assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource)); assert_param(IS_AFIO_EVENTOUT_PORT(GPIO_PortSource));
assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource)); assert_param(IS_AFIO_EVENTOUT_PIN(GPIO_PinSource));
/* Apply the new configuration */ /* Apply the new configuration */
MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource)); MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (GPIO_PortSource) | (GPIO_PinSource));
} }
/** /**
* @brief Enables the Event Output. * @brief Enables the Event Output.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_EnableEventout(void) void HAL_GPIOEx_EnableEventout(void)
{ {
SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
} }
/** /**
* @brief Disables the Event Output. * @brief Disables the Event Output.
* @retval None * @retval None
*/ */
void HAL_GPIOEx_DisableEventout(void) void HAL_GPIOEx_DisableEventout(void)
{ {
CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
} }
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
#endif /* HAL_GPIO_MODULE_ENABLED */ #endif /* HAL_GPIO_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/** /**
* @} * @}
*/ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1242
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
View File

File diff suppressed because it is too large Load Diff

2806
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
View File

File diff suppressed because it is too large Load Diff

1726
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
View File

File diff suppressed because it is too large Load Diff

14842
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
View File

File diff suppressed because it is too large Load Diff

4592
stm32_test1/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c → cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
View File

File diff suppressed because it is too large Load Diff

3133
cube/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c Normal file
View File

File diff suppressed because it is too large Load Diff

384
stm32_test1/Makefile → cube/Makefile
View File

@ -1,189 +1,195 @@
########################################################################################################################## ##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [3.10.0-B14] date: [Sat Oct 03 12:45:26 CEST 2020] # File automatically-generated by tool: [projectgenerator] version: [3.10.0-B14] date: [Tue Oct 06 13:31:48 CEST 2020]
########################################################################################################################## ##########################################################################################################################
# ------------------------------------------------ # ------------------------------------------------
# Generic Makefile (based on gcc) # Generic Makefile (based on gcc)
# #
# ChangeLog : # ChangeLog :
# 2017-02-10 - Several enhancements + project update mode # 2017-02-10 - Several enhancements + project update mode
# 2015-07-22 - first version # 2015-07-22 - first version
# ------------------------------------------------ # ------------------------------------------------
###################################### ######################################
# target # target
###################################### ######################################
TARGET = stm32_test1 TARGET = cube
###################################### ######################################
# building variables # building variables
###################################### ######################################
# debug build? # debug build?
DEBUG = 1 DEBUG = 1
# optimization # optimization
OPT = -Og OPT = -Og
####################################### #######################################
# paths # paths
####################################### #######################################
# Build path # Build path
BUILD_DIR = build BUILD_DIR = build
###################################### ######################################
# source # source
###################################### ######################################
# C sources # C sources
C_SOURCES = \ C_SOURCES = \
Core/Src/main.c \ Core/Src/main.c \
Core/Src/stm32f1xx_it.c \ Core/Src/gpio.c \
Core/Src/stm32f1xx_hal_msp.c \ Core/Src/adc.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \ Core/Src/usart.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \ Core/Src/stm32f1xx_it.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \ Core/Src/stm32f1xx_hal_msp.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c \
Core/Src/system_stm32f1xx.c \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c \
Core/Src/gpio.c Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c \
Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c \
# ASM sources Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c \
ASM_SOURCES = \ Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c \
startup_stm32f103xe.s Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c \
Core/Src/system_stm32f1xx.c
####################################### # ASM sources
# binaries ASM_SOURCES = \
####################################### startup_stm32f103xe.s
PREFIX = arm-none-eabi-
# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
# either it can be added to the PATH environment variable. #######################################
ifdef GCC_PATH # binaries
CC = $(GCC_PATH)/$(PREFIX)gcc #######################################
AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp PREFIX = arm-none-eabi-
CP = $(GCC_PATH)/$(PREFIX)objcopy # The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
SZ = $(GCC_PATH)/$(PREFIX)size # either it can be added to the PATH environment variable.
else ifdef GCC_PATH
CC = $(PREFIX)gcc CC = $(GCC_PATH)/$(PREFIX)gcc
AS = $(PREFIX)gcc -x assembler-with-cpp AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy CP = $(GCC_PATH)/$(PREFIX)objcopy
SZ = $(PREFIX)size SZ = $(GCC_PATH)/$(PREFIX)size
endif else
HEX = $(CP) -O ihex CC = $(PREFIX)gcc
BIN = $(CP) -O binary -S AS = $(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy
####################################### SZ = $(PREFIX)size
# CFLAGS endif
####################################### HEX = $(CP) -O ihex
# cpu BIN = $(CP) -O binary -S
CPU = -mcpu=cortex-m3
#######################################
# fpu # CFLAGS
# NONE for Cortex-M0/M0+/M3 #######################################
# cpu
# float-abi CPU = -mcpu=cortex-m3
# fpu
# mcu # NONE for Cortex-M0/M0+/M3
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
# float-abi
# macros for gcc
# AS defines
AS_DEFS = # mcu
MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
# C defines
C_DEFS = \ # macros for gcc
-DUSE_HAL_DRIVER \ # AS defines
-DSTM32F103xE AS_DEFS =
# C defines
# AS includes C_DEFS = \
AS_INCLUDES = -DUSE_HAL_DRIVER \
-DSTM32F103xE
# C includes
C_INCLUDES = \
-ICore/Inc \ # AS includes
-IDrivers/STM32F1xx_HAL_Driver/Inc \ AS_INCLUDES =
-IDrivers/STM32F1xx_HAL_Driver/Inc/Legacy \
-IDrivers/CMSIS/Device/ST/STM32F1xx/Include \ # C includes
-IDrivers/CMSIS/Include C_INCLUDES = \
-ICore/Inc \
-IDrivers/STM32F1xx_HAL_Driver/Inc \
# compile gcc flags -IDrivers/STM32F1xx_HAL_Driver/Inc/Legacy \
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -IDrivers/CMSIS/Device/ST/STM32F1xx/Include \
-IDrivers/CMSIS/Include
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -IDrivers/CMSIS/Include
ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2 # compile gcc flags
endif ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
# Generate dependency information
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2
endif
#######################################
# LDFLAGS
####################################### # Generate dependency information
# link script CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
LDSCRIPT = STM32F103VCTx_FLASH.ld
# libraries #######################################
LIBS = -lc -lm -lnosys # LDFLAGS
LIBDIR = #######################################
LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections # link script
LDSCRIPT = STM32F103VCTx_FLASH.ld
# default action: build all
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin # libraries
LIBS = -lc -lm -lnosys
LIBDIR =
####################################### LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
# build the application
####################################### # default action: build all
# list of objects all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
vpath %.c $(sort $(dir $(C_SOURCES)))
# list of ASM program objects #######################################
OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o))) # build the application
vpath %.s $(sort $(dir $(ASM_SOURCES))) #######################################
# list of objects
$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
$(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ vpath %.c $(sort $(dir $(C_SOURCES)))
# list of ASM program objects
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
$(AS) -c $(CFLAGS) $< -o $@ vpath %.s $(sort $(dir $(ASM_SOURCES)))
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
$(CC) $(OBJECTS) $(LDFLAGS) -o $@ $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
$(SZ) $@
$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) $(AS) -c $(CFLAGS) $< -o $@
$(HEX) $< $@
$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) $(CC) $(OBJECTS) $(LDFLAGS) -o $@
$(BIN) $< $@ $(SZ) $@
$(BUILD_DIR): $(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
mkdir $@ $(HEX) $< $@
####################################### $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
# clean up $(BIN) $< $@
#######################################
clean: $(BUILD_DIR):
-rm -fR $(BUILD_DIR) mkdir $@
####################################### #######################################
# dependencies # clean up
####################################### #######################################
-include $(wildcard $(BUILD_DIR)/*.d) clean:
-rm -fR $(BUILD_DIR)
# *** EOF ***
#######################################
# dependencies
#######################################
-include $(wildcard $(BUILD_DIR)/*.d)
# *** EOF ***

378
stm32_test1/STM32F103VCTx_FLASH.ld → cube/STM32F103VCTx_FLASH.ld
View File

@ -1,189 +1,189 @@
/* /*
****************************************************************************** ******************************************************************************
** **
** File : LinkerScript.ld ** File : LinkerScript.ld
** **
** Author : Auto-generated by System Workbench for STM32 ** Author : Auto-generated by System Workbench for STM32
** **
** Abstract : Linker script for STM32F103VCTx series ** Abstract : Linker script for STM32F103VCTx series
** 256Kbytes FLASH and 48Kbytes RAM ** 256Kbytes FLASH and 48Kbytes RAM
** **
** Set heap size, stack size and stack location according ** Set heap size, stack size and stack location according
** to application requirements. ** to application requirements.
** **
** Set memory bank area and size if external memory is used. ** Set memory bank area and size if external memory is used.
** **
** Target : STMicroelectronics STM32 ** Target : STMicroelectronics STM32
** **
** Distribution: The file is distributed “as is,” without any warranty ** Distribution: The file is distributed “as is,” without any warranty
** of any kind. ** of any kind.
** **
***************************************************************************** *****************************************************************************
** @attention ** @attention
** **
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2> ** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
** **
** Redistribution and use in source and binary forms, with or without modification, ** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met: ** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice, ** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer. ** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice, ** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation ** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution. ** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors ** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software ** may be used to endorse or promote products derived from this software
** without specific prior written permission. ** without specific prior written permission.
** **
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
** **
***************************************************************************** *****************************************************************************
*/ */
/* Entry Point */ /* Entry Point */
ENTRY(Reset_Handler) ENTRY(Reset_Handler)
/* Highest address of the user mode stack */ /* Highest address of the user mode stack */
_estack = 0x2000C000; /* end of RAM */ _estack = 0x2000C000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */ /* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */ _Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */ _Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */ /* Specify the memory areas */
MEMORY MEMORY
{ {
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 48K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 256K
} }
/* Define output sections */ /* Define output sections */
SECTIONS SECTIONS
{ {
/* The startup code goes first into FLASH */ /* The startup code goes first into FLASH */
.isr_vector : .isr_vector :
{ {
. = ALIGN(4); . = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */ KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4); . = ALIGN(4);
} >FLASH } >FLASH
/* The program code and other data goes into FLASH */ /* The program code and other data goes into FLASH */
.text : .text :
{ {
. = ALIGN(4); . = ALIGN(4);
*(.text) /* .text sections (code) */ *(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */ *(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */ *(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */ *(.glue_7t) /* glue thumb to arm code */
*(.eh_frame) *(.eh_frame)
KEEP (*(.init)) KEEP (*(.init))
KEEP (*(.fini)) KEEP (*(.fini))
. = ALIGN(4); . = ALIGN(4);
_etext = .; /* define a global symbols at end of code */ _etext = .; /* define a global symbols at end of code */
} >FLASH } >FLASH
/* Constant data goes into FLASH */ /* Constant data goes into FLASH */
.rodata : .rodata :
{ {
. = ALIGN(4); . = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4); . = ALIGN(4);
} >FLASH } >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : { .ARM : {
__exidx_start = .; __exidx_start = .;
*(.ARM.exidx*) *(.ARM.exidx*)
__exidx_end = .; __exidx_end = .;
} >FLASH } >FLASH
.preinit_array : .preinit_array :
{ {
PROVIDE_HIDDEN (__preinit_array_start = .); PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*)) KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .); PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH } >FLASH
.init_array : .init_array :
{ {
PROVIDE_HIDDEN (__init_array_start = .); PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*))) KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*)) KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .); PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH } >FLASH
.fini_array : .fini_array :
{ {
PROVIDE_HIDDEN (__fini_array_start = .); PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*))) KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*)) KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .); PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH } >FLASH
/* used by the startup to initialize data */ /* used by the startup to initialize data */
_sidata = LOADADDR(.data); _sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */ /* Initialized data sections goes into RAM, load LMA copy after code */
.data : .data :
{ {
. = ALIGN(4); . = ALIGN(4);
_sdata = .; /* create a global symbol at data start */ _sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */ *(.data) /* .data sections */
*(.data*) /* .data* sections */ *(.data*) /* .data* sections */
. = ALIGN(4); . = ALIGN(4);
_edata = .; /* define a global symbol at data end */ _edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH } >RAM AT> FLASH
/* Uninitialized data section */ /* Uninitialized data section */
. = ALIGN(4); . = ALIGN(4);
.bss : .bss :
{ {
/* This is used by the startup in order to initialize the .bss secion */ /* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */ _sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss; __bss_start__ = _sbss;
*(.bss) *(.bss)
*(.bss*) *(.bss*)
*(COMMON) *(COMMON)
. = ALIGN(4); . = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */ _ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss; __bss_end__ = _ebss;
} >RAM } >RAM
/* User_heap_stack section, used to check that there is enough RAM left */ /* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack : ._user_heap_stack :
{ {
. = ALIGN(8); . = ALIGN(8);
PROVIDE ( end = . ); PROVIDE ( end = . );
PROVIDE ( _end = . ); PROVIDE ( _end = . );
. = . + _Min_Heap_Size; . = . + _Min_Heap_Size;
. = . + _Min_Stack_Size; . = . + _Min_Stack_Size;
. = ALIGN(8); . = ALIGN(8);
} >RAM } >RAM
/* Remove information from the standard libraries */ /* Remove information from the standard libraries */
/DISCARD/ : /DISCARD/ :
{ {
libc.a ( * ) libc.a ( * )
libm.a ( * ) libm.a ( * )
libgcc.a ( * ) libgcc.a ( * )
} }
.ARM.attributes 0 : { *(.ARM.attributes) } .ARM.attributes 0 : { *(.ARM.attributes) }
} }

100
stm32_test1/stm32_test1.ioc → cube/cube.ioc
View File

@ -1,29 +1,47 @@
#MicroXplorer Configuration settings - do not modify #MicroXplorer Configuration settings - do not modify
ADC1.ContinuousConvMode=ENABLE
ADC1.EnableRegularConversion=DISABLE
ADC1.IPParameters=master,ContinuousConvMode,EnableRegularConversion
ADC1.master=1
File.Version=6 File.Version=6
GPIO.groupedBy= GPIO.groupedBy=Group By Peripherals
KeepUserPlacement=false KeepUserPlacement=false
Mcu.Family=STM32F1 Mcu.Family=STM32F1
Mcu.IP0=NVIC Mcu.IP0=ADC1
Mcu.IP1=RCC Mcu.IP1=NVIC
Mcu.IP2=SYS Mcu.IP2=RCC
Mcu.IPNb=3 Mcu.IP3=SYS
Mcu.IP4=UART4
Mcu.IP5=UART5
Mcu.IPNb=6
Mcu.Name=STM32F103V(C-D-E)Tx Mcu.Name=STM32F103V(C-D-E)Tx
Mcu.Package=LQFP100 Mcu.Package=LQFP100
Mcu.Pin0=PC13-TAMPER-RTC Mcu.Pin0=PC13-TAMPER-RTC
Mcu.Pin1=PC14-OSC32_IN Mcu.Pin1=PC14-OSC32_IN
Mcu.Pin10=PD3
Mcu.Pin11=PD6
Mcu.Pin12=PD7
Mcu.Pin13=PB3
Mcu.Pin14=VP_SYS_VS_ND
Mcu.Pin15=VP_SYS_VS_Systick
Mcu.Pin2=PC15-OSC32_OUT Mcu.Pin2=PC15-OSC32_OUT
Mcu.Pin3=OSC_IN Mcu.Pin3=OSC_IN
Mcu.Pin4=OSC_OUT Mcu.Pin4=OSC_OUT
Mcu.Pin5=VP_SYS_VS_ND Mcu.Pin5=PA1
Mcu.Pin6=VP_SYS_VS_Systick Mcu.Pin6=PC10
Mcu.PinsNb=7 Mcu.Pin7=PC11
Mcu.Pin8=PC12
Mcu.Pin9=PD2
Mcu.PinsNb=16
Mcu.ThirdPartyNb=0 Mcu.ThirdPartyNb=0
Mcu.UserConstants= Mcu.UserConstants=
Mcu.UserName=STM32F103VCTx Mcu.UserName=STM32F103VCTx
MxCube.Version=6.0.0 MxCube.Version=6.0.0
MxDb.Version=DB.6.0.0 MxDb.Version=DB.6.0.0
NVIC.ADC1_2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.EXTI3_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.ForceEnableDMAVector=true NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
@ -32,23 +50,62 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.UART4_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.UART5_IRQn=true\:0\:0\:false\:false\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Mode=HSE-External-Oscillator
OSC_IN.Signal=RCC_OSC_IN OSC_IN.Signal=RCC_OSC_IN
OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Mode=HSE-External-Oscillator
OSC_OUT.Signal=RCC_OSC_OUT OSC_OUT.Signal=RCC_OSC_OUT
PA1.GPIOParameters=GPIO_Label
PA1.GPIO_Label=Frontend_In
PA1.Signal=ADCx_IN1
PB3.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
PB3.GPIO_Label=Loop_Status
PB3.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
PB3.GPIO_PuPd=GPIO_PULLUP
PB3.Locked=true
PB3.Signal=GPXTI3
PC10.GPIOParameters=GPIO_Label
PC10.GPIO_Label=Debug_TX
PC10.Mode=Asynchronous
PC10.Signal=UART4_TX
PC11.GPIOParameters=GPIO_Label
PC11.GPIO_Label=Debug_RX
PC11.Mode=Asynchronous
PC11.Signal=UART4_RX
PC12.GPIOParameters=GPIO_Label
PC12.GPIO_Label=Meterbus_Tx
PC12.Mode=Asynchronous
PC12.Signal=UART5_TX
PC13-TAMPER-RTC.GPIOParameters=GPIO_Label PC13-TAMPER-RTC.GPIOParameters=GPIO_Label
PC13-TAMPER-RTC.GPIO_Label=LED_Green PC13-TAMPER-RTC.GPIO_Label=LED_Heartbeat
PC13-TAMPER-RTC.Locked=true PC13-TAMPER-RTC.Locked=true
PC13-TAMPER-RTC.Signal=GPIO_Output PC13-TAMPER-RTC.Signal=GPIO_Output
PC14-OSC32_IN.GPIOParameters=GPIO_Label PC14-OSC32_IN.GPIOParameters=GPIO_Label
PC14-OSC32_IN.GPIO_Label=LED_Red PC14-OSC32_IN.GPIO_Label=LED_Error
PC14-OSC32_IN.Locked=true PC14-OSC32_IN.Locked=true
PC14-OSC32_IN.Signal=GPIO_Output PC14-OSC32_IN.Signal=GPIO_Output
PC15-OSC32_OUT.GPIOParameters=GPIO_Label PC15-OSC32_OUT.GPIOParameters=GPIO_Label
PC15-OSC32_OUT.GPIO_Label=LED_Blue PC15-OSC32_OUT.GPIO_Label=LED_Operation
PC15-OSC32_OUT.Locked=true PC15-OSC32_OUT.Locked=true
PC15-OSC32_OUT.Signal=GPIO_Output PC15-OSC32_OUT.Signal=GPIO_Output
PD2.GPIOParameters=GPIO_Label
PD2.GPIO_Label=Meterbus_RX
PD2.Mode=Asynchronous
PD2.Signal=UART5_RX
PD3.GPIOParameters=GPIO_Label
PD3.GPIO_Label=Frontend_Out
PD3.Locked=true
PD3.Signal=GPIO_Output
PD6.GPIOParameters=GPIO_Label
PD6.GPIO_Label=Loop_Disable
PD6.Locked=true
PD6.Signal=GPIO_Output
PD7.GPIOParameters=GPIO_Label
PD7.GPIO_Label=Loop_Enable
PD7.Locked=true
PD7.Signal=GPIO_Output
PinOutPanel.RotationAngle=0 PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false ProjectManager.BackupPrevious=false
@ -70,15 +127,16 @@ ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false ProjectManager.NoMain=false
ProjectManager.PreviousToolchain= ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=stm32_test1.ioc ProjectManager.ProjectFileName=cube.ioc
ProjectManager.ProjectName=stm32_test1 ProjectManager.ProjectName=cube
ProjectManager.RegisterCallBack= ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x400 ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=Makefile ProjectManager.TargetToolchain=Makefile
ProjectManager.ToolChainLocation= ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_UART4_Init-UART4-false-HAL-true,5-MX_UART5_Init-UART5-false-HAL-true
RCC.ADCFreqValue=36000000 RCC.ADCFreqValue=12000000
RCC.ADCPresc=RCC_ADCPCLK2_DIV6
RCC.AHBFreq_Value=72000000 RCC.AHBFreq_Value=72000000
RCC.APB1CLKDivider=RCC_HCLK_DIV2 RCC.APB1CLKDivider=RCC_HCLK_DIV2
RCC.APB1Freq_Value=36000000 RCC.APB1Freq_Value=36000000
@ -91,7 +149,7 @@ RCC.FamilyName=M
RCC.HCLKFreq_Value=72000000 RCC.HCLKFreq_Value=72000000
RCC.I2S2Freq_Value=72000000 RCC.I2S2Freq_Value=72000000
RCC.I2S3Freq_Value=72000000 RCC.I2S3Freq_Value=72000000
RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
RCC.MCOFreq_Value=72000000 RCC.MCOFreq_Value=72000000
RCC.PLLCLKFreq_Value=72000000 RCC.PLLCLKFreq_Value=72000000
RCC.PLLMCOFreq_Value=36000000 RCC.PLLMCOFreq_Value=36000000
@ -104,6 +162,16 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.TimSysFreq_Value=72000000 RCC.TimSysFreq_Value=72000000
RCC.USBFreq_Value=72000000 RCC.USBFreq_Value=72000000
RCC.VCOOutput2Freq_Value=8000000 RCC.VCOOutput2Freq_Value=8000000
SH.ADCx_IN1.0=ADC1_IN1,IN1
SH.ADCx_IN1.ConfNb=1
SH.GPXTI3.0=GPIO_EXTI3
SH.GPXTI3.ConfNb=1
UART4.IPParameters=VirtualMode
UART4.VirtualMode=Asynchronous
UART5.BaudRate=2400
UART5.IPParameters=VirtualMode,BaudRate,Parity
UART5.Parity=PARITY_EVEN
UART5.VirtualMode=Asynchronous
VP_SYS_VS_ND.Mode=No_Debug VP_SYS_VS_ND.Mode=No_Debug
VP_SYS_VS_ND.Signal=SYS_VS_ND VP_SYS_VS_ND.Signal=SYS_VS_ND
VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Mode=SysTick

936
stm32_test1/startup_stm32f103xe.s → cube/startup_stm32f103xe.s
View File

@ -1,468 +1,468 @@
/** /**
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************ *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
* @file startup_stm32f103xe.s * @file startup_stm32f103xe.s
* @author MCD Application Team * @author MCD Application Team
* @brief STM32F103xE Devices vector table for Atollic toolchain. * @brief STM32F103xE Devices vector table for Atollic toolchain.
* This module performs: * This module performs:
* - Set the initial SP * - Set the initial SP
* - Set the initial PC == Reset_Handler, * - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address * - Set the vector table entries with the exceptions ISR address
* - Configure the clock system * - Configure the clock system
* - Configure external SRAM mounted on STM3210E-EVAL board * - Configure external SRAM mounted on STM3210E-EVAL board
* to be used as data memory (optional, to be enabled by user) * to be used as data memory (optional, to be enabled by user)
* - Branches to main in the C library (which eventually * - Branches to main in the C library (which eventually
* calls main()). * calls main()).
* After Reset the Cortex-M3 processor is in Thread mode, * After Reset the Cortex-M3 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main. * priority is Privileged, and the Stack is set to Main.
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
.syntax unified .syntax unified
.cpu cortex-m3 .cpu cortex-m3
.fpu softvfp .fpu softvfp
.thumb .thumb
.global g_pfnVectors .global g_pfnVectors
.global Default_Handler .global Default_Handler
/* start address for the initialization values of the .data section. /* start address for the initialization values of the .data section.
defined in linker script */ defined in linker script */
.word _sidata .word _sidata
/* start address for the .data section. defined in linker script */ /* start address for the .data section. defined in linker script */
.word _sdata .word _sdata
/* end address for the .data section. defined in linker script */ /* end address for the .data section. defined in linker script */
.word _edata .word _edata
/* start address for the .bss section. defined in linker script */ /* start address for the .bss section. defined in linker script */
.word _sbss .word _sbss
/* end address for the .bss section. defined in linker script */ /* end address for the .bss section. defined in linker script */
.word _ebss .word _ebss
.equ BootRAM, 0xF1E0F85F .equ BootRAM, 0xF1E0F85F
/** /**
* @brief This is the code that gets called when the processor first * @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely * starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application * necessary set is performed, after which the application
* supplied main() routine is called. * supplied main() routine is called.
* @param None * @param None
* @retval : None * @retval : None
*/ */
.section .text.Reset_Handler .section .text.Reset_Handler
.weak Reset_Handler .weak Reset_Handler
.type Reset_Handler, %function .type Reset_Handler, %function
Reset_Handler: Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */ /* Copy the data segment initializers from flash to SRAM */
movs r1, #0 movs r1, #0
b LoopCopyDataInit b LoopCopyDataInit
CopyDataInit: CopyDataInit:
ldr r3, =_sidata ldr r3, =_sidata
ldr r3, [r3, r1] ldr r3, [r3, r1]
str r3, [r0, r1] str r3, [r0, r1]
adds r1, r1, #4 adds r1, r1, #4
LoopCopyDataInit: LoopCopyDataInit:
ldr r0, =_sdata ldr r0, =_sdata
ldr r3, =_edata ldr r3, =_edata
adds r2, r0, r1 adds r2, r0, r1
cmp r2, r3 cmp r2, r3
bcc CopyDataInit bcc CopyDataInit
ldr r2, =_sbss ldr r2, =_sbss
b LoopFillZerobss b LoopFillZerobss
/* Zero fill the bss segment. */ /* Zero fill the bss segment. */
FillZerobss: FillZerobss:
movs r3, #0 movs r3, #0
str r3, [r2], #4 str r3, [r2], #4
LoopFillZerobss: LoopFillZerobss:
ldr r3, = _ebss ldr r3, = _ebss
cmp r2, r3 cmp r2, r3
bcc FillZerobss bcc FillZerobss
/* Call the clock system intitialization function.*/ /* Call the clock system intitialization function.*/
bl SystemInit bl SystemInit
/* Call static constructors */ /* Call static constructors */
bl __libc_init_array bl __libc_init_array
/* Call the application's entry point.*/ /* Call the application's entry point.*/
bl main bl main
bx lr bx lr
.size Reset_Handler, .-Reset_Handler .size Reset_Handler, .-Reset_Handler
/** /**
* @brief This is the code that gets called when the processor receives an * @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving * unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger. * the system state for examination by a debugger.
* *
* @param None * @param None
* @retval : None * @retval : None
*/ */
.section .text.Default_Handler,"ax",%progbits .section .text.Default_Handler,"ax",%progbits
Default_Handler: Default_Handler:
Infinite_Loop: Infinite_Loop:
b Infinite_Loop b Infinite_Loop
.size Default_Handler, .-Default_Handler .size Default_Handler, .-Default_Handler
/****************************************************************************** /******************************************************************************
* *
* The minimal vector table for a Cortex M3. Note that the proper constructs * The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address * must be placed on this to ensure that it ends up at physical address
* 0x0000.0000. * 0x0000.0000.
* *
******************************************************************************/ ******************************************************************************/
.section .isr_vector,"a",%progbits .section .isr_vector,"a",%progbits
.type g_pfnVectors, %object .type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors .size g_pfnVectors, .-g_pfnVectors
g_pfnVectors: g_pfnVectors:
.word _estack .word _estack
.word Reset_Handler .word Reset_Handler
.word NMI_Handler .word NMI_Handler
.word HardFault_Handler .word HardFault_Handler
.word MemManage_Handler .word MemManage_Handler
.word BusFault_Handler .word BusFault_Handler
.word UsageFault_Handler .word UsageFault_Handler
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word SVC_Handler .word SVC_Handler
.word DebugMon_Handler .word DebugMon_Handler
.word 0 .word 0
.word PendSV_Handler .word PendSV_Handler
.word SysTick_Handler .word SysTick_Handler
.word WWDG_IRQHandler .word WWDG_IRQHandler
.word PVD_IRQHandler .word PVD_IRQHandler
.word TAMPER_IRQHandler .word TAMPER_IRQHandler
.word RTC_IRQHandler .word RTC_IRQHandler
.word FLASH_IRQHandler .word FLASH_IRQHandler
.word RCC_IRQHandler .word RCC_IRQHandler
.word EXTI0_IRQHandler .word EXTI0_IRQHandler
.word EXTI1_IRQHandler .word EXTI1_IRQHandler
.word EXTI2_IRQHandler .word EXTI2_IRQHandler
.word EXTI3_IRQHandler .word EXTI3_IRQHandler
.word EXTI4_IRQHandler .word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler .word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler .word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler .word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler .word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler .word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler .word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler .word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler .word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler .word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler .word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler .word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler .word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler .word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler .word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler .word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler .word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler .word TIM1_CC_IRQHandler
.word TIM2_IRQHandler .word TIM2_IRQHandler
.word TIM3_IRQHandler .word TIM3_IRQHandler
.word TIM4_IRQHandler .word TIM4_IRQHandler
.word I2C1_EV_IRQHandler .word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler .word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler .word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler .word I2C2_ER_IRQHandler
.word SPI1_IRQHandler .word SPI1_IRQHandler
.word SPI2_IRQHandler .word SPI2_IRQHandler
.word USART1_IRQHandler .word USART1_IRQHandler
.word USART2_IRQHandler .word USART2_IRQHandler
.word USART3_IRQHandler .word USART3_IRQHandler
.word EXTI15_10_IRQHandler .word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler .word RTC_Alarm_IRQHandler
.word USBWakeUp_IRQHandler .word USBWakeUp_IRQHandler
.word TIM8_BRK_IRQHandler .word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler .word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler .word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler .word TIM8_CC_IRQHandler
.word ADC3_IRQHandler .word ADC3_IRQHandler
.word FSMC_IRQHandler .word FSMC_IRQHandler
.word SDIO_IRQHandler .word SDIO_IRQHandler
.word TIM5_IRQHandler .word TIM5_IRQHandler
.word SPI3_IRQHandler .word SPI3_IRQHandler
.word UART4_IRQHandler .word UART4_IRQHandler
.word UART5_IRQHandler .word UART5_IRQHandler
.word TIM6_IRQHandler .word TIM6_IRQHandler
.word TIM7_IRQHandler .word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler .word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler .word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler .word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_5_IRQHandler .word DMA2_Channel4_5_IRQHandler
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word 0 .word 0
.word BootRAM /* @0x1E0. This is for boot in RAM mode for .word BootRAM /* @0x1E0. This is for boot in RAM mode for
STM32F10x High Density devices. */ STM32F10x High Density devices. */
/******************************************************************************* /*******************************************************************************
* *
* Provide weak aliases for each Exception handler to the Default_Handler. * Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override * As they are weak aliases, any function with the same name will override
* this definition. * this definition.
* *
*******************************************************************************/ *******************************************************************************/
.weak NMI_Handler .weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler .thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler .weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler .thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler .weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler .thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler .weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler .thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler .weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler .thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler .weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler .thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler .weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler .thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler .weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler .thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler .weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler .thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler .weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler .thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler .weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler .thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler .weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler .thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_IRQHandler .weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler .thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler .weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler .thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler .weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler .thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler .weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler .thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler .weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler .thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler .weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler .thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler .weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler .thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler .weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler .thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler .weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler .weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler .weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler .weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler .weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler .weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler .weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler .weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler .thumb_set ADC1_2_IRQHandler,Default_Handler
.weak USB_HP_CAN1_TX_IRQHandler .weak USB_HP_CAN1_TX_IRQHandler
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
.weak USB_LP_CAN1_RX0_IRQHandler .weak USB_LP_CAN1_RX0_IRQHandler
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler .weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler .thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler .weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler .thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler .weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler .thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler .weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler .thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler .weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler .thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler .weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler .weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler .thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler .weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler .thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler .weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler .thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler .weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler .thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler .weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler .thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler .weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler .thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler .weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler .thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler .weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler .thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler .weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler .thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler .weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler .thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler .weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler .thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler .weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler .thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler .weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler .thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler .weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler .thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler .weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler .thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler .weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler .thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler .weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler .thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler .weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler .thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler .weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler .weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler .thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler .weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler .thumb_set ADC3_IRQHandler,Default_Handler
.weak FSMC_IRQHandler .weak FSMC_IRQHandler
.thumb_set FSMC_IRQHandler,Default_Handler .thumb_set FSMC_IRQHandler,Default_Handler
.weak SDIO_IRQHandler .weak SDIO_IRQHandler
.thumb_set SDIO_IRQHandler,Default_Handler .thumb_set SDIO_IRQHandler,Default_Handler
.weak TIM5_IRQHandler .weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler .thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler .weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler .thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler .weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler .thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler .weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler .thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler .weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler .thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler .weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler .thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler .weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler .weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler .weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_5_IRQHandler .weak DMA2_Channel4_5_IRQHandler
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

27
stm32_test1/.mxproject
View File

@ -1,27 +0,0 @@
[PreviousLibFiles]
LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_sc300.h;
[PreviousUsedMakefileFiles]
SourceFiles=Core/Src/main.c;Core/Src/gpio.c;Core/Src/stm32f1xx_it.c;Core/Src/stm32f1xx_hal_msp.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Core/Src/system_stm32f1xx.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_exti.c;Core/Src/system_stm32f1xx.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;;
HeaderPath=Drivers/STM32F1xx_HAL_Driver/Inc;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F1xx/Include;Drivers/CMSIS/Include;Core/Inc;
CDefines=USE_HAL_DRIVER;STM32F103xE;USE_HAL_DRIVER;USE_HAL_DRIVER;
[PreviousGenFiles]
AdvancedFolderStructure=true
HeaderFileListSize=4
HeaderFiles#0=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Inc/gpio.h
HeaderFiles#1=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Inc/stm32f1xx_it.h
HeaderFiles#2=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Inc/stm32f1xx_hal_conf.h
HeaderFiles#3=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Inc/main.h
HeaderFolderListSize=1
HeaderPath#0=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Inc
HeaderFiles=;
SourceFileListSize=4
SourceFiles#0=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Src/gpio.c
SourceFiles#1=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Src/stm32f1xx_it.c
SourceFiles#2=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Src/stm32f1xx_hal_msp.c
SourceFiles#3=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Src/main.c
SourceFolderListSize=1
SourcePath#0=/home/wn/Workspaces/stm32_test1/stm32_test1/Core/Src
SourceFiles=;

15
tools/insertMyCode.pl Normal file
View File

@ -0,0 +1,15 @@
#!/usr/bin/perl -w
while (<>) {
print $_;
print "#include \"main2.h\";\n" if m/USER CODE BEGIN Includes/;
print " my_setup_1();\n" if m/USER CODE BEGIN 1/;
print " my_setup_2();\n" if m/USER CODE BEGIN 2/;
print " my_loop();\n" if m/USER CODE BEGIN 3/;
print " my_errorHandler();\n" if m/USER CODE BEGIN Error_Handler/;
print " while(1) { };\n" if m/USER CODE END Error_Handler/;
}

18
tools/insertMyCode.sh Normal file
View File

@ -0,0 +1,18 @@
#!/bin/bash
MAIN_C=./Core/Src/main.c
MAIN_C_BAK=./Core/Src/main.c-bak
if [ ! -f $MAIN_C ]; then
echo "no $MAIN_C available"
exit 1
fi
if [ -f $MAIN_C_BAK ]; then
echo "$MAIN_C_BAK already available, delete manually"
exit 1
fi
mv $MAIN_C $MAIN_C_BAK
cat $MAIN_C_BAK | ../tools/insertMyCode.pl > $MAIN_C