4 Commits

Author SHA1 Message Date
da3c2a5ffb image 2024-03-08 08:23:51 +01:00
a5438cef14 accept multiple address/data octets 2024-03-08 08:16:56 +01:00
d295a36598 receivedata added 2024-03-07 21:50:09 +01:00
3eaf90dbd6 works again 2024-03-07 15:43:27 +01:00
2 changed files with 37 additions and 57 deletions

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docs/comm_game_ctrl_01.png Normal file

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94
main.S
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@ -9,12 +9,12 @@
;; ----------------------------------------------------
;; --- r4, r5 and r6 must not be used for any other ---
;; --- purpose ---
;; required for communication between drawscreen and shifter isr
;; required for communication between drawscreen and isr
#define SIGNAL_REGISTER r4
#define SIGNAL_INIT_VALUE SIGNAL_OCTET_DONE
#define SIGNAL_OCTET_DONE 0x01
#define SIGNAL_ISR_ENABLE 0x02
#define SIGNAL_ALL_DATA_DONE 0x04
#define SIGNAL_INIT_VALUE SIGNAL_OCTET_DONE
;; required for handover of data between drawscreen and isr
#define DATA_REGISTER r5
@ -101,10 +101,10 @@ init:
;; BIT7: spi, UCB0SIMO
mov.b #BIT5|BIT6|BIT7, &P1SEL
mov.b #BIT5|BIT6|BIT7, &P1SEL2
;; BIT1: timer, short pulse
;; BIT4: timer, long pulse
mov.b #BIT1|BIT4, &P2DIR
mov.b #BIT1|BIT4, &P2SEL
;; BIT4: long pulse
;; BIT1: short pulse
mov.b #BIT1|BIT4,&P2DIR
mov.b #BIT1|BIT4,&P2SEL
;; timer configuration
;; configure and stop timer
@ -122,7 +122,7 @@ init:
;; spi configuration
;; USCI B to slave mode
mov.b #0x00, &UCB0CTL0
mov.b #UCSYNC, &UCB0CTL0
mov.b #0x00, &UCB0CTL1
;; make sure the isr will not immediately start
@ -136,7 +136,7 @@ init:
;; ----------------------------------------------------
mainloop:
;call #forwardscreen_init
call #forwardscreen_init
call #resetscreen
mainloop_draw:
@ -145,16 +145,13 @@ mainloop_draw:
;; signal waiting for data
set_signal_waiting_for_data
call #forwardscreen
call #wait
;; receive data via spi
;call #receivedata
;call #forwardscreen
;call #wait
call #receivedata
;; data has been received, clear signal
clear_signal_waiting_for_data
jmp mainloop_draw
@ -163,7 +160,7 @@ wait:
push r11
push r12
mov.w #0x0010, r11
mov.w #0x0040, r11
wait_continue_1:
mov.w #0xffff, r12
wait_continue_2:
@ -191,7 +188,7 @@ forwardscreen:
mov.w data_forward_pointer, r10
mov.b #_off, @r10
inc.w r10
mov.b #_white, @r10
mov.b #_blue, @r10
cmp.w r10, r8
jnz forwardscreen_done
mov.w #screendata, r10
@ -224,65 +221,48 @@ resetscreen_continue:
;; ----------------------------------------------------
receivedata:
push r7
push r8
push r9
push r10
;; screendata addresses
mov.w #screendata, r7
mov.w #screendataend, r8
;; wait for first octet
receivedata_wait_for_first_octet:
receivedata_wait_for_control_octet:
bit #UCB0RXIFG, &UC0IFG
jz receivedata_wait_for_first_octet
jz receivedata_wait_for_control_octet
;; get data from buffer register
;; get control or address octet from buffer register
mov.b UCB0RXBUF, r9
;; check whether value == 0xff (wait for the whole
;; check whether value == 0xff (wait for the whole
;; set of data to fill the screendata)
cmp.b #0xff, r9
;; receive all data
;; receive all data
jz receivedata_wait_for_all_data
;; check whether value == 0xfe (no more data)
cmp.b #0xfe, r9
;; no more data
jz receivedata_end
;; if it is not 0xff, it is the octet number which is the
;; relative address within screendata
;; it is an address octet
receivedata_wait_for_octet:
bit #UCB0RXIFG, &UC0IFG
jz receivedata_wait_for_octet
;; get octet from buffer register
;; get data octet from buffer register
mov.b UCB0RXBUF, r10
;; move it to the destination
mov.b r10, screendata(r9)
;; done
jmp receivedata_end
mov.b r10, screendata(r9)
;; next address/control octet
jmp receivedata_wait_for_control_octet
receivedata_wait_for_all_data:
;; this is a bit dangerous, if the application controller
;; sends too few data, we are in a dead lock
receivedata_end:
pop r10
pop r9
pop r8
pop r7
ret
;; ----------------------------------------------------
drawscreen:
push r7
@ -360,26 +340,26 @@ drawscreen_data_done:
;; ----------------------------------------------------
; --- timer isr ---
;; r6: exclusively used by isr as bit-counter
shifter_isr:
timer1_a0_isr:
;; check isr enable bit
bit #SIGNAL_ISR_ENABLE, SIGNAL_REGISTER
jz shifter_isr_exit
jz timer1_a0_isr_exit
;; shift msb of data register r5 into carry flag and set or reset P1.0 accordingly
rla.b DATA_REGISTER
jnc shifter_isr_false_bit
jnc timer1_a0_isr_false_bit
set_data_bit
jmp shifter_isr_end
shifter_isr_false_bit:
jmp timer1_a0_isr_end
timer1_a0_isr_false_bit:
clear_data_bit
shifter_isr_end:
timer1_a0_isr_end:
;; enable output
set_output_enable
;; roll bit-counter
rla.b BIT_COUNTER_REGISTER
jnc shifter_isr_exit
jnc timer1_a0_isr_exit
;; reset bit-counter
mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER
@ -388,19 +368,19 @@ shifter_isr_end:
;; check whether all data are processed
bit #SIGNAL_ALL_DATA_DONE, SIGNAL_REGISTER
jz shifter_isr_exit
jz timer1_a0_isr_exit
;; disable isr
bic #SIGNAL_ISR_ENABLE, SIGNAL_REGISTER
;; disable output
clear_output_enable
shifter_isr_exit:
timer1_a0_isr_exit:
reti
;; ----------------------------------------------------
.section "__interrupt_vector_14","ax",@progbits
.word shifter_isr
.word timer1_a0_isr
;; .resetvec comes from linker
.section ".resetvec","ax",@progbits