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works_agai
| Author | SHA1 | Date | |
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| 92fb90983f |
174
main.S
174
main.S
@ -7,36 +7,13 @@
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#define SP r1
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#define SR r2
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;; --- register usage --------------------------------
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;; r4: synchronization between main loop and isr
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;; bit0 signals byte done from isr
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;; r5: data byte to be handled by isr
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;; r6: bit-counter, only used within isr
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;; r7: screen data start/next pointer
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;; r8: screen data end pointer
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;; r9: next screen data byte, prepared in mainloop
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#define SIGNAL_INIT_VALUE 0x00
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#define SIGNAL_BYTE_DONE 0x01
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#define SIGNAL_ISR_ENABLE 0x02
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#define SIGNAL_REGISTER r4
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#define DATA_BYTE_REGISTER r5
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#define NEXT_DATA_BYTE_REGISTER r9
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#define DATA_NEXT_ADDRESS_REGISTER r7
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#define DATA_LAST_ADDRESS_REGISTER r8
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#define BIT_COUNTER_REGISTER r6
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#define BIT_COUNTER_INIT_VALUE 0x01
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;; ---------------------------------------------------
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.section ".rodata","a"
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screendata:
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.byte 0b00000001
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.byte 0b00000011
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.byte 0b00000111
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.byte 0b00001111
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.byte 0x01
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.byte 0x03
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.byte 0x07
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.byte 0x0f
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screendataend:
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.byte 0xff
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red:
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@ -66,121 +43,144 @@ green:
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.section ".text","ax",@progbits
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_start:
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;; disable watchdog
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mov.w #WDTPW|WDTHOLD, &WDTCTL
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mov.w #WDTPW|WDTHOLD,&WDTCTL
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;; configure clock system to the highest frequency
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mov.b #DCO0|DCO1|DCO2, &DCOCTL
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mov.b #XT2OFF|RSEL0|RSEL1|RSEL2|RSEL3, &BCSCTL1
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mov.b #0, &BCSCTL2
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mov.b #0, &BCSCTL3
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mov.b #DCO0|DCO1|DCO2,&DCOCTL
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mov.b #XT2OFF|RSEL0|RSEL1|RSEL2|RSEL3,&BCSCTL1
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mov.b #0,&BCSCTL2
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mov.b #0,&BCSCTL3
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;; initialize stack pointer with value from linker
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mov.w #__stack, SP
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mov.w #0xaaaa, r7
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mov.w #0x5555, r8
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init:
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;; configuration of GPIO Ports
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mov.b #BIT0|BIT1|BIT2, &P1DIR
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mov.b #BIT1|BIT4, &P2DIR
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mov.b #BIT1|BIT4, &P2SEL
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mov.b #BIT0|BIT1|BIT2,&P1DIR
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mov.b #0,&P1OUT
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mov.b #BIT1|BIT4,&P2DIR
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mov.b #BIT1|BIT4,&P2SEL
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;; timer configuration
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;; configure and stop timer
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;; cycle time is 56.25ns
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mov.w #ID_0|MC_0|TACLR|TASSEL_2, &TA1CTL
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mov.w #ID_0|MC_0|TACLR|TASSEL_2,&TA1CTL
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;; 2.0us
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mov.w #45, &TA1CCR0
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mov.w #45,&TA1CCR0
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;; a bit less
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mov.w #10, &TA1CCR1
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mov.w #22, &TA1CCR2
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mov.w #10,&TA1CCR1
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mov.w #22,&TA1CCR2
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;; configure output mode for TA0.1
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mov.w #CCIE, &TA1CCTL0
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mov.w #OUTMOD_7, &TA1CCTL1
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mov.w #OUTMOD_7, &TA1CCTL2
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mov.w #CCIE,&TA1CCTL0
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mov.w #OUTMOD_7,&TA1CCTL1
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mov.w #OUTMOD_7,&TA1CCTL2
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;; initialize bit-counter for isr
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mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER
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;; initialize isr-sync register
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mov.b #SIGNAL_INIT_VALUE, SIGNAL_REGISTER
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mov.b #0x01,r6
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;; initialize isr-sync register, signal BYTE_DONE for the first start
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mov.b #0x01,r4
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;; screen data start/next into DATA_NEXT_ADDRESS_REGISTER
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mov.w #screendata, DATA_NEXT_ADDRESS_REGISTER
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;; screen data end into DATA_LAST_ADDRESS_REGISTER
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mov.w #screendataend, DATA_LAST_ADDRESS_REGISTER
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;; load first screen data value into DATA_BYTE_REGISTER
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mov.b @DATA_NEXT_ADDRESS_REGISTER, DATA_BYTE_REGISTER
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inc.w DATA_NEXT_ADDRESS_REGISTER
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;; screen data start/next into r7
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mov.w #screendata, r7
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;; screen data end into r8
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mov.w #screendataend, r8
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;; start timer in up mode
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bis.w #MC0, &TA1CTL
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bis.w #MC0,&TA1CTL
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;; enable interrupts
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eint
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;; r4: synchronization between mainloop and isr
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;; r5: data byte to be handled by isr
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mainloop:
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;; prepare next byte to handle by isr
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;; first, check whether we are already at the end of screen data
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cmp.w DATA_NEXT_ADDRESS_REGISTER, DATA_LAST_ADDRESS_REGISTER
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jnz mainloop_prepare_next_byte
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;; in that case rollover to the start again
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mov.w #screendata, DATA_NEXT_ADDRESS_REGISTER
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mainloop_prepare_next_byte:
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;; load the byte from the screen data next pointer
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mov.b @DATA_NEXT_ADDRESS_REGISTER, NEXT_DATA_BYTE_REGISTER
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;; and increase the pointer
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inc.w DATA_NEXT_ADDRESS_REGISTER
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cmp.w r7,r8
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jz mainloop_data_done
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;; load next data byte
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mov.b @r7,r9
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inc.w r7
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mainloop_wait_for_isr:
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;; check bit0 in sync register, wait for the signal from
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;; the isr
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bit #SIGNAL_BYTE_DONE, SIGNAL_REGISTER
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;; check bit0 in sync register
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bit #0x01,r4
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jz mainloop_wait_for_isr
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;; load data
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mov.b NEXT_DATA_BYTE_REGISTER, DATA_BYTE_REGISTER
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;; clear the signal
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bic #SIGNAL_BYTE_DONE, SIGNAL_REGISTER
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;; mark the cycle
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bis #BIT2, &P1OUT
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bic #BIT2, &P1OUT
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mov.b r9,r5
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;; clear BYTE_DONE
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bic #0x01, r4
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;; enable isr
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bis #0x02, r4
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;; continue
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jmp mainloop
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mainloop_data_done:
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;; signal all data processed, isr finish
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bis #0x04, r4
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bis #BIT2, &P1OUT
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;; continue
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jmp mainloop
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; --- timer isr ---
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;; r6: exclusively used by isr as bit-counter
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timer1_a0_isr:
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;; func begin marker
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bis #BIT0, &P1OUT
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;; check isr idle bit
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bit #SIGNAL_ISR_ENABLE, SIGNAL_REGISTER
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jnz timer1_a0_isr_exit
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;; check isr enable bit
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bit #0x02,r4
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jz timer1_a0_isr_exit
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;; shift msb of data register r5 into carry flag and set or reset P1.1 accordingly
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rla.b DATA_BYTE_REGISTER
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;; shift msb of data register r5 into carry flag and set or reset P1.0 accordingly
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rla.b r5
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jnc timer1_a0_isr_false_bit
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bis #BIT1, &P1OUT
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bis #BIT0,&P1OUT
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jmp timer1_a0_isr_end
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timer1_a0_isr_false_bit:
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bic #BIT1, &P1OUT
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bic #BIT0,&P1OUT
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;; shift bit-counter, after eight shifts signal byte done and reset bit-counter
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timer1_a0_isr_end:
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rla.b BIT_COUNTER_REGISTER
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;; enable output
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bis #BIT1, &P1OUT
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;; roll bit-counter
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rla.b r6
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jnc timer1_a0_isr_exit
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;; reset bit-counter
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mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER
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mov.b #0x01,r6
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;; signal byte done
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bis #SIGNAL_BYTE_DONE, SIGNAL_REGISTER
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bis #0x01,r4
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bit #0x04, r4
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jz timer1_a0_isr_exit
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;; disable isr
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bic #0x02, r4
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;; disable output
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bic #BIT1, &P1OUT
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timer1_a0_isr_exit:
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;; func end marker
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bic #BIT0, &P1OUT
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reti
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;timer0_a1_isr:
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; reti
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; --- interrupt vectors ---
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; .section "__interrupt_vector_9","ax",@progbits
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; .word timer0_a1_isr
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.section "__interrupt_vector_14","ax",@progbits
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.word timer1_a0_isr
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;; .resetvec comes from linker
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.section ".resetvec","ax",@progbits
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.word _start
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