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base: wn:9fed0c4657d90699850aa2c56b0f3dd12bbd9b3b
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wn:main wn:prepare_spi_load_2 wn:prepare_spi_load wn:use_subroutine wn:broken wn:works_again
wn:works_with_led_and_static_data wn:cycler_works_include_output_stage
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compare: wn:works_again
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wn:main wn:prepare_spi_load_2 wn:prepare_spi_load wn:use_subroutine wn:broken wn:works_again
wn:works_with_led_and_static_data wn:cycler_works_include_output_stage

1 Commits
9fed0c4657 ... works_agai

Author SHA1 Message Date
Wolfgang Hottgenroth
92fb90983f cycles work now 2024-02-27 11:25:57 +01:00
1 changed files with 87 additions and 87 deletions
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174
main.S
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@ -7,36 +7,13 @@
#define SP r1 #define SP r1
#define SR r2 #define SR r2
;; --- register usage --------------------------------
;; r4: synchronization between main loop and isr
;; bit0 signals byte done from isr
;; r5: data byte to be handled by isr
;; r6: bit-counter, only used within isr
;; r7: screen data start/next pointer
;; r8: screen data end pointer
;; r9: next screen data byte, prepared in mainloop
#define SIGNAL_INIT_VALUE 0x00
#define SIGNAL_BYTE_DONE 0x01
#define SIGNAL_ISR_ENABLE 0x02
#define SIGNAL_REGISTER r4
#define DATA_BYTE_REGISTER r5
#define NEXT_DATA_BYTE_REGISTER r9
#define DATA_NEXT_ADDRESS_REGISTER r7
#define DATA_LAST_ADDRESS_REGISTER r8
#define BIT_COUNTER_REGISTER r6
#define BIT_COUNTER_INIT_VALUE 0x01
;; ---------------------------------------------------
.section ".rodata","a" .section ".rodata","a"
screendata: screendata:
.byte 0b00000001 .byte 0x01
.byte 0b00000011 .byte 0x03
.byte 0b00000111 .byte 0x07
.byte 0b00001111 .byte 0x0f
screendataend: screendataend:
.byte 0xff .byte 0xff
red: red:
@ -66,121 +43,144 @@ green:
.section ".text","ax",@progbits .section ".text","ax",@progbits
_start: _start:
;; disable watchdog ;; disable watchdog
mov.w #WDTPW|WDTHOLD, &WDTCTL mov.w #WDTPW|WDTHOLD,&WDTCTL
;; configure clock system to the highest frequency ;; configure clock system to the highest frequency
mov.b #DCO0|DCO1|DCO2, &DCOCTL mov.b #DCO0|DCO1|DCO2,&DCOCTL
mov.b #XT2OFF|RSEL0|RSEL1|RSEL2|RSEL3, &BCSCTL1 mov.b #XT2OFF|RSEL0|RSEL1|RSEL2|RSEL3,&BCSCTL1
mov.b #0, &BCSCTL2 mov.b #0,&BCSCTL2
mov.b #0, &BCSCTL3 mov.b #0,&BCSCTL3
;; initialize stack pointer with value from linker ;; initialize stack pointer with value from linker
mov.w #__stack, SP mov.w #__stack, SP
mov.w #0xaaaa, r7
mov.w #0x5555, r8
init: init:
;; configuration of GPIO Ports ;; configuration of GPIO Ports
mov.b #BIT0|BIT1|BIT2, &P1DIR mov.b #BIT0|BIT1|BIT2,&P1DIR
mov.b #BIT1|BIT4, &P2DIR mov.b #0,&P1OUT
mov.b #BIT1|BIT4, &P2SEL mov.b #BIT1|BIT4,&P2DIR
mov.b #BIT1|BIT4,&P2SEL
;; timer configuration ;; timer configuration
;; configure and stop timer ;; configure and stop timer
;; cycle time is 56.25ns ;; cycle time is 56.25ns
mov.w #ID_0|MC_0|TACLR|TASSEL_2, &TA1CTL mov.w #ID_0|MC_0|TACLR|TASSEL_2,&TA1CTL
;; 2.0us ;; 2.0us
mov.w #45, &TA1CCR0 mov.w #45,&TA1CCR0
;; a bit less ;; a bit less
mov.w #10, &TA1CCR1 mov.w #10,&TA1CCR1
mov.w #22, &TA1CCR2 mov.w #22,&TA1CCR2
;; configure output mode for TA0.1 ;; configure output mode for TA0.1
mov.w #CCIE, &TA1CCTL0 mov.w #CCIE,&TA1CCTL0
mov.w #OUTMOD_7, &TA1CCTL1 mov.w #OUTMOD_7,&TA1CCTL1
mov.w #OUTMOD_7, &TA1CCTL2 mov.w #OUTMOD_7,&TA1CCTL2
;; initialize bit-counter for isr ;; initialize bit-counter for isr
mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER mov.b #0x01,r6
;; initialize isr-sync register ;; initialize isr-sync register, signal BYTE_DONE for the first start
mov.b #SIGNAL_INIT_VALUE, SIGNAL_REGISTER mov.b #0x01,r4
;; screen data start/next into DATA_NEXT_ADDRESS_REGISTER ;; screen data start/next into r7
mov.w #screendata, DATA_NEXT_ADDRESS_REGISTER mov.w #screendata, r7
;; screen data end into DATA_LAST_ADDRESS_REGISTER ;; screen data end into r8
mov.w #screendataend, DATA_LAST_ADDRESS_REGISTER mov.w #screendataend, r8
;; load first screen data value into DATA_BYTE_REGISTER
mov.b @DATA_NEXT_ADDRESS_REGISTER, DATA_BYTE_REGISTER
inc.w DATA_NEXT_ADDRESS_REGISTER
;; start timer in up mode ;; start timer in up mode
bis.w #MC0, &TA1CTL bis.w #MC0,&TA1CTL
;; enable interrupts ;; enable interrupts
eint eint
;; r4: synchronization between mainloop and isr
;; r5: data byte to be handled by isr
mainloop: mainloop:
;; prepare next byte to handle by isr ;; prepare next byte to handle by isr
;; first, check whether we are already at the end of screen data cmp.w r7,r8
cmp.w DATA_NEXT_ADDRESS_REGISTER, DATA_LAST_ADDRESS_REGISTER jz mainloop_data_done
jnz mainloop_prepare_next_byte
;; in that case rollover to the start again ;; load next data byte
mov.w #screendata, DATA_NEXT_ADDRESS_REGISTER mov.b @r7,r9
mainloop_prepare_next_byte: inc.w r7
;; load the byte from the screen data next pointer
mov.b @DATA_NEXT_ADDRESS_REGISTER, NEXT_DATA_BYTE_REGISTER
;; and increase the pointer
inc.w DATA_NEXT_ADDRESS_REGISTER
mainloop_wait_for_isr: mainloop_wait_for_isr:
;; check bit0 in sync register, wait for the signal from ;; check bit0 in sync register
;; the isr bit #0x01,r4
bit #SIGNAL_BYTE_DONE, SIGNAL_REGISTER
jz mainloop_wait_for_isr jz mainloop_wait_for_isr
;; load data ;; load data
mov.b NEXT_DATA_BYTE_REGISTER, DATA_BYTE_REGISTER mov.b r9,r5
;; clear the signal ;; clear BYTE_DONE
bic #SIGNAL_BYTE_DONE, SIGNAL_REGISTER bic #0x01, r4
;; mark the cycle ;; enable isr
bis #BIT2, &P1OUT bis #0x02, r4
bic #BIT2, &P1OUT
;; continue ;; continue
jmp mainloop jmp mainloop
mainloop_data_done:
;; signal all data processed, isr finish
bis #0x04, r4
bis #BIT2, &P1OUT
;; continue
jmp mainloop
; --- timer isr --- ; --- timer isr ---
;; r6: exclusively used by isr as bit-counter ;; r6: exclusively used by isr as bit-counter
timer1_a0_isr: timer1_a0_isr:
;; func begin marker ;; check isr enable bit
bis #BIT0, &P1OUT bit #0x02,r4
;; check isr idle bit jz timer1_a0_isr_exit
bit #SIGNAL_ISR_ENABLE, SIGNAL_REGISTER
jnz timer1_a0_isr_exit
;; shift msb of data register r5 into carry flag and set or reset P1.1 accordingly ;; shift msb of data register r5 into carry flag and set or reset P1.0 accordingly
rla.b DATA_BYTE_REGISTER rla.b r5
jnc timer1_a0_isr_false_bit jnc timer1_a0_isr_false_bit
bis #BIT1, &P1OUT bis #BIT0,&P1OUT
jmp timer1_a0_isr_end jmp timer1_a0_isr_end
timer1_a0_isr_false_bit: timer1_a0_isr_false_bit:
bic #BIT1, &P1OUT bic #BIT0,&P1OUT
;; shift bit-counter, after eight shifts signal byte done and reset bit-counter
timer1_a0_isr_end: timer1_a0_isr_end:
rla.b BIT_COUNTER_REGISTER ;; enable output
bis #BIT1, &P1OUT
;; roll bit-counter
rla.b r6
jnc timer1_a0_isr_exit jnc timer1_a0_isr_exit
;; reset bit-counter ;; reset bit-counter
mov.b #BIT_COUNTER_INIT_VALUE, BIT_COUNTER_REGISTER mov.b #0x01,r6
;; signal byte done ;; signal byte done
bis #SIGNAL_BYTE_DONE, SIGNAL_REGISTER bis #0x01,r4
bit #0x04, r4
jz timer1_a0_isr_exit
;; disable isr
bic #0x02, r4
;; disable output
bic #BIT1, &P1OUT
timer1_a0_isr_exit: timer1_a0_isr_exit:
;; func end marker
bic #BIT0, &P1OUT
reti reti
;timer0_a1_isr:
; reti
; --- interrupt vectors ---
; .section "__interrupt_vector_9","ax",@progbits
; .word timer0_a1_isr
.section "__interrupt_vector_14","ax",@progbits
.word timer1_a0_isr
;; .resetvec comes from linker ;; .resetvec comes from linker
.section ".resetvec","ax",@progbits .section ".resetvec","ax",@progbits
.word _start .word _start