names refactor

2024-02-27 19:09:50 +01:00
parent c9b8fbba52
commit 40c49b6809
2 changed files with 10 additions and 4 deletions
--- a/main.S
+++ b/main.S
@ -41,6 +41,12 @@
  .macro clear_output_enable
  bic   #BIT1, &P1OUT
  .endm
+  .macro set_debug
+  bis   #BIT2, &P1OUT
+  .endm
+  .macro clear_debug
+  bic   #BIT2, &P1OUT
+  .endm

  .section ".data"
 screendata:
@ -171,7 +177,7 @@ mainloop_wait_for_isr_2:
 mainloop_data_done:
  ;; signal all data processed, isr finish
  bis     #SIGNAL_ALL_DATA_DONE,  SIGNAL_REGISTER
-  bis     #BIT2, &P1OUT
+  set_debug
  ;; continue
  jmp     mainloop