diff --git a/Debug/my_src/led.d b/Debug/my_src/led.d index fba068d..4a00ac2 100644 --- a/Debug/my_src/led.d +++ b/Debug/my_src/led.d @@ -19,6 +19,7 @@ my_src/led.o: ../my_src/led.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,4 +66,6 @@ my_src/led.o: ../my_src/led.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h: diff --git a/Debug/my_src/led.o b/Debug/my_src/led.o index f1ac5b8..6f98ab2 100644 Binary files a/Debug/my_src/led.o and b/Debug/my_src/led.o differ diff --git a/Debug/my_src/main2.d b/Debug/my_src/main2.d index 246e01e..34199d5 100644 --- a/Debug/my_src/main2.d +++ b/Debug/my_src/main2.d @@ -20,7 +20,8 @@ my_src/main2.o: ../my_src/main2.c \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h ../my_src/led.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../my_src/led.h /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h: @@ -68,4 +69,6 @@ my_src/main2.o: ../my_src/main2.c \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + ../my_src/led.h: diff --git a/Debug/my_src/main2.o b/Debug/my_src/main2.o index cf56ceb..44385a5 100644 Binary files a/Debug/my_src/main2.o and b/Debug/my_src/main2.o differ diff --git a/Debug/newcar.elf b/Debug/newcar.elf index ce444a8..3cbc22d 100755 Binary files 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file tasks 0x140 ./hottislib/PontCoopScheduler.o errno 0x4 ./system/src/newlib/_syscalls.o pFlash 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o +hspi1 0x58 ./src/main.o Discarded input sections @@ -67,6 +68,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -149,6 +151,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o @@ -173,8 +176,8 @@ Discarded input sections .text.HAL_SYSTICK_Callback 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o @@ -222,6 +225,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -274,6 +278,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -305,10 +310,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_ranges 0x0000000000000000 0x58 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x2a2 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2ac ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -356,9 +361,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_line 0x0000000000000000 0xde6 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_str 0x0000000000000000 0x8dcf1 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_line 0x0000000000000000 0xdfd ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_str 0x0000000000000000 0x8f084 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_frame 0x0000000000000000 0x128 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .ARM.attributes @@ -414,6 +420,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o @@ -453,10 +460,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_ranges 0x0000000000000000 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_flash.o @@ -504,9 +511,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_line 0x0000000000000000 0x6a7 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_str 0x0000000000000000 0x8dcd9 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_line 0x0000000000000000 0x6be ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_str 0x0000000000000000 0x8f06c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_frame 0x0000000000000000 0x138 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .ARM.attributes @@ -563,6 +571,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o @@ -606,10 +615,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x98 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_ranges 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x2ae ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2b8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o @@ -657,9 +666,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_line 0x0000000000000000 0x7c8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_str 0x0000000000000000 0x8ded7 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0x7df ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x8f26a ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_frame 0x0000000000000000 0x1a4 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .ARM.attributes @@ -715,6 +725,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o @@ -729,8 +740,8 @@ Discarded input sections .text.HAL_GPIO_EXTI_IRQHandler 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o @@ -778,6 +789,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -830,6 +842,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -847,10 +860,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_ranges 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -898,9 +911,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_line 0x0000000000000000 0x4db ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_str 0x0000000000000000 0x8da2f ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_line 0x0000000000000000 0x4f2 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_str 0x0000000000000000 0x8edc2 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_frame 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .ARM.attributes @@ -956,6 +970,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o @@ -1003,10 +1018,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0xa8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_ranges 0x0000000000000000 0x98 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x2fc ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x306 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o @@ -1054,9 +1069,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_line 0x0000000000000000 0x69a ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_str 0x0000000000000000 0x8dfa3 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_line 0x0000000000000000 0x6b1 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_str 0x0000000000000000 0x8f336 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_frame 0x0000000000000000 0x164 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .ARM.attributes @@ -1112,6 +1128,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o @@ -1136,8 +1153,8 @@ Discarded input sections .text.HAL_RCC_NMI_IRQHandler 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o @@ -1185,6 +1202,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1237,6 +1255,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1255,10 +1274,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_ranges 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1306,13 +1325,326 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_line 0x0000000000000000 0x5e4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_str 0x0000000000000000 0x8dbd2 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_line 0x0000000000000000 0x5fb ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_str 0x0000000000000000 0x8ef65 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_frame 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .ARM.attributes 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 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0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .text.SPI_ISCRCErrorValid + 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x8d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x35 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x9c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4a ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x97 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x30d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xfd ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1f ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x187 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x5e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x189 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x57 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x778 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x141 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2a ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x57 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o @@ -1371,10 +1703,10 @@ Discarded input sections .debug_abbrev 0x0000000000000000 0x4e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_aranges 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x29d ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2a7 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o @@ -1422,9 +1754,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_line 0x0000000000000000 0x480 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_str 0x0000000000000000 0x8d970 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_line 0x0000000000000000 0x497 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_str 0x0000000000000000 0x8ed03 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .ARM.attributes 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o @@ -1479,6 +1812,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -1486,10 +1820,10 @@ Discarded input sections .debug_abbrev 0x0000000000000000 0x4e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_aranges 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3a ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x186 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -1537,9 +1871,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_line 0x0000000000000000 0x483 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_str 0x0000000000000000 0x8d973 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_line 0x0000000000000000 0x49a ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_str 0x0000000000000000 0x8ed06 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .ARM.attributes 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -2191,12 +2526,13 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/main.o .group 0x0000000000000000 0x8 ./src/main.o .group 0x0000000000000000 0x8 ./src/main.o + .group 0x0000000000000000 0x8 ./src/main.o .text 0x0000000000000000 0x0 ./src/main.o .data 0x0000000000000000 0x0 ./src/main.o .bss 0x0000000000000000 0x0 ./src/main.o .debug_macro 0x0000000000000000 0x886 ./src/main.o - .debug_macro 0x0000000000000000 0x16 ./src/main.o - .debug_macro 0x0000000000000000 0x180 ./src/main.o + .debug_macro 0x0000000000000000 0x3a ./src/main.o + .debug_macro 0x0000000000000000 0x186 ./src/main.o .debug_macro 0x0000000000000000 0x2e ./src/main.o .debug_macro 0x0000000000000000 0x22 ./src/main.o .debug_macro 0x0000000000000000 0x34e ./src/main.o @@ -2244,6 +2580,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/main.o .debug_macro 0x0000000000000000 0x250 ./src/main.o .debug_macro 0x0000000000000000 0x143 ./src/main.o + .debug_macro 0x0000000000000000 0x1f4 ./src/main.o .debug_macro 0x0000000000000000 0xae ./src/main.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o @@ -2296,12 +2633,15 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .text 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o .data 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o .bss 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o + .text.HAL_SPI_MspDeInit + 0x0000000000000000 0x2c ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x886 ./src/stm32f1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x16 ./src/stm32f1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x180 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3a ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x186 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x2e ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x22 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x34e ./src/stm32f1xx_hal_msp.o @@ -2349,6 +2689,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x250 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x143 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1f4 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0xae ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o @@ -2401,12 +2742,13 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .text 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .data 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .bss 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x886 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000000000 0x16 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000000000 0x180 ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x3a ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x186 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x2e ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x22 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x34e ./src/stm32f1xx_it.o @@ -2454,6 +2796,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x250 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x143 ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x1f4 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0xae ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o @@ -2507,12 +2850,13 @@ Discarded input sections .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o + .group 0x0000000000000000 0x8 ./my_src/led.o .text 0x0000000000000000 0x0 ./my_src/led.o .data 0x0000000000000000 0x0 ./my_src/led.o .bss 0x0000000000000000 0x0 ./my_src/led.o .debug_macro 0x0000000000000000 0x886 ./my_src/led.o - .debug_macro 0x0000000000000000 0x16 ./my_src/led.o - .debug_macro 0x0000000000000000 0x180 ./my_src/led.o + .debug_macro 0x0000000000000000 0x3a ./my_src/led.o + .debug_macro 0x0000000000000000 0x186 ./my_src/led.o .debug_macro 0x0000000000000000 0x2e ./my_src/led.o .debug_macro 0x0000000000000000 0x22 ./my_src/led.o .debug_macro 0x0000000000000000 0x34e ./my_src/led.o @@ -2560,6 +2904,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./my_src/led.o .debug_macro 0x0000000000000000 0x250 ./my_src/led.o .debug_macro 0x0000000000000000 0x143 ./my_src/led.o + .debug_macro 0x0000000000000000 0x1f4 ./my_src/led.o .debug_macro 0x0000000000000000 0xae ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o @@ -2616,6 +2961,7 @@ Discarded input sections .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o + .group 0x0000000000000000 0x8 ./my_src/main2.o .text 0x0000000000000000 0x0 ./my_src/main2.o .data 0x0000000000000000 0x0 ./my_src/main2.o .bss 0x0000000000000000 0x0 ./my_src/main2.o @@ -2638,8 +2984,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x16 ./my_src/main2.o .debug_macro 0x0000000000000000 0x29 ./my_src/main2.o .debug_macro 0x0000000000000000 0x34e ./my_src/main2.o - .debug_macro 0x0000000000000000 0x16 ./my_src/main2.o - .debug_macro 0x0000000000000000 0x180 ./my_src/main2.o + .debug_macro 0x0000000000000000 0x3a ./my_src/main2.o + .debug_macro 0x0000000000000000 0x186 ./my_src/main2.o .debug_macro 0x0000000000000000 0x2e ./my_src/main2.o .debug_macro 0x0000000000000000 0x22 ./my_src/main2.o .debug_macro 0x0000000000000000 0x3a ./my_src/main2.o @@ -2672,6 +3018,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./my_src/main2.o .debug_macro 0x0000000000000000 0x250 ./my_src/main2.o .debug_macro 0x0000000000000000 0x143 ./my_src/main2.o + .debug_macro 0x0000000000000000 0x1f4 ./my_src/main2.o .debug_macro 0x0000000000000000 0xae ./my_src/main2.o .group 0x0000000000000000 0x8 ./hottislib/PontCoopScheduler.o .group 0x0000000000000000 0x8 ./hottislib/PontCoopScheduler.o @@ -2784,6 +3131,8 @@ LOAD ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o +LOAD ./system/src/stm32f1xx/stm32f1xx_hal_spi.o +LOAD ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_tim.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o LOAD ./system/src/newlib/_cxx.o @@ -2823,7 +3172,7 @@ END GROUP 0x000000002000bc00 __Main_Stack_Limit = (__stack - __Main_Stack_Size) [!provide] PROVIDE (_Main_Stack_Limit, __Main_Stack_Limit) 0x0000000000000100 _Minimum_Stack_Size = 0x100 - 0x0000000020000164 PROVIDE (_Heap_Begin, _end_noinit) + 0x00000000200001c0 PROVIDE (_Heap_Begin, _end_noinit) 0x000000002000bc00 PROVIDE (_Heap_Limit, (__stack - __Main_Stack_Size)) .isr_vector 0x0000000008000000 0x36c @@ -2847,16 +3196,16 @@ END GROUP .inits 0x000000000800036c 0x28 0x000000000800036c __data_regions_array_start = . - 0x000000000800036c 0x4 LONG 0x800181c LOADADDR (.data) + 0x000000000800036c 0x4 LONG 0x8001a98 LOADADDR (.data) 0x0000000008000370 0x4 LONG 0x20000000 ADDR (.data) 0x0000000008000374 0x4 LONG 0x20000014 (ADDR (.data) + SIZEOF (.data)) - 0x0000000008000378 0x4 LONG 0x800181c LOADADDR (.data_CCMRAM) + 0x0000000008000378 0x4 LONG 0x8001a98 LOADADDR (.data_CCMRAM) 0x000000000800037c 0x4 LONG 0x0 ADDR (.data_CCMRAM) 0x0000000008000380 0x4 LONG 0x0 (ADDR (.data_CCMRAM) + SIZEOF (.data_CCMRAM)) 0x0000000008000384 __data_regions_array_end = . 0x0000000008000384 __bss_regions_array_start = . 0x0000000008000384 0x4 LONG 0x20000014 ADDR (.bss) - 0x0000000008000388 0x4 LONG 0x20000164 (ADDR (.bss) + SIZEOF (.bss)) + 0x0000000008000388 0x4 LONG 0x200001c0 (ADDR (.bss) + SIZEOF (.bss)) 0x000000000800038c 0x4 LONG 0x0 ADDR (.bss_CCMRAM) 0x0000000008000390 0x4 LONG 0x0 (ADDR (.bss_CCMRAM) + SIZEOF (.bss_CCMRAM)) 0x0000000008000394 __bss_regions_array_end = . @@ -2882,7 +3231,7 @@ END GROUP .flashtext *(.flashtext .flashtext.*) -.text 0x0000000008000394 0x1488 +.text 0x0000000008000394 0x1704 *(.text .text.*) .text.HAL_InitTick 0x0000000008000394 0x28 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -2935,210 +3284,221 @@ END GROUP .text.HAL_RCC_GetHCLKFreq 0x0000000008001324 0xc ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o 0x0000000008001324 HAL_RCC_GetHCLKFreq - .text._exit 0x0000000008001330 0x4 ./system/src/newlib/_exit.o - 0x0000000008001330 _exit + .text.HAL_SPI_Init + 0x0000000008001330 0x190 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x0000000008001330 HAL_SPI_Init + .text._exit 0x00000000080014c0 0x4 ./system/src/newlib/_exit.o + 0x00000000080014c0 _exit .text.__initialize_args - 0x0000000008001334 0x10 ./system/src/newlib/_syscalls.o - 0x0000000008001334 __initialize_args + 0x00000000080014c4 0x10 ./system/src/newlib/_syscalls.o + 0x00000000080014c4 __initialize_args .text.__initialize_hardware_early - 0x0000000008001344 0x18 ./system/src/cortexm/_initialize_hardware.o - 0x0000000008001344 __initialize_hardware_early + 0x00000000080014d4 0x18 ./system/src/cortexm/_initialize_hardware.o + 0x00000000080014d4 __initialize_hardware_early .text.__initialize_hardware - 0x000000000800135c 0x8 ./system/src/cortexm/_initialize_hardware.o - 0x000000000800135c __initialize_hardware + 0x00000000080014ec 0x8 ./system/src/cortexm/_initialize_hardware.o + 0x00000000080014ec __initialize_hardware .text.Default_Handler - 0x0000000008001364 0x2 ./system/src/cmsis/startup_stm32f103xe.o - 0x0000000008001364 RTC_Alarm_IRQHandler - 0x0000000008001364 EXTI2_IRQHandler - 0x0000000008001364 TIM8_TRG_COM_IRQHandler - 0x0000000008001364 TIM8_CC_IRQHandler - 0x0000000008001364 TIM1_CC_IRQHandler - 0x0000000008001364 TIM6_IRQHandler - 0x0000000008001364 PVD_IRQHandler - 0x0000000008001364 SDIO_IRQHandler - 0x0000000008001364 EXTI3_IRQHandler - 0x0000000008001364 EXTI0_IRQHandler - 0x0000000008001364 I2C2_EV_IRQHandler - 0x0000000008001364 ADC1_2_IRQHandler - 0x0000000008001364 SPI1_IRQHandler - 0x0000000008001364 TAMPER_IRQHandler - 0x0000000008001364 TIM8_UP_IRQHandler - 0x0000000008001364 DMA2_Channel2_IRQHandler - 0x0000000008001364 DMA1_Channel4_IRQHandler - 0x0000000008001364 USART3_IRQHandler - 0x0000000008001364 RTC_IRQHandler - 0x0000000008001364 DMA1_Channel7_IRQHandler - 0x0000000008001364 CAN1_RX1_IRQHandler - 0x0000000008001364 UART5_IRQHandler - 0x0000000008001364 ADC3_IRQHandler - 0x0000000008001364 TIM4_IRQHandler - 0x0000000008001364 DMA2_Channel1_IRQHandler - 0x0000000008001364 I2C1_EV_IRQHandler - 0x0000000008001364 DMA1_Channel6_IRQHandler - 0x0000000008001364 UART4_IRQHandler - 0x0000000008001364 TIM3_IRQHandler - 0x0000000008001364 RCC_IRQHandler - 0x0000000008001364 TIM1_TRG_COM_IRQHandler - 0x0000000008001364 DMA1_Channel1_IRQHandler - 0x0000000008001364 Default_Handler - 0x0000000008001364 EXTI15_10_IRQHandler - 0x0000000008001364 TIM7_IRQHandler - 0x0000000008001364 TIM5_IRQHandler - 0x0000000008001364 EXTI9_5_IRQHandler - 0x0000000008001364 SPI2_IRQHandler - 0x0000000008001364 DMA1_Channel5_IRQHandler - 0x0000000008001364 EXTI4_IRQHandler - 0x0000000008001364 USB_LP_CAN1_RX0_IRQHandler - 0x0000000008001364 USB_HP_CAN1_TX_IRQHandler - 0x0000000008001364 DMA1_Channel3_IRQHandler - 0x0000000008001364 FSMC_IRQHandler - 0x0000000008001364 TIM1_UP_IRQHandler - 0x0000000008001364 WWDG_IRQHandler - 0x0000000008001364 TIM2_IRQHandler - 0x0000000008001364 TIM1_BRK_IRQHandler - 0x0000000008001364 EXTI1_IRQHandler - 0x0000000008001364 DMA2_Channel4_5_IRQHandler - 0x0000000008001364 USART2_IRQHandler - 0x0000000008001364 I2C2_ER_IRQHandler - 0x0000000008001364 DMA1_Channel2_IRQHandler - 0x0000000008001364 TIM8_BRK_IRQHandler - 0x0000000008001364 CAN1_SCE_IRQHandler - 0x0000000008001364 FLASH_IRQHandler - 0x0000000008001364 USART1_IRQHandler - 0x0000000008001364 SPI3_IRQHandler - 0x0000000008001364 I2C1_ER_IRQHandler - 0x0000000008001364 USBWakeUp_IRQHandler - 0x0000000008001364 DMA2_Channel3_IRQHandler - *fill* 0x0000000008001366 0x2 + 0x00000000080014f4 0x2 ./system/src/cmsis/startup_stm32f103xe.o + 0x00000000080014f4 RTC_Alarm_IRQHandler + 0x00000000080014f4 EXTI2_IRQHandler + 0x00000000080014f4 TIM8_TRG_COM_IRQHandler + 0x00000000080014f4 TIM8_CC_IRQHandler + 0x00000000080014f4 TIM1_CC_IRQHandler + 0x00000000080014f4 TIM6_IRQHandler + 0x00000000080014f4 PVD_IRQHandler + 0x00000000080014f4 SDIO_IRQHandler + 0x00000000080014f4 EXTI3_IRQHandler + 0x00000000080014f4 EXTI0_IRQHandler + 0x00000000080014f4 I2C2_EV_IRQHandler + 0x00000000080014f4 ADC1_2_IRQHandler + 0x00000000080014f4 SPI1_IRQHandler + 0x00000000080014f4 TAMPER_IRQHandler + 0x00000000080014f4 TIM8_UP_IRQHandler + 0x00000000080014f4 DMA2_Channel2_IRQHandler + 0x00000000080014f4 DMA1_Channel4_IRQHandler + 0x00000000080014f4 USART3_IRQHandler + 0x00000000080014f4 RTC_IRQHandler + 0x00000000080014f4 DMA1_Channel7_IRQHandler + 0x00000000080014f4 CAN1_RX1_IRQHandler + 0x00000000080014f4 UART5_IRQHandler + 0x00000000080014f4 ADC3_IRQHandler + 0x00000000080014f4 TIM4_IRQHandler + 0x00000000080014f4 DMA2_Channel1_IRQHandler + 0x00000000080014f4 I2C1_EV_IRQHandler + 0x00000000080014f4 DMA1_Channel6_IRQHandler + 0x00000000080014f4 UART4_IRQHandler + 0x00000000080014f4 TIM3_IRQHandler + 0x00000000080014f4 RCC_IRQHandler + 0x00000000080014f4 TIM1_TRG_COM_IRQHandler + 0x00000000080014f4 DMA1_Channel1_IRQHandler + 0x00000000080014f4 Default_Handler + 0x00000000080014f4 EXTI15_10_IRQHandler + 0x00000000080014f4 TIM7_IRQHandler + 0x00000000080014f4 TIM5_IRQHandler + 0x00000000080014f4 EXTI9_5_IRQHandler + 0x00000000080014f4 SPI2_IRQHandler + 0x00000000080014f4 DMA1_Channel5_IRQHandler + 0x00000000080014f4 EXTI4_IRQHandler + 0x00000000080014f4 USB_LP_CAN1_RX0_IRQHandler + 0x00000000080014f4 USB_HP_CAN1_TX_IRQHandler + 0x00000000080014f4 DMA1_Channel3_IRQHandler + 0x00000000080014f4 FSMC_IRQHandler + 0x00000000080014f4 TIM1_UP_IRQHandler + 0x00000000080014f4 WWDG_IRQHandler + 0x00000000080014f4 TIM2_IRQHandler + 0x00000000080014f4 TIM1_BRK_IRQHandler + 0x00000000080014f4 EXTI1_IRQHandler + 0x00000000080014f4 DMA2_Channel4_5_IRQHandler + 0x00000000080014f4 USART2_IRQHandler + 0x00000000080014f4 I2C2_ER_IRQHandler + 0x00000000080014f4 DMA1_Channel2_IRQHandler + 0x00000000080014f4 TIM8_BRK_IRQHandler + 0x00000000080014f4 CAN1_SCE_IRQHandler + 0x00000000080014f4 FLASH_IRQHandler + 0x00000000080014f4 USART1_IRQHandler + 0x00000000080014f4 SPI3_IRQHandler + 0x00000000080014f4 I2C1_ER_IRQHandler + 0x00000000080014f4 USBWakeUp_IRQHandler + 0x00000000080014f4 DMA2_Channel3_IRQHandler + *fill* 0x00000000080014f6 0x2 .text.SystemInit - 0x0000000008001368 0x4c ./system/src/cmsis/system_stm32f1xx.o - 0x0000000008001368 SystemInit + 0x00000000080014f8 0x4c ./system/src/cmsis/system_stm32f1xx.o + 0x00000000080014f8 SystemInit .text.SystemCoreClockUpdate - 0x00000000080013b4 0x94 ./system/src/cmsis/system_stm32f1xx.o - 0x00000000080013b4 SystemCoreClockUpdate + 0x0000000008001544 0x94 ./system/src/cmsis/system_stm32f1xx.o + 0x0000000008001544 SystemCoreClockUpdate .text.MX_GPIO_Init - 0x0000000008001448 0x5c ./src/main.o + 0x00000000080015d8 0x7c ./src/main.o .text.Error_Handler - 0x00000000080014a4 0x8 ./src/main.o - 0x00000000080014a4 Error_Handler + 0x0000000008001654 0x8 ./src/main.o + 0x0000000008001654 Error_Handler + .text.MX_SPI1_Init + 0x000000000800165c 0x40 ./src/main.o .text.SystemClock_Config - 0x00000000080014ac 0x78 ./src/main.o - 0x00000000080014ac SystemClock_Config - .text.main 0x0000000008001524 0x1c ./src/main.o - 0x0000000008001524 main + 0x000000000800169c 0x78 ./src/main.o + 0x000000000800169c SystemClock_Config + .text.main 0x0000000008001714 0x20 ./src/main.o + 0x0000000008001714 main .text.assert_failed - 0x0000000008001540 0x4 ./src/main.o - 0x0000000008001540 assert_failed + 0x0000000008001734 0x4 ./src/main.o + 0x0000000008001734 assert_failed .text.HAL_MspInit - 0x0000000008001544 0x90 ./src/stm32f1xx_hal_msp.o - 0x0000000008001544 HAL_MspInit + 0x0000000008001738 0x90 ./src/stm32f1xx_hal_msp.o + 0x0000000008001738 HAL_MspInit + .text.HAL_SPI_MspInit + 0x00000000080017c8 0x58 ./src/stm32f1xx_hal_msp.o + 0x00000000080017c8 HAL_SPI_MspInit .text.NMI_Handler - 0x00000000080015d4 0x4 ./src/stm32f1xx_it.o - 0x00000000080015d4 NMI_Handler + 0x0000000008001820 0x4 ./src/stm32f1xx_it.o + 0x0000000008001820 NMI_Handler .text.HardFault_Handler - 0x00000000080015d8 0x4 ./src/stm32f1xx_it.o - 0x00000000080015d8 HardFault_Handler + 0x0000000008001824 0x4 ./src/stm32f1xx_it.o + 0x0000000008001824 HardFault_Handler .text.MemManage_Handler - 0x00000000080015dc 0x4 ./src/stm32f1xx_it.o - 0x00000000080015dc MemManage_Handler + 0x0000000008001828 0x4 ./src/stm32f1xx_it.o + 0x0000000008001828 MemManage_Handler .text.BusFault_Handler - 0x00000000080015e0 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e0 BusFault_Handler + 0x000000000800182c 0x4 ./src/stm32f1xx_it.o + 0x000000000800182c BusFault_Handler .text.UsageFault_Handler - 0x00000000080015e4 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e4 UsageFault_Handler + 0x0000000008001830 0x4 ./src/stm32f1xx_it.o + 0x0000000008001830 UsageFault_Handler .text.SVC_Handler - 0x00000000080015e8 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e8 SVC_Handler + 0x0000000008001834 0x4 ./src/stm32f1xx_it.o + 0x0000000008001834 SVC_Handler .text.DebugMon_Handler - 0x00000000080015ec 0x4 ./src/stm32f1xx_it.o - 0x00000000080015ec DebugMon_Handler + 0x0000000008001838 0x4 ./src/stm32f1xx_it.o + 0x0000000008001838 DebugMon_Handler .text.PendSV_Handler - 0x00000000080015f0 0x4 ./src/stm32f1xx_it.o - 0x00000000080015f0 PendSV_Handler + 0x000000000800183c 0x4 ./src/stm32f1xx_it.o + 0x000000000800183c PendSV_Handler .text.SysTick_Handler - 0x00000000080015f4 0xc ./src/stm32f1xx_it.o - 0x00000000080015f4 SysTick_Handler - .text.blink 0x0000000008001600 0x14 ./my_src/led.o - 0x0000000008001600 blink + 0x0000000008001840 0xc ./src/stm32f1xx_it.o + 0x0000000008001840 SysTick_Handler + .text.blink 0x000000000800184c 0x14 ./my_src/led.o + 0x000000000800184c blink .text.blinkInit - 0x0000000008001614 0x18 ./my_src/led.o - 0x0000000008001614 blinkInit + 0x0000000008001860 0x18 ./my_src/led.o + 0x0000000008001860 blinkInit .text.my_setup_1 - 0x000000000800162c 0x8 ./my_src/main2.o - 0x000000000800162c my_setup_1 - .text.my_loop 0x0000000008001634 0x8 ./my_src/main2.o - 0x0000000008001634 my_loop + 0x0000000008001878 0x8 ./my_src/main2.o + 0x0000000008001878 my_setup_1 + .text.my_loop 0x0000000008001880 0x8 ./my_src/main2.o + 0x0000000008001880 my_loop .text.HAL_SYSTICK_Callback - 0x000000000800163c 0x8 ./my_src/main2.o - 0x000000000800163c HAL_SYSTICK_Callback + 0x0000000008001888 0x8 ./my_src/main2.o + 0x0000000008001888 HAL_SYSTICK_Callback .text.my_errorHandler - 0x0000000008001644 0x4 ./my_src/main2.o - 0x0000000008001644 my_errorHandler + 0x0000000008001890 0x4 ./my_src/main2.o + 0x0000000008001890 my_errorHandler .text.my_setup_2 - 0x0000000008001648 0x8 ./my_src/main2.o - 0x0000000008001648 my_setup_2 - .text.schInit 0x0000000008001650 0x30 ./hottislib/PontCoopScheduler.o - 0x0000000008001650 schInit - .text.schAdd 0x0000000008001680 0x40 ./hottislib/PontCoopScheduler.o - 0x0000000008001680 schAdd - .text.schExec 0x00000000080016c0 0x58 ./hottislib/PontCoopScheduler.o - 0x00000000080016c0 schExec + 0x0000000008001894 0x8 ./my_src/main2.o + 0x0000000008001894 my_setup_2 + .text.schInit 0x000000000800189c 0x30 ./hottislib/PontCoopScheduler.o + 0x000000000800189c schInit + .text.schAdd 0x00000000080018cc 0x40 ./hottislib/PontCoopScheduler.o + 0x00000000080018cc schAdd + .text.schExec 0x000000000800190c 0x58 ./hottislib/PontCoopScheduler.o + 0x000000000800190c schExec .text.schUpdate - 0x0000000008001718 0x54 ./hottislib/PontCoopScheduler.o - 0x0000000008001718 schUpdate + 0x0000000008001964 0x54 ./hottislib/PontCoopScheduler.o + 0x0000000008001964 schUpdate *(.rodata .rodata.* .constdata .constdata.*) .rodata.str1.4 - 0x000000000800176c 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - *fill* 0x000000000800179b 0x1 + 0x00000000080019b8 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + *fill* 0x00000000080019e7 0x1 .rodata.str1.4 - 0x000000000800179c 0x2d ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - *fill* 0x00000000080017c9 0x3 - .rodata 0x00000000080017cc 0x12 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - *fill* 0x00000000080017de 0x2 + 0x00000000080019e8 0x2d ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + *fill* 0x0000000008001a15 0x3 + .rodata 0x0000000008001a18 0x12 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + *fill* 0x0000000008001a2a 0x2 .rodata.str1.4 - 0x00000000080017e0 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + 0x0000000008001a2c 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .rodata.str1.4 + 0x0000000008001a58 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x2f (size before relaxing) .rodata.AHBPrescTable - 0x000000000800180c 0x10 ./system/src/cmsis/system_stm32f1xx.o - 0x000000000800180c AHBPrescTable + 0x0000000008001a88 0x10 ./system/src/cmsis/system_stm32f1xx.o + 0x0000000008001a88 AHBPrescTable *(vtable) *(.eh_frame*) *(.glue_7) - .glue_7 0x000000000800181c 0x0 linker stubs + .glue_7 0x0000000008001a98 0x0 linker stubs *(.glue_7t) - .glue_7t 0x000000000800181c 0x0 linker stubs + .glue_7t 0x0000000008001a98 0x0 linker stubs -.vfp11_veneer 0x000000000800181c 0x0 - .vfp11_veneer 0x000000000800181c 0x0 linker stubs +.vfp11_veneer 0x0000000008001a98 0x0 + .vfp11_veneer 0x0000000008001a98 0x0 linker stubs -.v4_bx 0x000000000800181c 0x0 - .v4_bx 0x000000000800181c 0x0 linker stubs +.v4_bx 0x0000000008001a98 0x0 + .v4_bx 0x0000000008001a98 0x0 linker stubs -.iplt 0x000000000800181c 0x0 - .iplt 0x000000000800181c 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o +.iplt 0x0000000008001a98 0x0 + .iplt 0x0000000008001a98 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o -.rel.dyn 0x000000000800181c 0x0 - .rel.iplt 0x000000000800181c 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o +.rel.dyn 0x0000000008001a98 0x0 + .rel.iplt 0x0000000008001a98 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .ARM.extab *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x000000000800181c . = ALIGN (0x4) - 0x000000000800181c __exidx_start = . + 0x0000000008001a98 . = ALIGN (0x4) + 0x0000000008001a98 __exidx_start = . .ARM.exidx *(.ARM.exidx* .gnu.linkonce.armexidx.*) - 0x000000000800181c __exidx_end = . - 0x000000000800181c . = ALIGN (0x4) - 0x000000000800181c _etext = . - 0x000000000800181c __etext = . + 0x0000000008001a98 __exidx_end = . + 0x0000000008001a98 . = ALIGN (0x4) + 0x0000000008001a98 _etext = . + 0x0000000008001a98 __etext = . -.data_CCMRAM 0x0000000000000000 0x0 load address 0x000000000800181c +.data_CCMRAM 0x0000000000000000 0x0 load address 0x0000000008001a98 FILL mask 0xff *(.data.CCMRAM .data.CCMRAM.*) 0x0000000000000000 . = ALIGN (0x4) - 0x000000000800181c _sidata = LOADADDR (.data) + 0x0000000008001a98 _sidata = LOADADDR (.data) -.data 0x0000000020000000 0x14 load address 0x000000000800181c +.data 0x0000000020000000 0x14 load address 0x0000000008001a98 FILL mask 0xff 0x0000000020000000 _sdata = . 0x0000000020000000 __data_start__ = . @@ -3156,47 +3516,53 @@ END GROUP 0x0000000020000014 _edata = . 0x0000000020000014 __data_end__ = . -.igot.plt 0x0000000020000014 0x0 load address 0x0000000008001830 +.igot.plt 0x0000000020000014 0x0 load address 0x0000000008001aac .igot.plt 0x0000000020000014 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .bss_CCMRAM 0x0000000000000000 0x0 *(.bss.CCMRAM .bss.CCMRAM.*) -.bss 0x0000000020000014 0x150 +.bss 0x0000000020000014 0x1ac 0x0000000020000014 __bss_start__ = . 0x0000000020000014 _sbss = . *(.bss_begin .bss_begin.*) .bss_begin 0x0000000020000014 0x4 ./system/src/newlib/_startup.o *(.bss .bss.*) .bss.uwTick 0x0000000020000018 0x4 ./system/src/stm32f1xx/stm32f1xx_hal.o - .bss.name.4281 - 0x000000002000001c 0x1 ./system/src/newlib/_syscalls.o - *(COMMON) + .bss.uCRCErrorWorkaroundCheck + 0x000000002000001c 0x1 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x000000002000001c uCRCErrorWorkaroundCheck *fill* 0x000000002000001d 0x3 - COMMON 0x0000000020000020 0x140 ./hottislib/PontCoopScheduler.o - 0x0000000020000020 tasks + .bss.name.4281 + 0x0000000020000020 0x1 ./system/src/newlib/_syscalls.o + *(COMMON) + *fill* 0x0000000020000021 0x3 + COMMON 0x0000000020000024 0x58 ./src/main.o + 0x0000000020000024 hspi1 + COMMON 0x000000002000007c 0x140 ./hottislib/PontCoopScheduler.o + 0x000000002000007c tasks *(.bss_end .bss_end.*) - .bss_end 0x0000000020000160 0x4 ./system/src/newlib/_startup.o - 0x0000000020000164 . = ALIGN (0x4) - 0x0000000020000164 __bss_end__ = . - 0x0000000020000164 _ebss = . + .bss_end 0x00000000200001bc 0x4 ./system/src/newlib/_startup.o + 0x00000000200001c0 . = ALIGN (0x4) + 0x00000000200001c0 __bss_end__ = . + 0x00000000200001c0 _ebss = . .noinit_CCMRAM *(.noinit.CCMRAM .noinit.CCMRAM.*) -.noinit 0x0000000020000164 0x0 - 0x0000000020000164 _noinit = . +.noinit 0x00000000200001c0 0x0 + 0x00000000200001c0 _noinit = . *(.noinit .noinit.*) - 0x0000000020000164 . = ALIGN (0x4) - 0x0000000020000164 _end_noinit = . + 0x00000000200001c0 . = ALIGN (0x4) + 0x00000000200001c0 _end_noinit = . [!provide] PROVIDE (end, _end_noinit) [!provide] PROVIDE (_end, _end_noinit) [!provide] PROVIDE (__end, _end_noinit) [!provide] PROVIDE (__end__, _end_noinit) -._check_stack 0x0000000020000164 0x100 - 0x0000000020000264 . = (. + _Minimum_Stack_Size) - *fill* 0x0000000020000164 0x100 +._check_stack 0x00000000200001c0 0x100 + 0x00000000200002c0 . = (. + _Minimum_Stack_Size) + *fill* 0x00000000200001c0 0x100 .b1text *(.b1text) @@ -3248,6 +3614,7 @@ END GROUP .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_exit.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_startup.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_syscalls.o @@ -3272,31 +3639,33 @@ END GROUP .ARM.attributes 0x0000000000000099 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .ARM.attributes - 0x00000000000000cc 0x33 ./system/src/newlib/_exit.o + 0x00000000000000cc 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o .ARM.attributes - 0x00000000000000ff 0x33 ./system/src/newlib/_startup.o + 0x00000000000000ff 0x33 ./system/src/newlib/_exit.o .ARM.attributes - 0x0000000000000132 0x33 ./system/src/newlib/_syscalls.o + 0x0000000000000132 0x33 ./system/src/newlib/_startup.o .ARM.attributes - 0x0000000000000165 0x33 ./system/src/cortexm/_initialize_hardware.o + 0x0000000000000165 0x33 ./system/src/newlib/_syscalls.o .ARM.attributes - 0x0000000000000198 0x33 ./system/src/cortexm/exception_handlers.o + 0x0000000000000198 0x33 ./system/src/cortexm/_initialize_hardware.o .ARM.attributes - 0x00000000000001cb 0x21 ./system/src/cmsis/startup_stm32f103xe.o + 0x00000000000001cb 0x33 ./system/src/cortexm/exception_handlers.o .ARM.attributes - 0x00000000000001ec 0x33 ./system/src/cmsis/system_stm32f1xx.o + 0x00000000000001fe 0x21 ./system/src/cmsis/startup_stm32f103xe.o .ARM.attributes - 0x000000000000021f 0x33 ./src/main.o + 0x000000000000021f 0x33 ./system/src/cmsis/system_stm32f1xx.o .ARM.attributes - 0x0000000000000252 0x33 ./src/stm32f1xx_hal_msp.o + 0x0000000000000252 0x33 ./src/main.o .ARM.attributes - 0x0000000000000285 0x33 ./src/stm32f1xx_it.o + 0x0000000000000285 0x33 ./src/stm32f1xx_hal_msp.o .ARM.attributes - 0x00000000000002b8 0x33 ./my_src/led.o + 0x00000000000002b8 0x33 ./src/stm32f1xx_it.o .ARM.attributes - 0x00000000000002eb 0x33 ./my_src/main2.o + 0x00000000000002eb 0x33 ./my_src/led.o .ARM.attributes - 0x000000000000031e 0x33 ./hottislib/PontCoopScheduler.o + 0x000000000000031e 0x33 ./my_src/main2.o + .ARM.attributes + 0x0000000000000351 0x33 ./hottislib/PontCoopScheduler.o .debug *(.debug) @@ -3310,7 +3679,7 @@ END GROUP .debug_sfnames *(.debug_sfnames) -.debug_aranges 0x0000000000000000 0x518 +.debug_aranges 0x0000000000000000 0x558 *(.debug_aranges) .debug_aranges 0x0000000000000000 0xb0 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -3321,160 +3690,170 @@ END GROUP .debug_aranges 0x0000000000000198 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_aranges - 0x0000000000000220 0x28 ./system/src/newlib/_exit.o + 0x0000000000000220 0x28 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o .debug_aranges - 0x0000000000000248 0x40 ./system/src/newlib/_startup.o + 0x0000000000000248 0x28 ./system/src/newlib/_exit.o .debug_aranges - 0x0000000000000288 0x30 ./system/src/newlib/_syscalls.o + 0x0000000000000270 0x40 ./system/src/newlib/_startup.o .debug_aranges - 0x00000000000002b8 0x28 ./system/src/cortexm/_initialize_hardware.o + 0x00000000000002b0 0x30 ./system/src/newlib/_syscalls.o .debug_aranges - 0x00000000000002e0 0x80 ./system/src/cortexm/exception_handlers.o + 0x00000000000002e0 0x28 ./system/src/cortexm/_initialize_hardware.o .debug_aranges - 0x0000000000000360 0x28 ./system/src/cmsis/startup_stm32f103xe.o + 0x0000000000000308 0x80 ./system/src/cortexm/exception_handlers.o .debug_aranges - 0x0000000000000388 0x28 ./system/src/cmsis/system_stm32f1xx.o + 0x0000000000000388 0x28 ./system/src/cmsis/startup_stm32f103xe.o .debug_aranges - 0x00000000000003b0 0x40 ./src/main.o + 0x00000000000003b0 0x28 ./system/src/cmsis/system_stm32f1xx.o .debug_aranges - 0x00000000000003f0 0x20 ./src/stm32f1xx_hal_msp.o + 0x00000000000003d8 0x48 ./src/main.o .debug_aranges - 0x0000000000000410 0x60 ./src/stm32f1xx_it.o + 0x0000000000000420 0x30 ./src/stm32f1xx_hal_msp.o .debug_aranges - 0x0000000000000470 0x28 ./my_src/led.o + 0x0000000000000450 0x60 ./src/stm32f1xx_it.o .debug_aranges - 0x0000000000000498 0x40 ./my_src/main2.o + 0x00000000000004b0 0x28 ./my_src/led.o .debug_aranges - 0x00000000000004d8 0x40 ./hottislib/PontCoopScheduler.o + 0x00000000000004d8 0x40 ./my_src/main2.o + .debug_aranges + 0x0000000000000518 0x40 ./hottislib/PontCoopScheduler.o .debug_pubnames *(.debug_pubnames) -.debug_info 0x0000000000000000 0x54d7 +.debug_info 0x0000000000000000 0x6625 *(.debug_info .gnu.linkonce.wi.*) .debug_info 0x0000000000000000 0x6e9 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_info 0x00000000000006e9 0xd53 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_info 0x000000000000143c 0x7f2 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_info 0x0000000000001c2e 0x155d ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_info 0x000000000000318b 0xee ./system/src/newlib/_exit.o - .debug_info 0x0000000000003279 0x455 ./system/src/newlib/_startup.o - .debug_info 0x00000000000036ce 0x1c7 ./system/src/newlib/_syscalls.o - .debug_info 0x0000000000003895 0x2b1 ./system/src/cortexm/_initialize_hardware.o - .debug_info 0x0000000000003b46 0x281 ./system/src/cortexm/exception_handlers.o - .debug_info 0x0000000000003dc7 0x72 ./system/src/cmsis/startup_stm32f103xe.o - .debug_info 0x0000000000003e39 0x3bc ./system/src/cmsis/system_stm32f1xx.o - .debug_info 0x00000000000041f5 0x786 ./src/main.o - .debug_info 0x000000000000497b 0x48a ./src/stm32f1xx_hal_msp.o - .debug_info 0x0000000000004e05 0x169 ./src/stm32f1xx_it.o - .debug_info 0x0000000000004f6e 0x1bf ./my_src/led.o - .debug_info 0x000000000000512d 0x15a ./my_src/main2.o - .debug_info 0x0000000000005287 0x250 ./hottislib/PontCoopScheduler.o + .debug_info 0x000000000000318b 0x6f6 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_info 0x0000000000003881 0xee ./system/src/newlib/_exit.o + .debug_info 0x000000000000396f 0x455 ./system/src/newlib/_startup.o + .debug_info 0x0000000000003dc4 0x1c7 ./system/src/newlib/_syscalls.o + .debug_info 0x0000000000003f8b 0x2b1 ./system/src/cortexm/_initialize_hardware.o + .debug_info 0x000000000000423c 0x281 ./system/src/cortexm/exception_handlers.o + .debug_info 0x00000000000044bd 0x72 ./system/src/cmsis/startup_stm32f103xe.o + .debug_info 0x000000000000452f 0x3bc ./system/src/cmsis/system_stm32f1xx.o + .debug_info 0x00000000000048eb 0xc26 ./src/main.o + .debug_info 0x0000000000005511 0xa42 ./src/stm32f1xx_hal_msp.o + .debug_info 0x0000000000005f53 0x169 ./src/stm32f1xx_it.o + .debug_info 0x00000000000060bc 0x1bf ./my_src/led.o + .debug_info 0x000000000000627b 0x15a ./my_src/main2.o + .debug_info 0x00000000000063d5 0x250 ./hottislib/PontCoopScheduler.o -.debug_abbrev 0x0000000000000000 0x168e +.debug_abbrev 0x0000000000000000 0x189b *(.debug_abbrev) .debug_abbrev 0x0000000000000000 0x21f ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_abbrev 0x000000000000021f 0x2d4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_abbrev 0x00000000000004f3 0x204 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_abbrev 0x00000000000006f7 0x278 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_abbrev 0x000000000000096f 0xbd ./system/src/newlib/_exit.o - .debug_abbrev 0x0000000000000a2c 0x1ac ./system/src/newlib/_startup.o - .debug_abbrev 0x0000000000000bd8 0xec ./system/src/newlib/_syscalls.o - .debug_abbrev 0x0000000000000cc4 0xea ./system/src/cortexm/_initialize_hardware.o - .debug_abbrev 0x0000000000000dae 0x118 ./system/src/cortexm/exception_handlers.o - .debug_abbrev 0x0000000000000ec6 0x12 ./system/src/cmsis/startup_stm32f103xe.o - .debug_abbrev 0x0000000000000ed8 0x125 ./system/src/cmsis/system_stm32f1xx.o - .debug_abbrev 0x0000000000000ffd 0x1c7 ./src/main.o - .debug_abbrev 0x00000000000011c4 0x126 ./src/stm32f1xx_hal_msp.o - .debug_abbrev 0x00000000000012ea 0xbb ./src/stm32f1xx_it.o - .debug_abbrev 0x00000000000013a5 0x10b ./my_src/led.o - .debug_abbrev 0x00000000000014b0 0xb6 ./my_src/main2.o - .debug_abbrev 0x0000000000001566 0x128 ./hottislib/PontCoopScheduler.o + .debug_abbrev 0x000000000000096f 0x16d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_abbrev 0x0000000000000adc 0xbd ./system/src/newlib/_exit.o + .debug_abbrev 0x0000000000000b99 0x1ac ./system/src/newlib/_startup.o + .debug_abbrev 0x0000000000000d45 0xec ./system/src/newlib/_syscalls.o + .debug_abbrev 0x0000000000000e31 0xea ./system/src/cortexm/_initialize_hardware.o + .debug_abbrev 0x0000000000000f1b 0x118 ./system/src/cortexm/exception_handlers.o + .debug_abbrev 0x0000000000001033 0x12 ./system/src/cmsis/startup_stm32f103xe.o + .debug_abbrev 0x0000000000001045 0x125 ./system/src/cmsis/system_stm32f1xx.o + .debug_abbrev 0x000000000000116a 0x1fe ./src/main.o + .debug_abbrev 0x0000000000001368 0x18f ./src/stm32f1xx_hal_msp.o + .debug_abbrev 0x00000000000014f7 0xbb ./src/stm32f1xx_it.o + .debug_abbrev 0x00000000000015b2 0x10b ./my_src/led.o + .debug_abbrev 0x00000000000016bd 0xb6 ./my_src/main2.o + .debug_abbrev 0x0000000000001773 0x128 ./hottislib/PontCoopScheduler.o -.debug_line 0x0000000000000000 0x4875 +.debug_line 0x0000000000000000 0x4f2e *(.debug_line) - .debug_line 0x0000000000000000 0x5e0 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_line 0x00000000000005e0 0x64d ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_line 0x0000000000000c2d 0x757 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_line 0x0000000000001384 0xada ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_line 0x0000000000001e5e 0x257 ./system/src/newlib/_exit.o - .debug_line 0x00000000000020b5 0x2bf ./system/src/newlib/_startup.o - .debug_line 0x0000000000002374 0x2c8 ./system/src/newlib/_syscalls.o - .debug_line 0x000000000000263c 0x173 ./system/src/cortexm/_initialize_hardware.o - .debug_line 0x00000000000027af 0x3b5 ./system/src/cortexm/exception_handlers.o - .debug_line 0x0000000000002b64 0x86 ./system/src/cmsis/startup_stm32f103xe.o - .debug_line 0x0000000000002bea 0x17b ./system/src/cmsis/system_stm32f1xx.o - .debug_line 0x0000000000002d65 0x50b ./src/main.o - .debug_line 0x0000000000003270 0x489 ./src/stm32f1xx_hal_msp.o - .debug_line 0x00000000000036f9 0x50e ./src/stm32f1xx_it.o - .debug_line 0x0000000000003c07 0x4c5 ./my_src/led.o - .debug_line 0x00000000000040cc 0x524 ./my_src/main2.o - .debug_line 0x00000000000045f0 0x285 ./hottislib/PontCoopScheduler.o + .debug_line 0x0000000000000000 0x5f7 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_line 0x00000000000005f7 0x664 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_line 0x0000000000000c5b 0x76e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_line 0x00000000000013c9 0xaf1 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_line 0x0000000000001eba 0x594 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_line 0x000000000000244e 0x257 ./system/src/newlib/_exit.o + .debug_line 0x00000000000026a5 0x2bf ./system/src/newlib/_startup.o + .debug_line 0x0000000000002964 0x2c8 ./system/src/newlib/_syscalls.o + .debug_line 0x0000000000002c2c 0x173 ./system/src/cortexm/_initialize_hardware.o + .debug_line 0x0000000000002d9f 0x3b5 ./system/src/cortexm/exception_handlers.o + .debug_line 0x0000000000003154 0x86 ./system/src/cmsis/startup_stm32f103xe.o + .debug_line 0x00000000000031da 0x17b ./system/src/cmsis/system_stm32f1xx.o + .debug_line 0x0000000000003355 0x547 ./src/main.o + .debug_line 0x000000000000389c 0x4d1 ./src/stm32f1xx_hal_msp.o + .debug_line 0x0000000000003d6d 0x525 ./src/stm32f1xx_it.o + .debug_line 0x0000000000004292 0x4dc ./my_src/led.o + .debug_line 0x000000000000476e 0x53b ./my_src/main2.o + .debug_line 0x0000000000004ca9 0x285 ./hottislib/PontCoopScheduler.o -.debug_frame 0x0000000000000000 0xa30 +.debug_frame 0x0000000000000000 0xac8 *(.debug_frame) .debug_frame 0x0000000000000000 0x168 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_frame 0x0000000000000168 0x144 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_frame 0x00000000000002ac 0xf8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_frame 0x00000000000003a4 0x16c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_frame 0x0000000000000510 0x38 ./system/src/newlib/_exit.o - .debug_frame 0x0000000000000548 0x7c ./system/src/newlib/_startup.o - .debug_frame 0x00000000000005c4 0x50 ./system/src/newlib/_syscalls.o - .debug_frame 0x0000000000000614 0x40 ./system/src/cortexm/_initialize_hardware.o - .debug_frame 0x0000000000000654 0xe8 ./system/src/cortexm/exception_handlers.o - .debug_frame 0x000000000000073c 0x30 ./system/src/cmsis/system_stm32f1xx.o - .debug_frame 0x000000000000076c 0x8c ./src/main.o - .debug_frame 0x00000000000007f8 0x2c ./src/stm32f1xx_hal_msp.o - .debug_frame 0x0000000000000824 0xa8 ./src/stm32f1xx_it.o - .debug_frame 0x00000000000008cc 0x40 ./my_src/led.o - .debug_frame 0x000000000000090c 0x80 ./my_src/main2.o - .debug_frame 0x000000000000098c 0xa4 ./hottislib/PontCoopScheduler.o + .debug_frame 0x0000000000000510 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_frame 0x0000000000000550 0x38 ./system/src/newlib/_exit.o + .debug_frame 0x0000000000000588 0x7c ./system/src/newlib/_startup.o + .debug_frame 0x0000000000000604 0x50 ./system/src/newlib/_syscalls.o + .debug_frame 0x0000000000000654 0x40 ./system/src/cortexm/_initialize_hardware.o + .debug_frame 0x0000000000000694 0xe8 ./system/src/cortexm/exception_handlers.o + .debug_frame 0x000000000000077c 0x30 ./system/src/cmsis/system_stm32f1xx.o + .debug_frame 0x00000000000007ac 0xa8 ./src/main.o + .debug_frame 0x0000000000000854 0x68 ./src/stm32f1xx_hal_msp.o + .debug_frame 0x00000000000008bc 0xa8 ./src/stm32f1xx_it.o + .debug_frame 0x0000000000000964 0x40 ./my_src/led.o + .debug_frame 0x00000000000009a4 0x80 ./my_src/main2.o + .debug_frame 0x0000000000000a24 0xa4 ./hottislib/PontCoopScheduler.o -.debug_str 0x0000000000000000 0x90f76 +.debug_str 0x0000000000000000 0x926f2 *(.debug_str) - .debug_str 0x0000000000000000 0x8db62 ./system/src/stm32f1xx/stm32f1xx_hal.o - 0x8e153 (size before relaxing) - .debug_str 0x000000000008db62 0x2cf ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - 0x8e155 (size before relaxing) - .debug_str 0x000000000008de31 0x452 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - 0x8de5d (size before relaxing) - .debug_str 0x000000000008e283 0x3d6 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - 0x8deb6 (size before relaxing) - .debug_str 0x000000000008e659 0x10b6 ./system/src/newlib/_exit.o + .debug_str 0x0000000000000000 0x8eef0 ./system/src/stm32f1xx/stm32f1xx_hal.o + 0x8f4e6 (size before relaxing) + .debug_str 0x000000000008eef0 0x2cf ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + 0x8f4e8 (size before relaxing) + .debug_str 0x000000000008f1bf 0x452 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + 0x8f1f0 (size before relaxing) + .debug_str 0x000000000008f611 0x3d6 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + 0x8f249 (size before relaxing) + .debug_str 0x000000000008f9e7 0x3c9 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x8f142 (size before relaxing) + .debug_str 0x000000000008fdb0 0x10b6 ./system/src/newlib/_exit.o 0x6e32 (size before relaxing) - .debug_str 0x000000000008f70f 0x266 ./system/src/newlib/_startup.o + .debug_str 0x0000000000090e66 0x266 ./system/src/newlib/_startup.o 0x5db6 (size before relaxing) - .debug_str 0x000000000008f975 0x11d8 ./system/src/newlib/_syscalls.o + .debug_str 0x00000000000910cc 0x11d8 ./system/src/newlib/_syscalls.o 0x6fdb (size before relaxing) - .debug_str 0x0000000000090b4d 0x77 ./system/src/cortexm/_initialize_hardware.o + .debug_str 0x00000000000922a4 0x77 ./system/src/cortexm/_initialize_hardware.o 0x61edb (size before relaxing) - .debug_str 0x0000000000090bc4 0x1ce ./system/src/cortexm/exception_handlers.o + .debug_str 0x000000000009231b 0x1ce ./system/src/cortexm/exception_handlers.o 0x667d0 (size before relaxing) - .debug_str 0x0000000000090d92 0x4d ./system/src/cmsis/system_stm32f1xx.o + .debug_str 0x00000000000924e9 0x4d ./system/src/cmsis/system_stm32f1xx.o 0x61f2f (size before relaxing) - .debug_str 0x0000000000090ddf 0x89 ./src/main.o - 0x8e02f (size before relaxing) - .debug_str 0x0000000000090e68 0x1b ./src/stm32f1xx_hal_msp.o - 0x8ddd3 (size before relaxing) - .debug_str 0x0000000000090e83 0x28 ./src/stm32f1xx_it.o - 0x8da1f (size before relaxing) - .debug_str 0x0000000000090eab 0x51 ./my_src/led.o - 0x8d9d8 (size before relaxing) - .debug_str 0x0000000000090efc 0x34 ./my_src/main2.o - 0x8dad1 (size before relaxing) - .debug_str 0x0000000000090f30 0x46 ./hottislib/PontCoopScheduler.o + .debug_str 0x0000000000092536 0x9c ./src/main.o + 0x8f76a (size before relaxing) + .debug_str 0x00000000000925d2 0x2d ./src/stm32f1xx_hal_msp.o + 0x8f58c (size before relaxing) + .debug_str 0x00000000000925ff 0x28 ./src/stm32f1xx_it.o + 0x8edb2 (size before relaxing) + .debug_str 0x0000000000092627 0x51 ./my_src/led.o + 0x8ed6b (size before relaxing) + .debug_str 0x0000000000092678 0x34 ./my_src/main2.o + 0x8ee64 (size before relaxing) + .debug_str 0x00000000000926ac 0x46 ./hottislib/PontCoopScheduler.o 0x5dc0 (size before relaxing) -.debug_loc 0x0000000000000000 0x17e7 +.debug_loc 0x0000000000000000 0x18d7 *(.debug_loc) .debug_loc 0x0000000000000000 0x81 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_loc 0x0000000000000081 0x58c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_loc 0x000000000000060d 0x446 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_loc 0x0000000000000a53 0x8ba ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_loc 0x000000000000130d 0x265 ./system/src/newlib/_startup.o - .debug_loc 0x0000000000001572 0x63 ./system/src/newlib/_syscalls.o - .debug_loc 0x00000000000015d5 0xdf ./system/src/cmsis/system_stm32f1xx.o - .debug_loc 0x00000000000016b4 0x21 ./my_src/led.o - .debug_loc 0x00000000000016d5 0x112 ./hottislib/PontCoopScheduler.o + .debug_loc 0x000000000000130d 0xa3 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_loc 0x00000000000013b0 0x265 ./system/src/newlib/_startup.o + .debug_loc 0x0000000000001615 0x63 ./system/src/newlib/_syscalls.o + .debug_loc 0x0000000000001678 0xdf ./system/src/cmsis/system_stm32f1xx.o + .debug_loc 0x0000000000001757 0x4d ./src/stm32f1xx_hal_msp.o + .debug_loc 0x00000000000017a4 0x21 ./my_src/led.o + .debug_loc 0x00000000000017c5 0x112 ./hottislib/PontCoopScheduler.o .debug_macinfo *(.debug_macinfo) @@ -3492,111 +3871,114 @@ END GROUP *(.debug_varnames) OUTPUT(newcar.elf elf32-littlearm) -.debug_ranges 0x0000000000000000 0x428 +.debug_ranges 0x0000000000000000 0x458 .debug_ranges 0x0000000000000000 0xa0 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_ranges 0x00000000000000a0 0x80 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_ranges 0x0000000000000120 0x48 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_ranges 0x0000000000000168 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_ranges 0x00000000000001e0 0x18 ./system/src/newlib/_exit.o - .debug_ranges 0x00000000000001f8 0x48 ./system/src/newlib/_startup.o - .debug_ranges 0x0000000000000240 0x20 ./system/src/newlib/_syscalls.o - .debug_ranges 0x0000000000000260 0x18 ./system/src/cortexm/_initialize_hardware.o - .debug_ranges 0x0000000000000278 0x70 ./system/src/cortexm/exception_handlers.o - .debug_ranges 0x00000000000002e8 0x20 ./system/src/cmsis/startup_stm32f103xe.o - .debug_ranges 0x0000000000000308 0x18 ./system/src/cmsis/system_stm32f1xx.o - .debug_ranges 0x0000000000000320 0x30 ./src/main.o - .debug_ranges 0x0000000000000350 0x10 ./src/stm32f1xx_hal_msp.o - .debug_ranges 0x0000000000000360 0x50 ./src/stm32f1xx_it.o - .debug_ranges 0x00000000000003b0 0x18 ./my_src/led.o - .debug_ranges 0x00000000000003c8 0x30 ./my_src/main2.o - .debug_ranges 0x00000000000003f8 0x30 ./hottislib/PontCoopScheduler.o + .debug_ranges 0x00000000000001e0 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_ranges 0x00000000000001f8 0x18 ./system/src/newlib/_exit.o + .debug_ranges 0x0000000000000210 0x48 ./system/src/newlib/_startup.o + .debug_ranges 0x0000000000000258 0x20 ./system/src/newlib/_syscalls.o + .debug_ranges 0x0000000000000278 0x18 ./system/src/cortexm/_initialize_hardware.o + .debug_ranges 0x0000000000000290 0x70 ./system/src/cortexm/exception_handlers.o + .debug_ranges 0x0000000000000300 0x20 ./system/src/cmsis/startup_stm32f103xe.o + .debug_ranges 0x0000000000000320 0x18 ./system/src/cmsis/system_stm32f1xx.o + .debug_ranges 0x0000000000000338 0x38 ./src/main.o + .debug_ranges 0x0000000000000370 0x20 ./src/stm32f1xx_hal_msp.o + .debug_ranges 0x0000000000000390 0x50 ./src/stm32f1xx_it.o + .debug_ranges 0x00000000000003e0 0x18 ./my_src/led.o + .debug_ranges 0x00000000000003f8 0x30 ./my_src/main2.o + .debug_ranges 0x0000000000000428 0x30 ./hottislib/PontCoopScheduler.o -.debug_macro 0x0000000000000000 0x1a328 - .debug_macro 0x0000000000000000 0x2c0 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000002c0 0x886 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000b46 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000b5c 0x180 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000cdc 0x2e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000d0a 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000d2c 0x34e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000000107a 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o +.debug_macro 0x0000000000000000 0x1a846 + .debug_macro 0x0000000000000000 0x2ca ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000002ca 0x886 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000b50 0x3a ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000b8a 0x186 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000d10 0x2e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000d3e 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000d60 0x34e ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_macro 0x00000000000010ae 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000010e2 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000001c70 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000123cd 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000012410 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015793 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000157b5 0x4c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015801 0x8d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001588e 0x35 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000158c3 0x9c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001595f 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015975 0x4a ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000159bf 0x97 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015a56 0x30d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015d63 0xfd ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015e60 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015e70 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015ec2 0x1f ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015ee1 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015f24 0x20 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015f44 0x187 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000160cb 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000160db 0x5e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016139 0x1c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016155 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161a7 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161e7 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161f7 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016237 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001630e 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016324 0x189 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000164ad 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016504 0x778 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016c7c 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017153 0x141 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017294 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017463 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017611 0x2a ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001763b 0x3c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017677 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000176ce 0x8c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001775a 0x250 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000179aa 0x143 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017aed 0xae ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017b9b 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000017e37 0x30c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000018143 0x2c0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000018403 0x19c ./system/src/newlib/_exit.o - .debug_macro 0x000000000001859f 0x10e ./system/src/newlib/_exit.o - .debug_macro 0x00000000000186ad 0x8d ./system/src/newlib/_exit.o - .debug_macro 0x000000000001873a 0x35 ./system/src/newlib/_exit.o - .debug_macro 0x000000000001876f 0x15b ./system/src/newlib/_startup.o - .debug_macro 0x00000000000188ca 0x1d1 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018a9b 0x1c ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ab7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ac7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ad7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ae7 0x35 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018b1c 0x122 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018c3e 0x88 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018cc6 0x10c ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018dd2 0x159 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018f2b 0x16 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018f41 0x8a ./system/src/cortexm/_initialize_hardware.o - .debug_macro 0x0000000000018fcb 0x217 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000191e2 0x3a ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001921c 0x22 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001923e 0x10 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001924e 0xcf ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001931d 0xbe ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000193db 0x10 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000193eb 0x8c ./system/src/cmsis/system_stm32f1xx.o - .debug_macro 0x0000000000019477 0x2a6 ./src/main.o - .debug_macro 0x000000000001971d 0x29c ./src/stm32f1xx_hal_msp.o - .debug_macro 0x00000000000199b9 0x2a6 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000019c5f 0x2a5 ./my_src/led.o - .debug_macro 0x0000000000019f04 0x10 ./my_src/led.o - .debug_macro 0x0000000000019f14 0x2de ./my_src/main2.o - .debug_macro 0x000000000001a1f2 0x1c ./my_src/main2.o - .debug_macro 0x000000000001a20e 0x11a ./hottislib/PontCoopScheduler.o + .debug_macro 0x00000000000010e2 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000001116 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000001ca4 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000012401 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000012444 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000157c7 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000157e9 0x4c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015835 0x8d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000158c2 0x35 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000158f7 0x9c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015993 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000159a9 0x4a ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000159f3 0x97 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015a8a 0x30d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015d97 0xfd ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015e94 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015ea4 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015ef6 0x1f ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015f15 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015f58 0x20 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015f78 0x187 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000160ff 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001610f 0x5e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001616d 0x1c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016189 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000161db 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001621b 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001622b 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001626b 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016342 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016358 0x189 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000164e1 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016538 0x778 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016cb0 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017187 0x141 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000172c8 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017497 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017645 0x2a ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001766f 0x3c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000176ab 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017702 0x8c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001778e 0x250 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000179de 0x143 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017b21 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017d15 0xae ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017dc3 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000018069 0x316 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x000000000001837f 0x2ca ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000018649 0x2a6 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x00000000000188ef 0x19c ./system/src/newlib/_exit.o + .debug_macro 0x0000000000018a8b 0x10e ./system/src/newlib/_exit.o + .debug_macro 0x0000000000018b99 0x8d ./system/src/newlib/_exit.o + .debug_macro 0x0000000000018c26 0x35 ./system/src/newlib/_exit.o + .debug_macro 0x0000000000018c5b 0x15b ./system/src/newlib/_startup.o + .debug_macro 0x0000000000018db6 0x1d1 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000018f87 0x1c ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000018fa3 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000018fb3 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000018fc3 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000018fd3 0x35 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000019008 0x122 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001912a 0x88 ./system/src/newlib/_syscalls.o + .debug_macro 0x00000000000191b2 0x10c ./system/src/newlib/_syscalls.o + .debug_macro 0x00000000000192be 0x159 ./system/src/newlib/_syscalls.o + .debug_macro 0x0000000000019417 0x16 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001942d 0x8a ./system/src/cortexm/_initialize_hardware.o + .debug_macro 0x00000000000194b7 0x217 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x00000000000196ce 0x3a ./system/src/cortexm/exception_handlers.o + .debug_macro 0x0000000000019708 0x22 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001972a 0x10 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001973a 0xcf ./system/src/cortexm/exception_handlers.o + .debug_macro 0x0000000000019809 0xbe ./system/src/cortexm/exception_handlers.o + .debug_macro 0x00000000000198c7 0x10 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x00000000000198d7 0x8c ./system/src/cmsis/system_stm32f1xx.o + .debug_macro 0x0000000000019963 0x2b0 ./src/main.o + .debug_macro 0x0000000000019c13 0x2a6 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000019eb9 0x2b0 ./src/stm32f1xx_it.o + .debug_macro 0x000000000001a169 0x2af ./my_src/led.o + .debug_macro 0x000000000001a418 0x10 ./my_src/led.o + .debug_macro 0x000000000001a428 0x2e8 ./my_src/main2.o + .debug_macro 0x000000000001a710 0x1c ./my_src/main2.o + .debug_macro 0x000000000001a72c 0x11a ./hottislib/PontCoopScheduler.o diff --git a/Debug/src/main.d b/Debug/src/main.d index 8c5d6a7..01acacd 100644 --- a/Debug/src/main.d +++ b/Debug/src/main.d @@ -19,6 +19,7 @@ src/main.o: ../src/main.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ /home/wn/workspace-stm32/newcar/my_src/main2.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,4 +66,6 @@ src/main.o: ../src/main.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + /home/wn/workspace-stm32/newcar/my_src/main2.h: diff --git a/Debug/src/main.o b/Debug/src/main.o index e63b4f7..798b645 100644 Binary files a/Debug/src/main.o and b/Debug/src/main.o differ diff --git a/Debug/src/stm32f1xx_hal_msp.d b/Debug/src/stm32f1xx_hal_msp.d index 2f2fa5c..1618181 100644 --- a/Debug/src/stm32f1xx_hal_msp.d +++ b/Debug/src/stm32f1xx_hal_msp.d @@ -19,7 +19,8 @@ src/stm32f1xx_hal_msp.o: ../src/stm32f1xx_hal_msp.c \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -64,3 +65,5 @@ src/stm32f1xx_hal_msp.o: ../src/stm32f1xx_hal_msp.c \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/src/stm32f1xx_hal_msp.o b/Debug/src/stm32f1xx_hal_msp.o index bbc0866..2073476 100644 Binary files a/Debug/src/stm32f1xx_hal_msp.o and b/Debug/src/stm32f1xx_hal_msp.o differ diff --git a/Debug/src/stm32f1xx_it.d b/Debug/src/stm32f1xx_it.d index 9a8c74d..a1bc312 100644 --- a/Debug/src/stm32f1xx_it.d +++ b/Debug/src/stm32f1xx_it.d @@ -20,6 +20,7 @@ src/stm32f1xx_it.o: ../src/stm32f1xx_it.c \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ ../include/stm32f1xx_it.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -66,4 +67,6 @@ src/stm32f1xx_it.o: ../src/stm32f1xx_it.c \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + ../include/stm32f1xx_it.h: diff --git a/Debug/src/stm32f1xx_it.o b/Debug/src/stm32f1xx_it.o index a19b59f..8cf954a 100644 Binary files a/Debug/src/stm32f1xx_it.o and b/Debug/src/stm32f1xx_it.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal.d index 06e945a..ce55fab 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal.o index 20b0d0f..3a045f1 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d index 49a0f1c..477a633 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_cortex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_cortex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o index d6f7902..f9458bc 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d index 113dcdc..f4211a6 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_dma.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_dma.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o index 8dd9e8c..d5509c9 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d index 6c43a89..95ea828 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_flash.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_flash.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o index 5cda21e..cb6e9f9 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d index b5b8763..bda10e5 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o index b650f4e..8e7642a 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d index acbae9f..2670dcc 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o index bb2c5f3..8131cd4 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d index 1d747bd..e808172 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o index 84dc04a..85fd4a9 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d index d7a4e56..2c73b9b 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_pwr.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_pwr.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o index 2ecec67..bae29f5 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d index 0805d1a..1dc8323 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o index 4197394..6b2c131 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d index 1b26b2f..51d827e 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o index 3b0062d..0c1799e 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d new file mode 100644 index 0000000..48fe3d4 --- /dev/null +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d @@ -0,0 +1,70 @@ +system/src/stm32f1xx/stm32f1xx_hal_spi.o: \ + ../system/src/stm32f1xx/stm32f1xx_hal_spi.c \ + ../system/include/stm32f1xx/stm32f1xx_hal.h \ + ../include/stm32f1xx_hal_conf.h ../include/mxconstants.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_def.h \ + ../system/include/cmsis/device/stm32f1xx.h \ + ../system/include/cmsis/device/stm32f103xe.h \ + ../system/include/cmsis/core_cm3.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/device/system_stm32f1xx.h \ + ../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h + +../system/include/stm32f1xx/stm32f1xx_hal.h: + +../include/stm32f1xx_hal_conf.h: + +../include/mxconstants.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc.h: + +../system/include/stm32f1xx/stm32f1xx_hal_def.h: + +../system/include/cmsis/device/stm32f1xx.h: + +../system/include/cmsis/device/stm32f103xe.h: + +../system/include/cmsis/core_cm3.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/device/system_stm32f1xx.h: + +../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_cortex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o new file mode 100644 index 0000000..16f0c2b Binary files /dev/null and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d new file mode 100644 index 0000000..62317b1 --- /dev/null +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d @@ -0,0 +1,70 @@ +system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o: \ + ../system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c \ + ../system/include/stm32f1xx/stm32f1xx_hal.h \ + ../include/stm32f1xx_hal_conf.h ../include/mxconstants.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_def.h \ + ../system/include/cmsis/device/stm32f1xx.h \ + ../system/include/cmsis/device/stm32f103xe.h \ + ../system/include/cmsis/core_cm3.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/device/system_stm32f1xx.h \ + ../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h + +../system/include/stm32f1xx/stm32f1xx_hal.h: + +../include/stm32f1xx_hal_conf.h: + +../include/mxconstants.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc.h: + +../system/include/stm32f1xx/stm32f1xx_hal_def.h: + +../system/include/cmsis/device/stm32f1xx.h: + +../system/include/cmsis/device/stm32f103xe.h: + +../system/include/cmsis/core_cm3.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/device/system_stm32f1xx.h: + +../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_cortex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o new file mode 100644 index 0000000..2babc72 Binary files /dev/null and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d index c41fd6d..272672c 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_tim.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_tim.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o index dae0bb6..b0722ff 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d index a9f0a32..bb425d8 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d @@ -20,7 +20,8 @@ system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +66,5 @@ system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o index a4f209c..971885d 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o differ diff --git a/Debug/system/src/stm32f1xx/subdir.mk b/Debug/system/src/stm32f1xx/subdir.mk index a8d9ebc..8a80c41 100644 --- a/Debug/system/src/stm32f1xx/subdir.mk +++ b/Debug/system/src/stm32f1xx/subdir.mk @@ -14,6 +14,8 @@ C_SRCS += \ ../system/src/stm32f1xx/stm32f1xx_hal_pwr.c \ ../system/src/stm32f1xx/stm32f1xx_hal_rcc.c \ ../system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.c \ +../system/src/stm32f1xx/stm32f1xx_hal_spi.c \ +../system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c \ ../system/src/stm32f1xx/stm32f1xx_hal_tim.c \ ../system/src/stm32f1xx/stm32f1xx_hal_tim_ex.c @@ -28,6 +30,8 @@ OBJS += \ ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o \ +./system/src/stm32f1xx/stm32f1xx_hal_spi.o \ +./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o \ ./system/src/stm32f1xx/stm32f1xx_hal_tim.o \ ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -42,6 +46,8 @@ C_DEPS += \ ./system/src/stm32f1xx/stm32f1xx_hal_pwr.d \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc.d \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d \ +./system/src/stm32f1xx/stm32f1xx_hal_spi.d \ +./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d \ ./system/src/stm32f1xx/stm32f1xx_hal_tim.d \ ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d diff --git a/cube/newcar/.mxproject b/cube/newcar/.mxproject index 07b0cc7..fcda3ce 100644 --- a/cube/newcar/.mxproject +++ b/cube/newcar/.mxproject @@ -5,9 +5,9 @@ SourcePath=/home/wn/workspace-stm32/newcar/cube/newcar/Src SourceFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;mxconstants.h;stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h; [PreviousUsedRideFiles] -SourceFiles=../Src/main.c;../Src/stm32f1xx_it.c;../Src/stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s; +SourceFiles=../Src/main.c;../Src/stm32f1xx_it.c;../Src/stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s; HeaderPath=../Drivers/STM32F1xx_HAL_Driver/Inc;../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Include;../Drivers/CMSIS/Device/ST/STM32F1xx/Include; diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h new file mode 100644 index 0000000..c131bc7 --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.h + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_SPI_H +#define __STM32F1xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI Directional mode state. + This parameter can be a value of @ref SPI_Direction_mode */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + +}SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + +}HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx transfer size */ + + uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx transfer size */ + + uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ + + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ + + HAL_LockTypeDef Lock; /*!< SPI locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +}SPI_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Codes SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ +/** + * @} + */ + + + + +/** @defgroup SPI_mode SPI mode + * @{ + */ +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) + +/** + * @} + */ + +/** @defgroup SPI_Direction_mode SPI Direction mode + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL + +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA + +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) + +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST + +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for STM32F1xx family + * @{ + */ +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) + +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN + +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg); \ +}while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ +}while(0) + + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Mode. + * This parameter can be a value of @ref SPI_mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction_mode + * @retval None + */ +#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__: specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_data_size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__: specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__: specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave select parameter is in allowed range. + * @param __NSS__: specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__: specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__: specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__: specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + + +/* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions --------------------------------------------------------*/ +/** @addtogroup SPI_Private_Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c new file mode 100644 index 0000000..0d873e5 --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + For 8 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + +--------------------------------------------------------------------------------------------------+ + + For 16 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | + +--------------------------------------------------------------------------------------------------+ + + note: + The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + + note: + TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_TxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxISR(SPI_HandleTypeDef *hspi); +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Configure communication direction : 1Line */ + SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Transmit data in 16 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Receive data in 16 Bit mode */ + else + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set to read data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive last data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* If CRC computation is enabled */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set: CRC Received */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + + /* Read CRC to clear RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); + } + else + { + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->RxISR = &SPI_RxISR; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size ; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->RxISR = &SPI_2LinesRxISR; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + { + /* SPI CRC error interrupt occurred ---------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + /* SPI Mode Fault error interrupt occurred --------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Overrun error interrupt occurred -----------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + } + + /* Call the Error call Back in case of Errors */ + if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : - This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback() could be implenetd in the user file. + - The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} + +/** + * @brief Return the SPI error code + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI Error Code + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + + + /** + * @brief Interrupt Handler to close Tx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + + /* Disable ERR interrupt if Receive process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + { + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Tx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to transmit amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + } + /* Transmit data in 16 Bit mode */ + else + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + } + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* calculate and transfer CRC on Tx line */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + SPI_TxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to close Rx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set to read CRC data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC to reset RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if ( (hspi->State != HAL_SPI_STATE_BUSY_RX) + || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) ) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); + + /* if Transmit process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Rx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to receive amount of data in 2Lines mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + if(hspi->RxXferCount==0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to receive amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set CRC Next to calculate CRC on Rx side */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + if(hspi->RxXferCount == 0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set (CRC ready) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State= HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ + return (SPI_VALID_CRC_ERROR); +} +/** + * @} + */ + + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c new file mode 100644 index 0000000..03e1d7e --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Extended SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities SPI extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/** @defgroup SPI_Private_Variables SPI Private Variables + * @{ + */ +/* Variable used to determine if device is impacted by implementation of workaround + related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: + - STM32F101CDE/STM32F103CDE + - Revision ID : Z + - SPI2 + - In receive only mode, with CRC calculation enabled, at the end of the CRC reception, + the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: + + If the value is 0, the complete data transfer is successful. + + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. + If CRCERR is found reset, the complete data transfer is considered successful. +*/ +uint8_t uCRCErrorWorkaroundCheck = 0; +/** + * @} + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + +#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif + +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for + CRC errors wrongly detected */ + /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode. + Revision ID information is only available in Debug mode, so Workaround could not be implemented + to distinguish Rev Z devices (issue present) from more recent version (issue fixed). + So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ + uCRCErrorWorkaroundCheck = 0; +#else + uCRCErrorWorkaroundCheck = 0; +#endif + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check how to handle this CRC error (workaround to be applied or not) */ + /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ + if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) ) + { + if (hspi->Instance->RXCRCR == 0) + { + return (SPI_INVALID_CRC_ERROR); + } + } + return (SPI_VALID_CRC_ERROR); +#else + return (SPI_VALID_CRC_ERROR); +#endif +} +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Inc/mxconstants.h b/cube/newcar/Inc/mxconstants.h index 5c470b1..b949aff 100644 --- a/cube/newcar/Inc/mxconstants.h +++ b/cube/newcar/Inc/mxconstants.h @@ -43,6 +43,12 @@ #define LED_Pin GPIO_PIN_13 #define LED_GPIO_Port GPIOC +#define OLED_DC_Pin GPIO_PIN_1 +#define OLED_DC_GPIO_Port GPIOA +#define OLED_RST_Pin GPIO_PIN_2 +#define OLED_RST_GPIO_Port GPIOA +#define OLED_CS_Pin GPIO_PIN_3 +#define OLED_CS_GPIO_Port GPIOA /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/cube/newcar/Inc/stm32f1xx_hal_conf.h b/cube/newcar/Inc/stm32f1xx_hal_conf.h index 46779fa..c93e9c2 100644 --- a/cube/newcar/Inc/stm32f1xx_hal_conf.h +++ b/cube/newcar/Inc/stm32f1xx_hal_conf.h @@ -75,7 +75,7 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_UART_MODULE_ENABLED */ diff --git a/cube/newcar/Src/main.c b/cube/newcar/Src/main.c index 53d6886..815190a 100644 --- a/cube/newcar/Src/main.c +++ b/cube/newcar/Src/main.c @@ -38,6 +38,7 @@ /* USER CODE END Includes */ /* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -48,6 +49,7 @@ void SystemClock_Config(void); void Error_Handler(void); static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -75,6 +77,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_SPI1_Init(); /* USER CODE BEGIN 2 */ @@ -131,6 +134,29 @@ void SystemClock_Config(void) HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } +/* SPI1 init function */ +static void MX_SPI1_Init(void) +{ + + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + +} + /** Configure pins as * Analog * Input @@ -150,12 +176,21 @@ static void MX_GPIO_Init(void) /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : OLED_DC_Pin OLED_RST_Pin OLED_CS_Pin */ + GPIO_InitStruct.Pin = OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ diff --git a/cube/newcar/Src/stm32f1xx_hal_msp.c b/cube/newcar/Src/stm32f1xx_hal_msp.c index 5b0181d..a807316 100644 --- a/cube/newcar/Src/stm32f1xx_hal_msp.c +++ b/cube/newcar/Src/stm32f1xx_hal_msp.c @@ -77,6 +77,65 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + } + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/cube/newcar/newcar.ioc b/cube/newcar/newcar.ioc index e5cfbe2..35d917d 100644 --- a/cube/newcar/newcar.ioc +++ b/cube/newcar/newcar.ioc @@ -4,17 +4,24 @@ KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=NVIC Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IPNb=3 +Mcu.IP2=SPI1 +Mcu.IP3=SYS +Mcu.IPNb=4 Mcu.Name=STM32F103V(C-D-E)Tx Mcu.Package=LQFP100 Mcu.Pin0=PC13-TAMPER-RTC Mcu.Pin1=OSC_IN +Mcu.Pin10=PA14 +Mcu.Pin11=VP_SYS_VS_Systick Mcu.Pin2=OSC_OUT -Mcu.Pin3=PA13 -Mcu.Pin4=PA14 -Mcu.Pin5=VP_SYS_VS_Systick -Mcu.PinsNb=6 +Mcu.Pin3=PA1 +Mcu.Pin4=PA2 +Mcu.Pin5=PA3 +Mcu.Pin6=PA5 +Mcu.Pin7=PA6 +Mcu.Pin8=PA7 +Mcu.Pin9=PA13 +Mcu.PinsNb=12 Mcu.UserConstants= Mcu.UserName=STM32F103VCTx MxCube.Version=4.16.1 @@ -33,10 +40,28 @@ OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=OLED_DC +PA1.Locked=true +PA1.Signal=GPIO_Output PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=OLED_RST +PA2.Locked=true +PA2.Signal=GPIO_Output +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=OLED_CS +PA3.Locked=true +PA3.Signal=GPIO_Output +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI PC13-TAMPER-RTC.GPIOParameters=GPIO_Label PC13-TAMPER-RTC.GPIO_Label=LED PC13-TAMPER-RTC.Locked=true @@ -72,7 +97,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=SW4STM32 ProjectManager.ToolChainLocation=/home/wn/workspace-stm32/newcar/cube/newcar ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false,2-MX_SPI1_Init-SPI1-false RCC.ADCFreqValue=36000000 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 @@ -100,6 +125,10 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 +SPI1.CalculateBaudRate=4.5 MBits/s +SPI1.IPParameters=Mode,BaudRatePrescaler,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=newcar diff --git a/include/mxconstants.h b/include/mxconstants.h index 5c470b1..b949aff 100644 --- a/include/mxconstants.h +++ b/include/mxconstants.h @@ -43,6 +43,12 @@ #define LED_Pin GPIO_PIN_13 #define LED_GPIO_Port GPIOC +#define OLED_DC_Pin GPIO_PIN_1 +#define OLED_DC_GPIO_Port GPIOA +#define OLED_RST_Pin GPIO_PIN_2 +#define OLED_RST_GPIO_Port GPIOA +#define OLED_CS_Pin GPIO_PIN_3 +#define OLED_CS_GPIO_Port GPIOA /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/include/stm32f1xx_hal_conf.h b/include/stm32f1xx_hal_conf.h index 46779fa..c93e9c2 100644 --- a/include/stm32f1xx_hal_conf.h +++ b/include/stm32f1xx_hal_conf.h @@ -75,7 +75,7 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_UART_MODULE_ENABLED */ diff --git a/src/main.c b/src/main.c index 2ee3b40..839b9b4 100644 --- a/src/main.c +++ b/src/main.c @@ -39,6 +39,7 @@ /* USER CODE END Includes */ /* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -49,6 +50,7 @@ void SystemClock_Config(void); void Error_Handler(void); static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -77,6 +79,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_SPI1_Init(); /* USER CODE BEGIN 2 */ my_setup_2(); @@ -135,6 +138,29 @@ void SystemClock_Config(void) HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } +/* SPI1 init function */ +static void MX_SPI1_Init(void) +{ + + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + +} + /** Configure pins as * Analog * Input @@ -154,12 +180,21 @@ static void MX_GPIO_Init(void) /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : OLED_DC_Pin OLED_RST_Pin OLED_CS_Pin */ + GPIO_InitStruct.Pin = OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ diff --git a/src/main.c-bak b/src/main.c-bak index 53d6886..815190a 100644 --- a/src/main.c-bak +++ b/src/main.c-bak @@ -38,6 +38,7 @@ /* USER CODE END Includes */ /* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -48,6 +49,7 @@ void SystemClock_Config(void); void Error_Handler(void); static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -75,6 +77,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_SPI1_Init(); /* USER CODE BEGIN 2 */ @@ -131,6 +134,29 @@ void SystemClock_Config(void) HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } +/* SPI1 init function */ +static void MX_SPI1_Init(void) +{ + + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + +} + /** Configure pins as * Analog * Input @@ -150,12 +176,21 @@ static void MX_GPIO_Init(void) /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : OLED_DC_Pin OLED_RST_Pin OLED_CS_Pin */ + GPIO_InitStruct.Pin = OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ diff --git a/src/stm32f1xx_hal_msp.c b/src/stm32f1xx_hal_msp.c index 5b0181d..a807316 100644 --- a/src/stm32f1xx_hal_msp.c +++ b/src/stm32f1xx_hal_msp.c @@ -77,6 +77,65 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + } + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/system/include/stm32f1xx/stm32f1xx_hal_spi.h b/system/include/stm32f1xx/stm32f1xx_hal_spi.h new file mode 100644 index 0000000..c131bc7 --- /dev/null +++ b/system/include/stm32f1xx/stm32f1xx_hal_spi.h @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.h + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_SPI_H +#define __STM32F1xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI Directional mode state. + This parameter can be a value of @ref SPI_Direction_mode */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + +}SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + +}HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx transfer size */ + + uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx transfer size */ + + uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ + + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ + + HAL_LockTypeDef Lock; /*!< SPI locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +}SPI_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Codes SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ +/** + * @} + */ + + + + +/** @defgroup SPI_mode SPI mode + * @{ + */ +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) + +/** + * @} + */ + +/** @defgroup SPI_Direction_mode SPI Direction mode + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL + +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA + +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) + +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST + +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for STM32F1xx family + * @{ + */ +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) + +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN + +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg); \ +}while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ +}while(0) + + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Mode. + * This parameter can be a value of @ref SPI_mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction_mode + * @retval None + */ +#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__: specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_data_size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__: specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__: specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave select parameter is in allowed range. + * @param __NSS__: specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__: specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__: specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__: specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + + +/* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions --------------------------------------------------------*/ +/** @addtogroup SPI_Private_Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f1xx/stm32f1xx_hal_spi.c b/system/src/stm32f1xx/stm32f1xx_hal_spi.c new file mode 100644 index 0000000..0d873e5 --- /dev/null +++ b/system/src/stm32f1xx/stm32f1xx_hal_spi.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + For 8 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + +--------------------------------------------------------------------------------------------------+ + + For 16 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | + +--------------------------------------------------------------------------------------------------+ + + note: + The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + + note: + TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_TxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxISR(SPI_HandleTypeDef *hspi); +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Configure communication direction : 1Line */ + SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Transmit data in 16 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Receive data in 16 Bit mode */ + else + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set to read data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive last data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* If CRC computation is enabled */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set: CRC Received */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + + /* Read CRC to clear RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); + } + else + { + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->RxISR = &SPI_RxISR; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size ; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->RxISR = &SPI_2LinesRxISR; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + { + /* SPI CRC error interrupt occurred ---------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + /* SPI Mode Fault error interrupt occurred --------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Overrun error interrupt occurred -----------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + } + + /* Call the Error call Back in case of Errors */ + if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : - This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback() could be implenetd in the user file. + - The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} + +/** + * @brief Return the SPI error code + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI Error Code + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + + + /** + * @brief Interrupt Handler to close Tx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + + /* Disable ERR interrupt if Receive process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + { + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Tx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to transmit amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + } + /* Transmit data in 16 Bit mode */ + else + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + } + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* calculate and transfer CRC on Tx line */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + SPI_TxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to close Rx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set to read CRC data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC to reset RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if ( (hspi->State != HAL_SPI_STATE_BUSY_RX) + || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) ) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); + + /* if Transmit process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Rx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to receive amount of data in 2Lines mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + if(hspi->RxXferCount==0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to receive amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set CRC Next to calculate CRC on Rx side */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + if(hspi->RxXferCount == 0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set (CRC ready) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State= HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ + return (SPI_VALID_CRC_ERROR); +} +/** + * @} + */ + + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c b/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c new file mode 100644 index 0000000..03e1d7e --- /dev/null +++ b/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Extended SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities SPI extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/** @defgroup SPI_Private_Variables SPI Private Variables + * @{ + */ +/* Variable used to determine if device is impacted by implementation of workaround + related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: + - STM32F101CDE/STM32F103CDE + - Revision ID : Z + - SPI2 + - In receive only mode, with CRC calculation enabled, at the end of the CRC reception, + the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: + + If the value is 0, the complete data transfer is successful. + + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. + If CRCERR is found reset, the complete data transfer is considered successful. +*/ +uint8_t uCRCErrorWorkaroundCheck = 0; +/** + * @} + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + +#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif + +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for + CRC errors wrongly detected */ + /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode. + Revision ID information is only available in Debug mode, so Workaround could not be implemented + to distinguish Rev Z devices (issue present) from more recent version (issue fixed). + So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ + uCRCErrorWorkaroundCheck = 0; +#else + uCRCErrorWorkaroundCheck = 0; +#endif + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check how to handle this CRC error (workaround to be applied or not) */ + /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ + if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) ) + { + if (hspi->Instance->RXCRCR == 0) + { + return (SPI_INVALID_CRC_ERROR); + } + } + return (SPI_VALID_CRC_ERROR); +#else + return (SPI_VALID_CRC_ERROR); +#endif +} +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/