diff --git a/Debug/my_src/led.d b/Debug/my_src/led.d index fba068d..50621a3 100644 --- a/Debug/my_src/led.d +++ b/Debug/my_src/led.d @@ -19,6 +19,9 @@ my_src/led.o: ../my_src/led.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h \ /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,4 +68,10 @@ my_src/led.o: ../my_src/led.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: + /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h: diff --git a/Debug/my_src/led.o b/Debug/my_src/led.o index f1ac5b8..d451d3f 100644 Binary files a/Debug/my_src/led.o and b/Debug/my_src/led.o differ diff --git a/Debug/my_src/main2.d b/Debug/my_src/main2.d index 246e01e..d0c05fe 100644 --- a/Debug/my_src/main2.d +++ b/Debug/my_src/main2.d @@ -20,7 +20,11 @@ my_src/main2.o: ../my_src/main2.c \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h ../my_src/led.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../my_src/led.h \ + ../my_src/oled.h /home/wn/workspace-stm32/newcar/hottislib/PontCoopScheduler.h: @@ -68,4 +72,12 @@ my_src/main2.o: ../my_src/main2.c \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: + ../my_src/led.h: + +../my_src/oled.h: diff --git a/Debug/my_src/main2.o b/Debug/my_src/main2.o index cf56ceb..4403fcd 100644 Binary files a/Debug/my_src/main2.o and b/Debug/my_src/main2.o differ diff --git a/Debug/my_src/oled.d b/Debug/my_src/oled.d new file mode 100644 index 0000000..66a5e34 --- /dev/null +++ b/Debug/my_src/oled.d @@ -0,0 +1,79 @@ +my_src/oled.o: ../my_src/oled.c ../my_src/oled.h ../my_src/oled-fonts.h \ + ../system/include/stm32f1xx/stm32f1xx_hal.h \ + ../include/stm32f1xx_hal_conf.h ../include/mxconstants.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_def.h \ + ../system/include/cmsis/device/stm32f1xx.h \ + ../system/include/cmsis/device/stm32f103xe.h \ + ../system/include/cmsis/core_cm3.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/device/system_stm32f1xx.h \ + ../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h + +../my_src/oled.h: + +../my_src/oled-fonts.h: + +../system/include/stm32f1xx/stm32f1xx_hal.h: + +../include/stm32f1xx_hal_conf.h: + +../include/mxconstants.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc.h: + +../system/include/stm32f1xx/stm32f1xx_hal_def.h: + +../system/include/cmsis/device/stm32f1xx.h: + +../system/include/cmsis/device/stm32f103xe.h: + +../system/include/cmsis/core_cm3.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/device/system_stm32f1xx.h: + +../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_cortex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/my_src/oled.o b/Debug/my_src/oled.o new file mode 100644 index 0000000..92792e4 Binary files /dev/null and b/Debug/my_src/oled.o differ diff --git a/Debug/my_src/subdir.mk b/Debug/my_src/subdir.mk index e24c2a3..99702bf 100644 --- a/Debug/my_src/subdir.mk +++ b/Debug/my_src/subdir.mk @@ -5,15 +5,18 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../my_src/led.c \ -../my_src/main2.c +../my_src/main2.c \ +../my_src/oled.c OBJS += \ ./my_src/led.o \ -./my_src/main2.o +./my_src/main2.o \ +./my_src/oled.o C_DEPS += \ ./my_src/led.d \ -./my_src/main2.d +./my_src/main2.d \ +./my_src/oled.d # Each subdirectory must supply rules for building sources it contributes diff --git a/Debug/newcar.elf b/Debug/newcar.elf index ce444a8..284083b 100755 Binary files a/Debug/newcar.elf and b/Debug/newcar.elf differ diff --git a/Debug/newcar.hex b/Debug/newcar.hex index e5f02d8..9cbb924 100644 --- a/Debug/newcar.hex +++ b/Debug/newcar.hex @@ -1,23 +1,23 @@ :020000040800F2 -:1000000000C00020F9020008D5150008D915000825 -:10001000DD150008E1150008E515000800000000E6 -:10002000000000000000000000000000E9150008CA -:10003000ED15000800000000F1150008F515000896 -:1000400065130008651300086513000865130008B0 -:1000500065130008651300086513000865130008A0 -:100060006513000865130008651300086513000890 -:100070006513000865130008651300086513000880 -:100080006513000865130008651300086513000870 -:100090006513000865130008651300086513000860 -:1000A0006513000865130008651300086513000850 -:1000B0006513000865130008651300086513000840 -:1000C0006513000865130008651300086513000830 -:1000D0006513000865130008651300086513000820 -:1000E0006513000865130008651300086513000810 -:1000F0006513000865130008651300086513000800 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+htim4 0x3c ./src/main.o tasks 0x140 ./hottislib/PontCoopScheduler.o errno 0x4 ./system/src/newlib/_syscalls.o pFlash 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o +htim3 0x3c ./src/main.o +htim1 0x3c ./src/main.o +hspi1 0x58 ./src/main.o +htim2 0x3c ./src/main.o Discarded input sections @@ -67,6 +73,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -149,6 +158,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o @@ -173,8 +185,8 @@ Discarded input sections .text.HAL_SYSTICK_Callback 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o @@ -222,6 +234,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -274,6 +289,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -305,10 +323,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_ranges 0x0000000000000000 0x58 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x2a2 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2c0 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o @@ -356,9 +374,12 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_line 0x0000000000000000 0xde6 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o - .debug_str 0x0000000000000000 0x8dcf1 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_line 0x0000000000000000 0xe2e ./system/src/stm32f1xx/stm32f1xx_hal_dma.o + .debug_str 0x0000000000000000 0x94987 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .debug_frame 0x0000000000000000 0x128 ./system/src/stm32f1xx/stm32f1xx_hal_dma.o .ARM.attributes @@ -414,6 +435,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o @@ -453,10 +477,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_ranges 0x0000000000000000 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_flash.o @@ -504,9 +528,12 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_line 0x0000000000000000 0x6a7 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o - .debug_str 0x0000000000000000 0x8dcd9 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_line 0x0000000000000000 0x6ef ./system/src/stm32f1xx/stm32f1xx_hal_flash.o + .debug_str 0x0000000000000000 0x9496f ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .debug_frame 0x0000000000000000 0x138 ./system/src/stm32f1xx/stm32f1xx_hal_flash.o .ARM.attributes @@ -563,6 +590,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o @@ -606,10 +636,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x98 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_ranges 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x2ae ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2cc ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o @@ -657,9 +687,12 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_line 0x0000000000000000 0x7c8 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o - .debug_str 0x0000000000000000 0x8ded7 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0x810 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x94b6d ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .debug_frame 0x0000000000000000 0x1a4 ./system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o .ARM.attributes @@ -715,6 +748,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o @@ -729,8 +765,8 @@ Discarded input sections .text.HAL_GPIO_EXTI_IRQHandler 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o @@ -778,6 +814,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -830,6 +869,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -847,10 +889,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_ranges 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o @@ -898,9 +940,12 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_line 0x0000000000000000 0x4db ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o - .debug_str 0x0000000000000000 0x8da2f ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_line 0x0000000000000000 0x523 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o + .debug_str 0x0000000000000000 0x946c5 ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .debug_frame 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o .ARM.attributes @@ -956,6 +1001,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o @@ -1003,10 +1051,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0xa8 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_ranges 0x0000000000000000 0x98 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x2fc ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x31a ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o @@ -1054,9 +1102,12 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_line 0x0000000000000000 0x69a ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o - .debug_str 0x0000000000000000 0x8dfa3 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_line 0x0000000000000000 0x6e2 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o + .debug_str 0x0000000000000000 0x94c39 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .debug_frame 0x0000000000000000 0x164 ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o .ARM.attributes @@ -1112,6 +1163,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o @@ -1136,8 +1190,8 @@ Discarded input sections .text.HAL_RCC_NMI_IRQHandler 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o @@ -1185,6 +1239,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1237,6 +1294,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1255,10 +1315,10 @@ Discarded input sections .debug_aranges 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_ranges 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o @@ -1306,13 +1366,319 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_line 0x0000000000000000 0x5e4 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o - .debug_str 0x0000000000000000 0x8dbd2 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_line 0x0000000000000000 0x62c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .debug_str 0x0000000000000000 0x94868 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .debug_frame 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o .ARM.attributes 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Init + 0x0000000000000000 0x198 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_DeInit + 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TransmitReceive + 0x0000000000000000 0x360 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Transmit_IT + 0x0000000000000000 0xd8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TransmitReceive_IT + 0x0000000000000000 0xec ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Receive_IT + 0x0000000000000000 0xc8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Transmit_DMA + 0x0000000000000000 0xf0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TransmitReceive_DMA + 0x0000000000000000 0x160 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Receive_DMA + 0x0000000000000000 0xf0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_DMAPause + 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_DMAResume + 0x0000000000000000 0x30 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_DMAStop + 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TxCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_RxCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TxRxCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TxHalfCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMAHalfTransmitCplt + 0x0000000000000000 0xc ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_RxHalfCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMAHalfReceiveCplt + 0x0000000000000000 0xc ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_TxRxHalfCpltCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMAHalfTransmitReceiveCplt + 0x0000000000000000 0xc ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_ErrorCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_TxCloseIRQHandler + 0x0000000000000000 0x98 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_TxISR + 0x0000000000000000 0x44 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMAError + 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMATransmitCplt + 0x0000000000000000 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMATransmitReceiveCplt + 0x0000000000000000 0xd0 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_IRQHandler + 0x0000000000000000 0xbc ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_GetError + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_ISCRCErrorValid + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Receive + 0x0000000000000000 0x230 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_RxCloseIRQHandler + 0x0000000000000000 0x108 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_RxISR + 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_2LinesRxISR + 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.SPI_DMAReceiveCplt + 0x0000000000000000 0xec ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x8d ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x35 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x9c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x4a ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x97 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x30d ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0xfd ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1f ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x187 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x5e ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x1c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 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0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .text.SPI_ISCRCErrorValid + 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x8d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x35 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x9c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4a ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x97 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x30d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xfd ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1f ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x43 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x20 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x187 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x5e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x52 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x189 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x57 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x778 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x141 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x2a ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x3c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x57 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o @@ -1367,14 +1733,189 @@ Discarded input sections .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_info 0x0000000000000000 0x99 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_abbrev 0x0000000000000000 0x4e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_aranges - 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x29d ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_TI2_SetConfig + 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_TI3_SetConfig + 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_TI4_SetConfig + 0x0000000000000000 0x34 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_DeInit + 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Start + 0x0000000000000000 0x70 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Stop + 0x0000000000000000 0x84 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Start_IT + 0x0000000000000000 0x6c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Stop_IT + 0x0000000000000000 0x80 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Start_DMA + 0x0000000000000000 0xb8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_Stop_DMA + 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_DeInit + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_DeInit + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_DeInit + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_DeInit + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_DeInit + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStart + 0x0000000000000000 0x244 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_DMABurst_WriteStop + 0x0000000000000000 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStart + 0x0000000000000000 0x244 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_DMABurst_ReadStop + 0x0000000000000000 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_GenerateEvent + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_ConfigOCrefClear + 0x0000000000000000 0x21c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_ConfigTI1Input + 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_SlaveConfigSynchronization_IT + 0x0000000000000000 0xd0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_ReadCapturedValue + 0x0000000000000000 0x13c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PeriodElapsedCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_DMAPeriodElapsedCplt + 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_DelayElapsedCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_CaptureCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_DMACaptureCplt + 0x0000000000000000 0x44 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_PulseFinishedCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_DMADelayPulseCplt + 0x0000000000000000 0x44 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_TriggerCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IRQHandler + 0x0000000000000000 0x174 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_DMATriggerCplt + 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_ErrorCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_DMAError + 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Base_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Init + 0x0000000000000000 0xc4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Init + 0x0000000000000000 0xc4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_Init + 0x0000000000000000 0xe8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Init + 0x0000000000000000 0x194 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_ConfigChannel + 0x0000000000000000 0x1a8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_TI1_SetConfig + 0x0000000000000000 0x84 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_ConfigChannel + 0x0000000000000000 0x200 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_ConfigChannel + 0x0000000000000000 0x200 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_CCxChannelCmd + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Start + 0x0000000000000000 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Stop + 0x0000000000000000 0xb8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Start_IT + 0x0000000000000000 0xd4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Stop_IT + 0x0000000000000000 0xfc ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Start_DMA + 0x0000000000000000 0x170 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OC_Stop_DMA + 0x0000000000000000 0x104 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Start + 0x0000000000000000 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Stop + 0x0000000000000000 0xc0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Start_IT + 0x0000000000000000 0xd4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_IT + 0x0000000000000000 0xfc ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Start_DMA + 0x0000000000000000 0x170 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_Stop_DMA + 0x0000000000000000 0x104 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Start + 0x0000000000000000 0x6c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Stop + 0x0000000000000000 0x80 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Start_IT + 0x0000000000000000 0xb0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Stop_IT + 0x0000000000000000 0xc4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Start_DMA + 0x0000000000000000 0x184 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_IC_Stop_DMA + 0x0000000000000000 0x104 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start + 0x0000000000000000 0x44 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop + 0x0000000000000000 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_Start_IT + 0x0000000000000000 0x58 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_OnePulse_Stop_IT + 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Start + 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop + 0x0000000000000000 0x9c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_IT + 0x0000000000000000 0xb0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_IT + 0x0000000000000000 0xc8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Start_DMA + 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_Encoder_Stop_DMA + 0x0000000000000000 0xc8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o @@ -1422,12 +1963,13 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_line 0x0000000000000000 0x480 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .debug_str 0x0000000000000000 0x8d970 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o - .ARM.attributes - 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -1482,14 +2024,77 @@ Discarded input sections .text 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .data 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .bss 0x0000000000000000 0x0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_info 0x0000000000000000 0x99 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_abbrev 0x0000000000000000 0x4e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_aranges - 0x0000000000000000 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.TIM_CCxNChannelCmd + 0x0000000000000000 0x1c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Init + 0x0000000000000000 0x174 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_MspDeInit + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_DeInit + 0x0000000000000000 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start + 0x0000000000000000 0x5c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop + 0x0000000000000000 0x70 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_IT + 0x0000000000000000 0x68 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_IT + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Start_DMA + 0x0000000000000000 0xb4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_Stop_DMA + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start + 0x0000000000000000 0x54 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_IT + 0x0000000000000000 0xa4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_IT + 0x0000000000000000 0xd4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Start_DMA + 0x0000000000000000 0x134 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OCN_Stop_DMA + 0x0000000000000000 0xc8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start + 0x0000000000000000 0x54 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_IT + 0x0000000000000000 0xa4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_IT + 0x0000000000000000 0xd4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Start_DMA + 0x0000000000000000 0x134 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_PWMN_Stop_DMA + 0x0000000000000000 0xc8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start + 0x0000000000000000 0x4c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop + 0x0000000000000000 0x7c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Start_IT + 0x0000000000000000 0x60 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_OnePulseN_Stop_IT + 0x0000000000000000 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutationEvent + 0x0000000000000000 0xa0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutationEvent_IT + 0x0000000000000000 0xac ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_ConfigCommutationEvent_DMA + 0x0000000000000000 0xc0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_CommutationCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.TIMEx_DMACommutationCplt + 0x0000000000000000 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_BreakCallback + 0x0000000000000000 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .text.HAL_TIMEx_HallSensor_GetState + 0x0000000000000000 0x8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x886 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x16 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x180 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xca ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x18c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x2e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x22 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x34e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -1537,12 +2142,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x250 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x143 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x83e ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x11 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0xae ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_line 0x0000000000000000 0x483 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .debug_str 0x0000000000000000 0x8d973 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .comment 0x0000000000000000 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o - .ARM.attributes - 0x0000000000000000 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .group 0x0000000000000000 0x8 ./system/src/newlib/_cxx.o .group 0x0000000000000000 0x8 ./system/src/newlib/_cxx.o .group 0x0000000000000000 0x8 ./system/src/newlib/_cxx.o @@ -2191,12 +2794,15 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/main.o .group 0x0000000000000000 0x8 ./src/main.o .group 0x0000000000000000 0x8 ./src/main.o + .group 0x0000000000000000 0x8 ./src/main.o + .group 0x0000000000000000 0x8 ./src/main.o + .group 0x0000000000000000 0x8 ./src/main.o .text 0x0000000000000000 0x0 ./src/main.o .data 0x0000000000000000 0x0 ./src/main.o .bss 0x0000000000000000 0x0 ./src/main.o .debug_macro 0x0000000000000000 0x886 ./src/main.o - .debug_macro 0x0000000000000000 0x16 ./src/main.o - .debug_macro 0x0000000000000000 0x180 ./src/main.o + .debug_macro 0x0000000000000000 0xca ./src/main.o + .debug_macro 0x0000000000000000 0x18c ./src/main.o .debug_macro 0x0000000000000000 0x2e ./src/main.o .debug_macro 0x0000000000000000 0x22 ./src/main.o .debug_macro 0x0000000000000000 0x34e ./src/main.o @@ -2244,6 +2850,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/main.o .debug_macro 0x0000000000000000 0x250 ./src/main.o .debug_macro 0x0000000000000000 0x143 ./src/main.o + .debug_macro 0x0000000000000000 0x1f4 ./src/main.o + .debug_macro 0x0000000000000000 0x83e ./src/main.o + .debug_macro 0x0000000000000000 0x11 ./src/main.o .debug_macro 0x0000000000000000 0xae ./src/main.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o @@ -2296,12 +2905,19 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_hal_msp.o .text 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o .data 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o .bss 0x0000000000000000 0x0 ./src/stm32f1xx_hal_msp.o + .text.HAL_SPI_MspDeInit + 0x0000000000000000 0x2c ./src/stm32f1xx_hal_msp.o + .text.HAL_TIM_Base_MspDeInit + 0x0000000000000000 0xa8 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x886 ./src/stm32f1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x16 ./src/stm32f1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x180 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0xca ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x18c ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x2e ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x22 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x34e ./src/stm32f1xx_hal_msp.o @@ -2349,6 +2965,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x250 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0x143 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1f4 ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x83e ./src/stm32f1xx_hal_msp.o + .debug_macro 0x0000000000000000 0x11 ./src/stm32f1xx_hal_msp.o .debug_macro 0x0000000000000000 0xae ./src/stm32f1xx_hal_msp.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o @@ -2401,12 +3020,15 @@ Discarded input sections .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o + .group 0x0000000000000000 0x8 ./src/stm32f1xx_it.o .text 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .data 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .bss 0x0000000000000000 0x0 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x886 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000000000 0x16 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000000000 0x180 ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0xca ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x18c ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x2e ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x22 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x34e ./src/stm32f1xx_it.o @@ -2454,6 +3076,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x250 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0x143 ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x1f4 ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x83e ./src/stm32f1xx_it.o + .debug_macro 0x0000000000000000 0x11 ./src/stm32f1xx_it.o .debug_macro 0x0000000000000000 0xae ./src/stm32f1xx_it.o .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o @@ -2507,12 +3132,15 @@ Discarded input sections .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/led.o + .group 0x0000000000000000 0x8 ./my_src/led.o + .group 0x0000000000000000 0x8 ./my_src/led.o + .group 0x0000000000000000 0x8 ./my_src/led.o .text 0x0000000000000000 0x0 ./my_src/led.o .data 0x0000000000000000 0x0 ./my_src/led.o .bss 0x0000000000000000 0x0 ./my_src/led.o .debug_macro 0x0000000000000000 0x886 ./my_src/led.o - .debug_macro 0x0000000000000000 0x16 ./my_src/led.o - .debug_macro 0x0000000000000000 0x180 ./my_src/led.o + .debug_macro 0x0000000000000000 0xca ./my_src/led.o + .debug_macro 0x0000000000000000 0x18c ./my_src/led.o .debug_macro 0x0000000000000000 0x2e ./my_src/led.o .debug_macro 0x0000000000000000 0x22 ./my_src/led.o .debug_macro 0x0000000000000000 0x34e ./my_src/led.o @@ -2560,6 +3188,9 @@ Discarded input sections .debug_macro 0x0000000000000000 0x8c ./my_src/led.o .debug_macro 0x0000000000000000 0x250 ./my_src/led.o .debug_macro 0x0000000000000000 0x143 ./my_src/led.o + .debug_macro 0x0000000000000000 0x1f4 ./my_src/led.o + .debug_macro 0x0000000000000000 0x83e ./my_src/led.o + .debug_macro 0x0000000000000000 0x11 ./my_src/led.o .debug_macro 0x0000000000000000 0xae ./my_src/led.o .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o @@ -2616,6 +3247,9 @@ Discarded input sections .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o .group 0x0000000000000000 0x8 ./my_src/main2.o + .group 0x0000000000000000 0x8 ./my_src/main2.o + .group 0x0000000000000000 0x8 ./my_src/main2.o + .group 0x0000000000000000 0x8 ./my_src/main2.o .text 0x0000000000000000 0x0 ./my_src/main2.o .data 0x0000000000000000 0x0 ./my_src/main2.o .bss 0x0000000000000000 0x0 ./my_src/main2.o @@ -2638,8 +3272,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x16 ./my_src/main2.o .debug_macro 0x0000000000000000 0x29 ./my_src/main2.o .debug_macro 0x0000000000000000 0x34e ./my_src/main2.o - .debug_macro 0x0000000000000000 0x16 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.text.SetPageAddress + 0x0000000000000000 0x1c ./my_src/oled.o + .text.SetStartLine + 0x0000000000000000 0xc ./my_src/oled.o + .text.SetContrastControl + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Charge_Pump + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Segment_Remap + 0x0000000000000000 0xc ./my_src/oled.o + .text.Set_Entire_Display + 0x0000000000000000 0xc ./my_src/oled.o + .text.Set_Inverse_Display + 0x0000000000000000 0xc ./my_src/oled.o + .text.Set_Multiplex_Ratio + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Display_On_Off + 0x0000000000000000 0xc ./my_src/oled.o + .text.SetStartPage + 0x0000000000000000 0xc ./my_src/oled.o + .text.Set_Common_Remap + 0x0000000000000000 0xc ./my_src/oled.o + .text.Set_Display_Offset + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Display_Clock + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Precharge_Period + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_Common_Config + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_VCOMH + 0x0000000000000000 0x14 ./my_src/oled.o + .text.Set_NOP 0x0000000000000000 0xc ./my_src/oled.o + .text.oledInit + 0x0000000000000000 0x84 ./my_src/oled.o + .text.LED_P6x8Char + 0x0000000000000000 0x38 ./my_src/oled.o + .text.LED_P6x8Str + 0x0000000000000000 0x5c ./my_src/oled.o + .text.LED_PrintBMP + 0x0000000000000000 0x48 ./my_src/oled.o + .text.LED_Cursor + 0x0000000000000000 0x54 ./my_src/oled.o + .rodata.F6x8 0x0000000000000000 0x228 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x886 ./my_src/oled.o + .debug_macro 0x0000000000000000 0xca ./my_src/oled.o + .debug_macro 0x0000000000000000 0x18c ./my_src/oled.o + .debug_macro 0x0000000000000000 0x2e ./my_src/oled.o + .debug_macro 0x0000000000000000 0x22 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x34e ./my_src/oled.o + .debug_macro 0x0000000000000000 0x34 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x34 ./my_src/oled.o + .debug_macro 0x0000000000000000 0xb8e ./my_src/oled.o + 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.debug_macro 0x0000000000000000 0x3c ./my_src/oled.o + .debug_macro 0x0000000000000000 0x57 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x8c ./my_src/oled.o + .debug_macro 0x0000000000000000 0x250 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x143 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x1f4 ./my_src/oled.o + .debug_macro 0x0000000000000000 0x83e ./my_src/oled.o + .debug_macro 0x0000000000000000 0x11 ./my_src/oled.o + .debug_macro 0x0000000000000000 0xae ./my_src/oled.o .group 0x0000000000000000 0x8 ./hottislib/PontCoopScheduler.o .group 0x0000000000000000 0x8 ./hottislib/PontCoopScheduler.o .group 0x0000000000000000 0x8 ./hottislib/PontCoopScheduler.o @@ -2784,6 +3589,8 @@ LOAD ./system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o +LOAD ./system/src/stm32f1xx/stm32f1xx_hal_spi.o +LOAD ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_tim.o LOAD ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o LOAD ./system/src/newlib/_cxx.o @@ -2804,6 +3611,7 @@ LOAD ./src/stm32f1xx_hal_msp.o LOAD ./src/stm32f1xx_it.o LOAD ./my_src/led.o LOAD ./my_src/main2.o +LOAD ./my_src/oled.o LOAD ./hottislib/PontCoopScheduler.o LOAD /usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/lib/armv7-m/libstdc++_nano.a LOAD /usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/lib/armv7-m/libm.a @@ -2823,7 +3631,7 @@ END GROUP 0x000000002000bc00 __Main_Stack_Limit = (__stack - __Main_Stack_Size) [!provide] PROVIDE (_Main_Stack_Limit, __Main_Stack_Limit) 0x0000000000000100 _Minimum_Stack_Size = 0x100 - 0x0000000020000164 PROVIDE (_Heap_Begin, _end_noinit) + 0x00000000200002ec PROVIDE (_Heap_Begin, _end_noinit) 0x000000002000bc00 PROVIDE (_Heap_Limit, (__stack - __Main_Stack_Size)) .isr_vector 0x0000000008000000 0x36c @@ -2847,16 +3655,16 @@ END GROUP .inits 0x000000000800036c 0x28 0x000000000800036c __data_regions_array_start = . - 0x000000000800036c 0x4 LONG 0x800181c LOADADDR (.data) + 0x000000000800036c 0x4 LONG 0x8003b10 LOADADDR (.data) 0x0000000008000370 0x4 LONG 0x20000000 ADDR (.data) 0x0000000008000374 0x4 LONG 0x20000014 (ADDR (.data) + SIZEOF (.data)) - 0x0000000008000378 0x4 LONG 0x800181c LOADADDR (.data_CCMRAM) + 0x0000000008000378 0x4 LONG 0x8003b10 LOADADDR (.data_CCMRAM) 0x000000000800037c 0x4 LONG 0x0 ADDR (.data_CCMRAM) 0x0000000008000380 0x4 LONG 0x0 (ADDR (.data_CCMRAM) + SIZEOF (.data_CCMRAM)) 0x0000000008000384 __data_regions_array_end = . 0x0000000008000384 __bss_regions_array_start = . 0x0000000008000384 0x4 LONG 0x20000014 ADDR (.bss) - 0x0000000008000388 0x4 LONG 0x20000164 (ADDR (.bss) + SIZEOF (.bss)) + 0x0000000008000388 0x4 LONG 0x200002ec (ADDR (.bss) + SIZEOF (.bss)) 0x000000000800038c 0x4 LONG 0x0 ADDR (.bss_CCMRAM) 0x0000000008000390 0x4 LONG 0x0 (ADDR (.bss_CCMRAM) + SIZEOF (.bss_CCMRAM)) 0x0000000008000394 __bss_regions_array_end = . @@ -2882,7 +3690,7 @@ END GROUP .flashtext *(.flashtext .flashtext.*) -.text 0x0000000008000394 0x1488 +.text 0x0000000008000394 0x377c *(.text .text.*) .text.HAL_InitTick 0x0000000008000394 0x28 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -2935,210 +3743,316 @@ END GROUP .text.HAL_RCC_GetHCLKFreq 0x0000000008001324 0xc ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o 0x0000000008001324 HAL_RCC_GetHCLKFreq - .text._exit 0x0000000008001330 0x4 ./system/src/newlib/_exit.o - 0x0000000008001330 _exit + .text.SPI_WaitOnFlagUntilTimeout + 0x0000000008001330 0xe4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .text.HAL_SPI_Transmit + 0x0000000008001414 0x1d4 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + 0x0000000008001414 HAL_SPI_Transmit + .text.HAL_SPI_Init + 0x00000000080015e8 0x190 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x00000000080015e8 HAL_SPI_Init + .text.TIM_TI1_ConfigInputStage + 0x0000000008001778 0x24 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_TI2_ConfigInputStage + 0x000000000800179c 0x28 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_ITRx_SetConfig + 0x00000000080017c4 0x10 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_ETR_SetConfig + 0x00000000080017d4 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_OC1_SetConfig + 0x00000000080017ec 0xb4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_OC3_SetConfig + 0x00000000080018a0 0xb8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x0000000008001958 0x70 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.TIM_SlaveTimer_SetConfig + 0x00000000080019c8 0x328 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .text.HAL_TIM_PWM_MspInit + 0x0000000008001cf0 0x4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x0000000008001cf0 HAL_TIM_PWM_MspInit + .text.HAL_TIM_ConfigClockSource + 0x0000000008001cf4 0x4d0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x0000000008001cf4 HAL_TIM_ConfigClockSource + .text.HAL_TIM_SlaveConfigSynchronization + 0x00000000080021c4 0xd0 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x00000000080021c4 HAL_TIM_SlaveConfigSynchronization + .text.TIM_Base_SetConfig + 0x0000000008002294 0x90 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x0000000008002294 TIM_Base_SetConfig + .text.HAL_TIM_Base_Init + 0x0000000008002324 0xbc ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x0000000008002324 HAL_TIM_Base_Init + .text.HAL_TIM_PWM_Init + 0x00000000080023e0 0xc4 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x00000000080023e0 HAL_TIM_PWM_Init + .text.TIM_OC2_SetConfig + 0x00000000080024a4 0xb8 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x00000000080024a4 TIM_OC2_SetConfig + .text.HAL_TIM_PWM_ConfigChannel + 0x000000000800255c 0x234 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x000000000800255c HAL_TIM_PWM_ConfigChannel + .text.HAL_TIMEx_ConfigBreakDeadTime + 0x0000000008002790 0x100 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + 0x0000000008002790 HAL_TIMEx_ConfigBreakDeadTime + .text.HAL_TIMEx_MasterConfigSynchronization + 0x0000000008002890 0xe0 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + 0x0000000008002890 HAL_TIMEx_MasterConfigSynchronization + .text._exit 0x0000000008002970 0x4 ./system/src/newlib/_exit.o + 0x0000000008002970 _exit .text.__initialize_args - 0x0000000008001334 0x10 ./system/src/newlib/_syscalls.o - 0x0000000008001334 __initialize_args + 0x0000000008002974 0x10 ./system/src/newlib/_syscalls.o + 0x0000000008002974 __initialize_args .text.__initialize_hardware_early - 0x0000000008001344 0x18 ./system/src/cortexm/_initialize_hardware.o - 0x0000000008001344 __initialize_hardware_early + 0x0000000008002984 0x18 ./system/src/cortexm/_initialize_hardware.o + 0x0000000008002984 __initialize_hardware_early .text.__initialize_hardware - 0x000000000800135c 0x8 ./system/src/cortexm/_initialize_hardware.o - 0x000000000800135c __initialize_hardware + 0x000000000800299c 0x8 ./system/src/cortexm/_initialize_hardware.o + 0x000000000800299c __initialize_hardware .text.Default_Handler - 0x0000000008001364 0x2 ./system/src/cmsis/startup_stm32f103xe.o - 0x0000000008001364 RTC_Alarm_IRQHandler - 0x0000000008001364 EXTI2_IRQHandler - 0x0000000008001364 TIM8_TRG_COM_IRQHandler - 0x0000000008001364 TIM8_CC_IRQHandler - 0x0000000008001364 TIM1_CC_IRQHandler - 0x0000000008001364 TIM6_IRQHandler - 0x0000000008001364 PVD_IRQHandler - 0x0000000008001364 SDIO_IRQHandler - 0x0000000008001364 EXTI3_IRQHandler - 0x0000000008001364 EXTI0_IRQHandler - 0x0000000008001364 I2C2_EV_IRQHandler - 0x0000000008001364 ADC1_2_IRQHandler - 0x0000000008001364 SPI1_IRQHandler - 0x0000000008001364 TAMPER_IRQHandler - 0x0000000008001364 TIM8_UP_IRQHandler - 0x0000000008001364 DMA2_Channel2_IRQHandler - 0x0000000008001364 DMA1_Channel4_IRQHandler - 0x0000000008001364 USART3_IRQHandler - 0x0000000008001364 RTC_IRQHandler - 0x0000000008001364 DMA1_Channel7_IRQHandler - 0x0000000008001364 CAN1_RX1_IRQHandler - 0x0000000008001364 UART5_IRQHandler - 0x0000000008001364 ADC3_IRQHandler - 0x0000000008001364 TIM4_IRQHandler - 0x0000000008001364 DMA2_Channel1_IRQHandler - 0x0000000008001364 I2C1_EV_IRQHandler - 0x0000000008001364 DMA1_Channel6_IRQHandler - 0x0000000008001364 UART4_IRQHandler - 0x0000000008001364 TIM3_IRQHandler - 0x0000000008001364 RCC_IRQHandler - 0x0000000008001364 TIM1_TRG_COM_IRQHandler - 0x0000000008001364 DMA1_Channel1_IRQHandler - 0x0000000008001364 Default_Handler - 0x0000000008001364 EXTI15_10_IRQHandler - 0x0000000008001364 TIM7_IRQHandler - 0x0000000008001364 TIM5_IRQHandler - 0x0000000008001364 EXTI9_5_IRQHandler - 0x0000000008001364 SPI2_IRQHandler - 0x0000000008001364 DMA1_Channel5_IRQHandler - 0x0000000008001364 EXTI4_IRQHandler - 0x0000000008001364 USB_LP_CAN1_RX0_IRQHandler - 0x0000000008001364 USB_HP_CAN1_TX_IRQHandler - 0x0000000008001364 DMA1_Channel3_IRQHandler - 0x0000000008001364 FSMC_IRQHandler - 0x0000000008001364 TIM1_UP_IRQHandler - 0x0000000008001364 WWDG_IRQHandler - 0x0000000008001364 TIM2_IRQHandler - 0x0000000008001364 TIM1_BRK_IRQHandler - 0x0000000008001364 EXTI1_IRQHandler - 0x0000000008001364 DMA2_Channel4_5_IRQHandler - 0x0000000008001364 USART2_IRQHandler - 0x0000000008001364 I2C2_ER_IRQHandler - 0x0000000008001364 DMA1_Channel2_IRQHandler - 0x0000000008001364 TIM8_BRK_IRQHandler - 0x0000000008001364 CAN1_SCE_IRQHandler - 0x0000000008001364 FLASH_IRQHandler - 0x0000000008001364 USART1_IRQHandler - 0x0000000008001364 SPI3_IRQHandler - 0x0000000008001364 I2C1_ER_IRQHandler - 0x0000000008001364 USBWakeUp_IRQHandler - 0x0000000008001364 DMA2_Channel3_IRQHandler - *fill* 0x0000000008001366 0x2 + 0x00000000080029a4 0x2 ./system/src/cmsis/startup_stm32f103xe.o + 0x00000000080029a4 RTC_Alarm_IRQHandler + 0x00000000080029a4 EXTI2_IRQHandler + 0x00000000080029a4 TIM8_TRG_COM_IRQHandler + 0x00000000080029a4 TIM8_CC_IRQHandler + 0x00000000080029a4 TIM1_CC_IRQHandler + 0x00000000080029a4 TIM6_IRQHandler + 0x00000000080029a4 PVD_IRQHandler + 0x00000000080029a4 SDIO_IRQHandler + 0x00000000080029a4 EXTI3_IRQHandler + 0x00000000080029a4 EXTI0_IRQHandler + 0x00000000080029a4 I2C2_EV_IRQHandler + 0x00000000080029a4 ADC1_2_IRQHandler + 0x00000000080029a4 SPI1_IRQHandler + 0x00000000080029a4 TAMPER_IRQHandler + 0x00000000080029a4 TIM8_UP_IRQHandler + 0x00000000080029a4 DMA2_Channel2_IRQHandler + 0x00000000080029a4 DMA1_Channel4_IRQHandler + 0x00000000080029a4 USART3_IRQHandler + 0x00000000080029a4 RTC_IRQHandler + 0x00000000080029a4 DMA1_Channel7_IRQHandler + 0x00000000080029a4 CAN1_RX1_IRQHandler + 0x00000000080029a4 UART5_IRQHandler + 0x00000000080029a4 ADC3_IRQHandler + 0x00000000080029a4 TIM4_IRQHandler + 0x00000000080029a4 DMA2_Channel1_IRQHandler + 0x00000000080029a4 I2C1_EV_IRQHandler + 0x00000000080029a4 DMA1_Channel6_IRQHandler + 0x00000000080029a4 UART4_IRQHandler + 0x00000000080029a4 TIM3_IRQHandler + 0x00000000080029a4 RCC_IRQHandler + 0x00000000080029a4 TIM1_TRG_COM_IRQHandler + 0x00000000080029a4 DMA1_Channel1_IRQHandler + 0x00000000080029a4 Default_Handler + 0x00000000080029a4 EXTI15_10_IRQHandler + 0x00000000080029a4 TIM7_IRQHandler + 0x00000000080029a4 TIM5_IRQHandler + 0x00000000080029a4 EXTI9_5_IRQHandler + 0x00000000080029a4 SPI2_IRQHandler + 0x00000000080029a4 DMA1_Channel5_IRQHandler + 0x00000000080029a4 EXTI4_IRQHandler + 0x00000000080029a4 USB_LP_CAN1_RX0_IRQHandler + 0x00000000080029a4 USB_HP_CAN1_TX_IRQHandler + 0x00000000080029a4 DMA1_Channel3_IRQHandler + 0x00000000080029a4 FSMC_IRQHandler + 0x00000000080029a4 TIM1_UP_IRQHandler + 0x00000000080029a4 WWDG_IRQHandler + 0x00000000080029a4 TIM2_IRQHandler + 0x00000000080029a4 TIM1_BRK_IRQHandler + 0x00000000080029a4 EXTI1_IRQHandler + 0x00000000080029a4 DMA2_Channel4_5_IRQHandler + 0x00000000080029a4 USART2_IRQHandler + 0x00000000080029a4 I2C2_ER_IRQHandler + 0x00000000080029a4 DMA1_Channel2_IRQHandler + 0x00000000080029a4 TIM8_BRK_IRQHandler + 0x00000000080029a4 CAN1_SCE_IRQHandler + 0x00000000080029a4 FLASH_IRQHandler + 0x00000000080029a4 USART1_IRQHandler + 0x00000000080029a4 SPI3_IRQHandler + 0x00000000080029a4 I2C1_ER_IRQHandler + 0x00000000080029a4 USBWakeUp_IRQHandler + 0x00000000080029a4 DMA2_Channel3_IRQHandler + *fill* 0x00000000080029a6 0x2 .text.SystemInit - 0x0000000008001368 0x4c ./system/src/cmsis/system_stm32f1xx.o - 0x0000000008001368 SystemInit + 0x00000000080029a8 0x4c ./system/src/cmsis/system_stm32f1xx.o + 0x00000000080029a8 SystemInit .text.SystemCoreClockUpdate - 0x00000000080013b4 0x94 ./system/src/cmsis/system_stm32f1xx.o - 0x00000000080013b4 SystemCoreClockUpdate + 0x00000000080029f4 0x94 ./system/src/cmsis/system_stm32f1xx.o + 0x00000000080029f4 SystemCoreClockUpdate .text.MX_GPIO_Init - 0x0000000008001448 0x5c ./src/main.o + 0x0000000008002a88 0xc8 ./src/main.o .text.Error_Handler - 0x00000000080014a4 0x8 ./src/main.o - 0x00000000080014a4 Error_Handler + 0x0000000008002b50 0x8 ./src/main.o + 0x0000000008002b50 Error_Handler + .text.MX_SPI1_Init + 0x0000000008002b58 0x44 ./src/main.o + .text.MX_TIM1_Init + 0x0000000008002b9c 0xdc ./src/main.o + .text.MX_TIM2_Init + 0x0000000008002c78 0x5c ./src/main.o + .text.MX_TIM3_Init + 0x0000000008002cd4 0x60 ./src/main.o + .text.MX_TIM4_Init + 0x0000000008002d34 0x60 ./src/main.o + .text.MX_TIM8_Init + 0x0000000008002d94 0x60 ./src/main.o .text.SystemClock_Config - 0x00000000080014ac 0x78 ./src/main.o - 0x00000000080014ac SystemClock_Config - .text.main 0x0000000008001524 0x1c ./src/main.o - 0x0000000008001524 main + 0x0000000008002df4 0x78 ./src/main.o + 0x0000000008002df4 SystemClock_Config + .text.main 0x0000000008002e6c 0x34 ./src/main.o + 0x0000000008002e6c main .text.assert_failed - 0x0000000008001540 0x4 ./src/main.o - 0x0000000008001540 assert_failed + 0x0000000008002ea0 0x4 ./src/main.o + 0x0000000008002ea0 assert_failed .text.HAL_MspInit - 0x0000000008001544 0x90 ./src/stm32f1xx_hal_msp.o - 0x0000000008001544 HAL_MspInit + 0x0000000008002ea4 0x90 ./src/stm32f1xx_hal_msp.o + 0x0000000008002ea4 HAL_MspInit + .text.HAL_SPI_MspInit + 0x0000000008002f34 0x58 ./src/stm32f1xx_hal_msp.o + 0x0000000008002f34 HAL_SPI_MspInit + .text.HAL_TIM_Base_MspInit + 0x0000000008002f8c 0x114 ./src/stm32f1xx_hal_msp.o + 0x0000000008002f8c HAL_TIM_Base_MspInit + .text.HAL_TIM_MspPostInit + 0x00000000080030a0 0x40 ./src/stm32f1xx_hal_msp.o + 0x00000000080030a0 HAL_TIM_MspPostInit .text.NMI_Handler - 0x00000000080015d4 0x4 ./src/stm32f1xx_it.o - 0x00000000080015d4 NMI_Handler + 0x00000000080030e0 0x4 ./src/stm32f1xx_it.o + 0x00000000080030e0 NMI_Handler .text.HardFault_Handler - 0x00000000080015d8 0x4 ./src/stm32f1xx_it.o - 0x00000000080015d8 HardFault_Handler + 0x00000000080030e4 0x4 ./src/stm32f1xx_it.o + 0x00000000080030e4 HardFault_Handler .text.MemManage_Handler - 0x00000000080015dc 0x4 ./src/stm32f1xx_it.o - 0x00000000080015dc MemManage_Handler + 0x00000000080030e8 0x4 ./src/stm32f1xx_it.o + 0x00000000080030e8 MemManage_Handler .text.BusFault_Handler - 0x00000000080015e0 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e0 BusFault_Handler + 0x00000000080030ec 0x4 ./src/stm32f1xx_it.o + 0x00000000080030ec BusFault_Handler .text.UsageFault_Handler - 0x00000000080015e4 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e4 UsageFault_Handler + 0x00000000080030f0 0x4 ./src/stm32f1xx_it.o + 0x00000000080030f0 UsageFault_Handler .text.SVC_Handler - 0x00000000080015e8 0x4 ./src/stm32f1xx_it.o - 0x00000000080015e8 SVC_Handler + 0x00000000080030f4 0x4 ./src/stm32f1xx_it.o + 0x00000000080030f4 SVC_Handler .text.DebugMon_Handler - 0x00000000080015ec 0x4 ./src/stm32f1xx_it.o - 0x00000000080015ec DebugMon_Handler + 0x00000000080030f8 0x4 ./src/stm32f1xx_it.o + 0x00000000080030f8 DebugMon_Handler .text.PendSV_Handler - 0x00000000080015f0 0x4 ./src/stm32f1xx_it.o - 0x00000000080015f0 PendSV_Handler + 0x00000000080030fc 0x4 ./src/stm32f1xx_it.o + 0x00000000080030fc PendSV_Handler .text.SysTick_Handler - 0x00000000080015f4 0xc ./src/stm32f1xx_it.o - 0x00000000080015f4 SysTick_Handler - .text.blink 0x0000000008001600 0x14 ./my_src/led.o - 0x0000000008001600 blink + 0x0000000008003100 0xc ./src/stm32f1xx_it.o + 0x0000000008003100 SysTick_Handler + .text.blink 0x000000000800310c 0x14 ./my_src/led.o + 0x000000000800310c blink .text.blinkInit - 0x0000000008001614 0x18 ./my_src/led.o - 0x0000000008001614 blinkInit + 0x0000000008003120 0x18 ./my_src/led.o + 0x0000000008003120 blinkInit .text.my_setup_1 - 0x000000000800162c 0x8 ./my_src/main2.o - 0x000000000800162c my_setup_1 - .text.my_loop 0x0000000008001634 0x8 ./my_src/main2.o - 0x0000000008001634 my_loop + 0x0000000008003138 0x8 ./my_src/main2.o + 0x0000000008003138 my_setup_1 + .text.my_loop 0x0000000008003140 0x8 ./my_src/main2.o + 0x0000000008003140 my_loop .text.HAL_SYSTICK_Callback - 0x000000000800163c 0x8 ./my_src/main2.o - 0x000000000800163c HAL_SYSTICK_Callback + 0x0000000008003148 0x8 ./my_src/main2.o + 0x0000000008003148 HAL_SYSTICK_Callback .text.my_errorHandler - 0x0000000008001644 0x4 ./my_src/main2.o - 0x0000000008001644 my_errorHandler + 0x0000000008003150 0x4 ./my_src/main2.o + 0x0000000008003150 my_errorHandler .text.my_setup_2 - 0x0000000008001648 0x8 ./my_src/main2.o - 0x0000000008001648 my_setup_2 - .text.schInit 0x0000000008001650 0x30 ./hottislib/PontCoopScheduler.o - 0x0000000008001650 schInit - .text.schAdd 0x0000000008001680 0x40 ./hottislib/PontCoopScheduler.o - 0x0000000008001680 schAdd - .text.schExec 0x00000000080016c0 0x58 ./hottislib/PontCoopScheduler.o - 0x00000000080016c0 schExec + 0x0000000008003154 0x18 ./my_src/main2.o + 0x0000000008003154 my_setup_2 + .text.__LEDPIN_DC + 0x000000000800316c 0x14 ./my_src/oled.o + .text.__LEDPIN_CS + 0x0000000008003180 0x14 ./my_src/oled.o + .text.LED_WrDat + 0x0000000008003194 0x30 ./my_src/oled.o + 0x0000000008003194 LED_WrDat + .text.LED_WrCmd + 0x00000000080031c4 0x30 ./my_src/oled.o + 0x00000000080031c4 LED_WrCmd + .text.LED_Set_Pos + 0x00000000080031f4 0x20 ./my_src/oled.o + 0x00000000080031f4 LED_Set_Pos + .text.LED_P8x16Str + 0x0000000008003214 0x80 ./my_src/oled.o + 0x0000000008003214 LED_P8x16Str + .text.schInit 0x0000000008003294 0x30 ./hottislib/PontCoopScheduler.o + 0x0000000008003294 schInit + .text.schAdd 0x00000000080032c4 0x40 ./hottislib/PontCoopScheduler.o + 0x00000000080032c4 schAdd + .text.schExec 0x0000000008003304 0x58 ./hottislib/PontCoopScheduler.o + 0x0000000008003304 schExec .text.schUpdate - 0x0000000008001718 0x54 ./hottislib/PontCoopScheduler.o - 0x0000000008001718 schUpdate + 0x000000000800335c 0x54 ./hottislib/PontCoopScheduler.o + 0x000000000800335c schUpdate *(.rodata .rodata.* .constdata .constdata.*) .rodata.str1.4 - 0x000000000800176c 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - *fill* 0x000000000800179b 0x1 + 0x00000000080033b0 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + *fill* 0x00000000080033df 0x1 .rodata.str1.4 - 0x000000000800179c 0x2d ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - *fill* 0x00000000080017c9 0x3 - .rodata 0x00000000080017cc 0x12 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - *fill* 0x00000000080017de 0x2 + 0x00000000080033e0 0x2d ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + *fill* 0x000000000800340d 0x3 + .rodata 0x0000000008003410 0x12 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + *fill* 0x0000000008003422 0x2 .rodata.str1.4 - 0x00000000080017e0 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + 0x0000000008003424 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .rodata.str1.4 + 0x0000000008003450 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .rodata.str1.4 + 0x000000000800347c 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + *fill* 0x00000000080034ab 0x1 + .rodata.str1.4 + 0x00000000080034ac 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .rodata.str1.4 + 0x00000000080034d8 0x2f ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + *fill* 0x0000000008003507 0x1 .rodata.AHBPrescTable - 0x000000000800180c 0x10 ./system/src/cmsis/system_stm32f1xx.o - 0x000000000800180c AHBPrescTable + 0x0000000008003508 0x10 ./system/src/cmsis/system_stm32f1xx.o + 0x0000000008003508 AHBPrescTable + .rodata.str1.4 + 0x0000000008003518 0x8 ./my_src/main2.o + 0x6 (size before relaxing) + .rodata.F8X16 0x0000000008003520 0x5f0 ./my_src/oled.o + 0x0000000008003520 F8X16 *(vtable) *(.eh_frame*) *(.glue_7) - .glue_7 0x000000000800181c 0x0 linker stubs + .glue_7 0x0000000008003b10 0x0 linker stubs *(.glue_7t) - .glue_7t 0x000000000800181c 0x0 linker stubs + .glue_7t 0x0000000008003b10 0x0 linker stubs -.vfp11_veneer 0x000000000800181c 0x0 - .vfp11_veneer 0x000000000800181c 0x0 linker stubs +.vfp11_veneer 0x0000000008003b10 0x0 + .vfp11_veneer 0x0000000008003b10 0x0 linker stubs -.v4_bx 0x000000000800181c 0x0 - .v4_bx 0x000000000800181c 0x0 linker stubs +.v4_bx 0x0000000008003b10 0x0 + .v4_bx 0x0000000008003b10 0x0 linker stubs -.iplt 0x000000000800181c 0x0 - .iplt 0x000000000800181c 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o +.iplt 0x0000000008003b10 0x0 + .iplt 0x0000000008003b10 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o -.rel.dyn 0x000000000800181c 0x0 - .rel.iplt 0x000000000800181c 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o +.rel.dyn 0x0000000008003b10 0x0 + .rel.iplt 0x0000000008003b10 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .ARM.extab *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x000000000800181c . = ALIGN (0x4) - 0x000000000800181c __exidx_start = . + 0x0000000008003b10 . = ALIGN (0x4) + 0x0000000008003b10 __exidx_start = . .ARM.exidx *(.ARM.exidx* .gnu.linkonce.armexidx.*) - 0x000000000800181c __exidx_end = . - 0x000000000800181c . = ALIGN (0x4) - 0x000000000800181c _etext = . - 0x000000000800181c __etext = . + 0x0000000008003b10 __exidx_end = . + 0x0000000008003b10 . = ALIGN (0x4) + 0x0000000008003b10 _etext = . + 0x0000000008003b10 __etext = . -.data_CCMRAM 0x0000000000000000 0x0 load address 0x000000000800181c +.data_CCMRAM 0x0000000000000000 0x0 load address 0x0000000008003b10 FILL mask 0xff *(.data.CCMRAM .data.CCMRAM.*) 0x0000000000000000 . = ALIGN (0x4) - 0x000000000800181c _sidata = LOADADDR (.data) + 0x0000000008003b10 _sidata = LOADADDR (.data) -.data 0x0000000020000000 0x14 load address 0x000000000800181c +.data 0x0000000020000000 0x14 load address 0x0000000008003b10 FILL mask 0xff 0x0000000020000000 _sdata = . 0x0000000020000000 __data_start__ = . @@ -3156,47 +4070,58 @@ END GROUP 0x0000000020000014 _edata = . 0x0000000020000014 __data_end__ = . -.igot.plt 0x0000000020000014 0x0 load address 0x0000000008001830 +.igot.plt 0x0000000020000014 0x0 load address 0x0000000008003b24 .igot.plt 0x0000000020000014 0x0 ./system/src/stm32f1xx/stm32f1xx_hal.o .bss_CCMRAM 0x0000000000000000 0x0 *(.bss.CCMRAM .bss.CCMRAM.*) -.bss 0x0000000020000014 0x150 +.bss 0x0000000020000014 0x2d8 0x0000000020000014 __bss_start__ = . 0x0000000020000014 _sbss = . *(.bss_begin .bss_begin.*) .bss_begin 0x0000000020000014 0x4 ./system/src/newlib/_startup.o *(.bss .bss.*) .bss.uwTick 0x0000000020000018 0x4 ./system/src/stm32f1xx/stm32f1xx_hal.o - .bss.name.4281 - 0x000000002000001c 0x1 ./system/src/newlib/_syscalls.o - *(COMMON) + .bss.uCRCErrorWorkaroundCheck + 0x000000002000001c 0x1 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x000000002000001c uCRCErrorWorkaroundCheck *fill* 0x000000002000001d 0x3 - COMMON 0x0000000020000020 0x140 ./hottislib/PontCoopScheduler.o - 0x0000000020000020 tasks + .bss.name.4281 + 0x0000000020000020 0x1 ./system/src/newlib/_syscalls.o + *(COMMON) + *fill* 0x0000000020000021 0x3 + COMMON 0x0000000020000024 0x184 ./src/main.o + 0x0000000020000024 htim8 + 0x0000000020000060 htim4 + 0x000000002000009c htim3 + 0x00000000200000d8 htim1 + 0x0000000020000114 hspi1 + 0x000000002000016c htim2 + COMMON 0x00000000200001a8 0x140 ./hottislib/PontCoopScheduler.o + 0x00000000200001a8 tasks *(.bss_end .bss_end.*) - .bss_end 0x0000000020000160 0x4 ./system/src/newlib/_startup.o - 0x0000000020000164 . = ALIGN (0x4) - 0x0000000020000164 __bss_end__ = . - 0x0000000020000164 _ebss = . + .bss_end 0x00000000200002e8 0x4 ./system/src/newlib/_startup.o + 0x00000000200002ec . = ALIGN (0x4) + 0x00000000200002ec __bss_end__ = . + 0x00000000200002ec _ebss = . .noinit_CCMRAM *(.noinit.CCMRAM .noinit.CCMRAM.*) -.noinit 0x0000000020000164 0x0 - 0x0000000020000164 _noinit = . +.noinit 0x00000000200002ec 0x0 + 0x00000000200002ec _noinit = . *(.noinit .noinit.*) - 0x0000000020000164 . = ALIGN (0x4) - 0x0000000020000164 _end_noinit = . + 0x00000000200002ec . = ALIGN (0x4) + 0x00000000200002ec _end_noinit = . [!provide] PROVIDE (end, _end_noinit) [!provide] PROVIDE (_end, _end_noinit) [!provide] PROVIDE (__end, _end_noinit) [!provide] PROVIDE (__end__, _end_noinit) -._check_stack 0x0000000020000164 0x100 - 0x0000000020000264 . = (. + _Minimum_Stack_Size) - *fill* 0x0000000020000164 0x100 +._check_stack 0x00000000200002ec 0x100 + 0x00000000200003ec . = (. + _Minimum_Stack_Size) + *fill* 0x00000000200002ec 0x100 .b1text *(.b1text) @@ -3248,6 +4173,10 @@ END GROUP .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .comment 0x000000000000002b 0x2c ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_exit.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_startup.o .comment 0x000000000000002b 0x2c ./system/src/newlib/_syscalls.o @@ -3259,6 +4188,7 @@ END GROUP .comment 0x000000000000002b 0x2c ./src/stm32f1xx_it.o .comment 0x000000000000002b 0x2c ./my_src/led.o .comment 0x000000000000002b 0x2c ./my_src/main2.o + .comment 0x000000000000002b 0x2c ./my_src/oled.o .comment 0x000000000000002b 0x2c ./hottislib/PontCoopScheduler.o .ARM.attributes @@ -3272,31 +4202,41 @@ END GROUP .ARM.attributes 0x0000000000000099 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .ARM.attributes - 0x00000000000000cc 0x33 ./system/src/newlib/_exit.o + 0x00000000000000cc 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o .ARM.attributes - 0x00000000000000ff 0x33 ./system/src/newlib/_startup.o + 0x00000000000000ff 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o .ARM.attributes - 0x0000000000000132 0x33 ./system/src/newlib/_syscalls.o + 0x0000000000000132 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .ARM.attributes - 0x0000000000000165 0x33 ./system/src/cortexm/_initialize_hardware.o + 0x0000000000000165 0x33 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .ARM.attributes - 0x0000000000000198 0x33 ./system/src/cortexm/exception_handlers.o + 0x0000000000000198 0x33 ./system/src/newlib/_exit.o .ARM.attributes - 0x00000000000001cb 0x21 ./system/src/cmsis/startup_stm32f103xe.o + 0x00000000000001cb 0x33 ./system/src/newlib/_startup.o .ARM.attributes - 0x00000000000001ec 0x33 ./system/src/cmsis/system_stm32f1xx.o + 0x00000000000001fe 0x33 ./system/src/newlib/_syscalls.o .ARM.attributes - 0x000000000000021f 0x33 ./src/main.o + 0x0000000000000231 0x33 ./system/src/cortexm/_initialize_hardware.o .ARM.attributes - 0x0000000000000252 0x33 ./src/stm32f1xx_hal_msp.o + 0x0000000000000264 0x33 ./system/src/cortexm/exception_handlers.o .ARM.attributes - 0x0000000000000285 0x33 ./src/stm32f1xx_it.o + 0x0000000000000297 0x21 ./system/src/cmsis/startup_stm32f103xe.o .ARM.attributes - 0x00000000000002b8 0x33 ./my_src/led.o + 0x00000000000002b8 0x33 ./system/src/cmsis/system_stm32f1xx.o .ARM.attributes - 0x00000000000002eb 0x33 ./my_src/main2.o + 0x00000000000002eb 0x33 ./src/main.o .ARM.attributes - 0x000000000000031e 0x33 ./hottislib/PontCoopScheduler.o + 0x000000000000031e 0x33 ./src/stm32f1xx_hal_msp.o + .ARM.attributes + 0x0000000000000351 0x33 ./src/stm32f1xx_it.o + .ARM.attributes + 0x0000000000000384 0x33 ./my_src/led.o + .ARM.attributes + 0x00000000000003b7 0x33 ./my_src/main2.o + .ARM.attributes + 0x00000000000003ea 0x33 ./my_src/oled.o + .ARM.attributes + 0x000000000000041d 0x33 ./hottislib/PontCoopScheduler.o .debug *(.debug) @@ -3310,7 +4250,7 @@ END GROUP .debug_sfnames *(.debug_sfnames) -.debug_aranges 0x0000000000000000 0x518 +.debug_aranges 0x0000000000000000 0xcc0 *(.debug_aranges) .debug_aranges 0x0000000000000000 0xb0 ./system/src/stm32f1xx/stm32f1xx_hal.o @@ -3321,160 +4261,206 @@ END GROUP .debug_aranges 0x0000000000000198 0x88 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o .debug_aranges - 0x0000000000000220 0x28 ./system/src/newlib/_exit.o + 0x0000000000000220 0x158 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o .debug_aranges - 0x0000000000000248 0x40 ./system/src/newlib/_startup.o + 0x0000000000000378 0x28 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o .debug_aranges - 0x0000000000000288 0x30 ./system/src/newlib/_syscalls.o + 0x00000000000003a0 0x368 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o .debug_aranges - 0x00000000000002b8 0x28 ./system/src/cortexm/_initialize_hardware.o + 0x0000000000000708 0x138 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o .debug_aranges - 0x00000000000002e0 0x80 ./system/src/cortexm/exception_handlers.o + 0x0000000000000840 0x28 ./system/src/newlib/_exit.o .debug_aranges - 0x0000000000000360 0x28 ./system/src/cmsis/startup_stm32f103xe.o + 0x0000000000000868 0x40 ./system/src/newlib/_startup.o .debug_aranges - 0x0000000000000388 0x28 ./system/src/cmsis/system_stm32f1xx.o + 0x00000000000008a8 0x30 ./system/src/newlib/_syscalls.o .debug_aranges - 0x00000000000003b0 0x40 ./src/main.o + 0x00000000000008d8 0x28 ./system/src/cortexm/_initialize_hardware.o .debug_aranges - 0x00000000000003f0 0x20 ./src/stm32f1xx_hal_msp.o + 0x0000000000000900 0x80 ./system/src/cortexm/exception_handlers.o .debug_aranges - 0x0000000000000410 0x60 ./src/stm32f1xx_it.o + 0x0000000000000980 0x28 ./system/src/cmsis/startup_stm32f103xe.o .debug_aranges - 0x0000000000000470 0x28 ./my_src/led.o + 0x00000000000009a8 0x28 ./system/src/cmsis/system_stm32f1xx.o .debug_aranges - 0x0000000000000498 0x40 ./my_src/main2.o + 0x00000000000009d0 0x70 ./src/main.o .debug_aranges - 0x00000000000004d8 0x40 ./hottislib/PontCoopScheduler.o + 0x0000000000000a40 0x48 ./src/stm32f1xx_hal_msp.o + .debug_aranges + 0x0000000000000a88 0x60 ./src/stm32f1xx_it.o + .debug_aranges + 0x0000000000000ae8 0x28 ./my_src/led.o + .debug_aranges + 0x0000000000000b10 0x40 ./my_src/main2.o + .debug_aranges + 0x0000000000000b50 0x130 ./my_src/oled.o + .debug_aranges + 0x0000000000000c80 0x40 ./hottislib/PontCoopScheduler.o .debug_pubnames *(.debug_pubnames) -.debug_info 0x0000000000000000 0x54d7 +.debug_info 0x0000000000000000 0xf9e3 *(.debug_info .gnu.linkonce.wi.*) .debug_info 0x0000000000000000 0x6e9 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_info 0x00000000000006e9 0xd53 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_info 0x000000000000143c 0x7f2 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_info 0x0000000000001c2e 0x155d ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_info 0x000000000000318b 0xee ./system/src/newlib/_exit.o - .debug_info 0x0000000000003279 0x455 ./system/src/newlib/_startup.o - .debug_info 0x00000000000036ce 0x1c7 ./system/src/newlib/_syscalls.o - .debug_info 0x0000000000003895 0x2b1 ./system/src/cortexm/_initialize_hardware.o - .debug_info 0x0000000000003b46 0x281 ./system/src/cortexm/exception_handlers.o - .debug_info 0x0000000000003dc7 0x72 ./system/src/cmsis/startup_stm32f103xe.o - .debug_info 0x0000000000003e39 0x3bc ./system/src/cmsis/system_stm32f1xx.o - .debug_info 0x00000000000041f5 0x786 ./src/main.o - .debug_info 0x000000000000497b 0x48a ./src/stm32f1xx_hal_msp.o - .debug_info 0x0000000000004e05 0x169 ./src/stm32f1xx_it.o - .debug_info 0x0000000000004f6e 0x1bf ./my_src/led.o - .debug_info 0x000000000000512d 0x15a ./my_src/main2.o - .debug_info 0x0000000000005287 0x250 ./hottislib/PontCoopScheduler.o + .debug_info 0x000000000000318b 0x1798 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_info 0x0000000000004923 0x6f6 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_info 0x0000000000005019 0x4303 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_info 0x000000000000931c 0x1775 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_info 0x000000000000aa91 0xee ./system/src/newlib/_exit.o + .debug_info 0x000000000000ab7f 0x455 ./system/src/newlib/_startup.o + .debug_info 0x000000000000afd4 0x1c7 ./system/src/newlib/_syscalls.o + .debug_info 0x000000000000b19b 0x2b1 ./system/src/cortexm/_initialize_hardware.o + .debug_info 0x000000000000b44c 0x281 ./system/src/cortexm/exception_handlers.o + .debug_info 0x000000000000b6cd 0x72 ./system/src/cmsis/startup_stm32f103xe.o + .debug_info 0x000000000000b73f 0x3bc ./system/src/cmsis/system_stm32f1xx.o + .debug_info 0x000000000000bafb 0x15ba ./src/main.o + .debug_info 0x000000000000d0b5 0xebc ./src/stm32f1xx_hal_msp.o + .debug_info 0x000000000000df71 0x169 ./src/stm32f1xx_it.o + .debug_info 0x000000000000e0da 0x1bf ./my_src/led.o + .debug_info 0x000000000000e299 0x182 ./my_src/main2.o + .debug_info 0x000000000000e41b 0x1378 ./my_src/oled.o + .debug_info 0x000000000000f793 0x250 ./hottislib/PontCoopScheduler.o -.debug_abbrev 0x0000000000000000 0x168e +.debug_abbrev 0x0000000000000000 0x21ff *(.debug_abbrev) .debug_abbrev 0x0000000000000000 0x21f ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_abbrev 0x000000000000021f 0x2d4 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_abbrev 0x00000000000004f3 0x204 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_abbrev 0x00000000000006f7 0x278 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_abbrev 0x000000000000096f 0xbd ./system/src/newlib/_exit.o - .debug_abbrev 0x0000000000000a2c 0x1ac ./system/src/newlib/_startup.o - .debug_abbrev 0x0000000000000bd8 0xec ./system/src/newlib/_syscalls.o - .debug_abbrev 0x0000000000000cc4 0xea ./system/src/cortexm/_initialize_hardware.o - .debug_abbrev 0x0000000000000dae 0x118 ./system/src/cortexm/exception_handlers.o - .debug_abbrev 0x0000000000000ec6 0x12 ./system/src/cmsis/startup_stm32f103xe.o - .debug_abbrev 0x0000000000000ed8 0x125 ./system/src/cmsis/system_stm32f1xx.o - .debug_abbrev 0x0000000000000ffd 0x1c7 ./src/main.o - .debug_abbrev 0x00000000000011c4 0x126 ./src/stm32f1xx_hal_msp.o - .debug_abbrev 0x00000000000012ea 0xbb ./src/stm32f1xx_it.o - .debug_abbrev 0x00000000000013a5 0x10b ./my_src/led.o - .debug_abbrev 0x00000000000014b0 0xb6 ./my_src/main2.o - .debug_abbrev 0x0000000000001566 0x128 ./hottislib/PontCoopScheduler.o + .debug_abbrev 0x000000000000096f 0x22a ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_abbrev 0x0000000000000b99 0x16d ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_abbrev 0x0000000000000d06 0x22a ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_abbrev 0x0000000000000f30 0x21b ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_abbrev 0x000000000000114b 0xbd ./system/src/newlib/_exit.o + .debug_abbrev 0x0000000000001208 0x1ac ./system/src/newlib/_startup.o + .debug_abbrev 0x00000000000013b4 0xec ./system/src/newlib/_syscalls.o + .debug_abbrev 0x00000000000014a0 0xea ./system/src/cortexm/_initialize_hardware.o + .debug_abbrev 0x000000000000158a 0x118 ./system/src/cortexm/exception_handlers.o + .debug_abbrev 0x00000000000016a2 0x12 ./system/src/cmsis/startup_stm32f103xe.o + .debug_abbrev 0x00000000000016b4 0x125 ./system/src/cmsis/system_stm32f1xx.o + .debug_abbrev 0x00000000000017d9 0x260 ./src/main.o + .debug_abbrev 0x0000000000001a39 0x1c7 ./src/stm32f1xx_hal_msp.o + .debug_abbrev 0x0000000000001c00 0xbb ./src/stm32f1xx_it.o + .debug_abbrev 0x0000000000001cbb 0x10b ./my_src/led.o + .debug_abbrev 0x0000000000001dc6 0xcd ./my_src/main2.o + .debug_abbrev 0x0000000000001e93 0x244 ./my_src/oled.o + .debug_abbrev 0x00000000000020d7 0x128 ./hottislib/PontCoopScheduler.o -.debug_line 0x0000000000000000 0x4875 +.debug_line 0x0000000000000000 0xa00b *(.debug_line) - .debug_line 0x0000000000000000 0x5e0 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_line 0x00000000000005e0 0x64d ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_line 0x0000000000000c2d 0x757 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_line 0x0000000000001384 0xada ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_line 0x0000000000001e5e 0x257 ./system/src/newlib/_exit.o - .debug_line 0x00000000000020b5 0x2bf ./system/src/newlib/_startup.o - .debug_line 0x0000000000002374 0x2c8 ./system/src/newlib/_syscalls.o - .debug_line 0x000000000000263c 0x173 ./system/src/cortexm/_initialize_hardware.o - .debug_line 0x00000000000027af 0x3b5 ./system/src/cortexm/exception_handlers.o - .debug_line 0x0000000000002b64 0x86 ./system/src/cmsis/startup_stm32f103xe.o - .debug_line 0x0000000000002bea 0x17b ./system/src/cmsis/system_stm32f1xx.o - .debug_line 0x0000000000002d65 0x50b ./src/main.o - .debug_line 0x0000000000003270 0x489 ./src/stm32f1xx_hal_msp.o - .debug_line 0x00000000000036f9 0x50e ./src/stm32f1xx_it.o - .debug_line 0x0000000000003c07 0x4c5 ./my_src/led.o - .debug_line 0x00000000000040cc 0x524 ./my_src/main2.o - .debug_line 0x00000000000045f0 0x285 ./hottislib/PontCoopScheduler.o + .debug_line 0x0000000000000000 0x628 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_line 0x0000000000000628 0x695 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_line 0x0000000000000cbd 0x79f ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_line 0x000000000000145c 0xb22 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_line 0x0000000000001f7e 0xdf9 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_line 0x0000000000002d77 0x5c5 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_line 0x000000000000333c 0x28c3 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_line 0x0000000000005bff 0xecc ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_line 0x0000000000006acb 0x257 ./system/src/newlib/_exit.o + .debug_line 0x0000000000006d22 0x2bf ./system/src/newlib/_startup.o + .debug_line 0x0000000000006fe1 0x2c8 ./system/src/newlib/_syscalls.o + .debug_line 0x00000000000072a9 0x173 ./system/src/cortexm/_initialize_hardware.o + .debug_line 0x000000000000741c 0x3b5 ./system/src/cortexm/exception_handlers.o + .debug_line 0x00000000000077d1 0x86 ./system/src/cmsis/startup_stm32f103xe.o + .debug_line 0x0000000000007857 0x17b ./system/src/cmsis/system_stm32f1xx.o + .debug_line 0x00000000000079d2 0x64c ./src/main.o + .debug_line 0x000000000000801e 0x566 ./src/stm32f1xx_hal_msp.o + .debug_line 0x0000000000008584 0x556 ./src/stm32f1xx_it.o + .debug_line 0x0000000000008ada 0x50d ./my_src/led.o + .debug_line 0x0000000000008fe7 0x577 ./my_src/main2.o + .debug_line 0x000000000000955e 0x828 ./my_src/oled.o + .debug_line 0x0000000000009d86 0x285 ./hottislib/PontCoopScheduler.o -.debug_frame 0x0000000000000000 0xa30 +.debug_frame 0x0000000000000000 0x21bc *(.debug_frame) .debug_frame 0x0000000000000000 0x168 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_frame 0x0000000000000168 0x144 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_frame 0x00000000000002ac 0xf8 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_frame 0x00000000000003a4 0x16c ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_frame 0x0000000000000510 0x38 ./system/src/newlib/_exit.o - .debug_frame 0x0000000000000548 0x7c ./system/src/newlib/_startup.o - .debug_frame 0x00000000000005c4 0x50 ./system/src/newlib/_syscalls.o - .debug_frame 0x0000000000000614 0x40 ./system/src/cortexm/_initialize_hardware.o - .debug_frame 0x0000000000000654 0xe8 ./system/src/cortexm/exception_handlers.o - .debug_frame 0x000000000000073c 0x30 ./system/src/cmsis/system_stm32f1xx.o - .debug_frame 0x000000000000076c 0x8c ./src/main.o - .debug_frame 0x00000000000007f8 0x2c ./src/stm32f1xx_hal_msp.o - .debug_frame 0x0000000000000824 0xa8 ./src/stm32f1xx_it.o - .debug_frame 0x00000000000008cc 0x40 ./my_src/led.o - .debug_frame 0x000000000000090c 0x80 ./my_src/main2.o - .debug_frame 0x000000000000098c 0xa4 ./hottislib/PontCoopScheduler.o + .debug_frame 0x0000000000000510 0x414 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_frame 0x0000000000000924 0x40 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_frame 0x0000000000000964 0xa88 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_frame 0x00000000000013ec 0x3c8 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_frame 0x00000000000017b4 0x38 ./system/src/newlib/_exit.o + .debug_frame 0x00000000000017ec 0x7c ./system/src/newlib/_startup.o + .debug_frame 0x0000000000001868 0x50 ./system/src/newlib/_syscalls.o + .debug_frame 0x00000000000018b8 0x40 ./system/src/cortexm/_initialize_hardware.o + .debug_frame 0x00000000000018f8 0xe8 ./system/src/cortexm/exception_handlers.o + .debug_frame 0x00000000000019e0 0x30 ./system/src/cmsis/system_stm32f1xx.o + .debug_frame 0x0000000000001a10 0x138 ./src/main.o + .debug_frame 0x0000000000001b48 0xbc ./src/stm32f1xx_hal_msp.o + .debug_frame 0x0000000000001c04 0xa8 ./src/stm32f1xx_it.o + .debug_frame 0x0000000000001cac 0x40 ./my_src/led.o + .debug_frame 0x0000000000001cec 0x80 ./my_src/main2.o + .debug_frame 0x0000000000001d6c 0x3ac ./my_src/oled.o + .debug_frame 0x0000000000002118 0xa4 ./hottislib/PontCoopScheduler.o -.debug_str 0x0000000000000000 0x90f76 +.debug_str 0x0000000000000000 0x99973 *(.debug_str) - .debug_str 0x0000000000000000 0x8db62 ./system/src/stm32f1xx/stm32f1xx_hal.o - 0x8e153 (size before relaxing) - .debug_str 0x000000000008db62 0x2cf ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - 0x8e155 (size before relaxing) - .debug_str 0x000000000008de31 0x452 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - 0x8de5d (size before relaxing) - .debug_str 0x000000000008e283 0x3d6 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - 0x8deb6 (size before relaxing) - .debug_str 0x000000000008e659 0x10b6 ./system/src/newlib/_exit.o + .debug_str 0x0000000000000000 0x947f3 ./system/src/stm32f1xx/stm32f1xx_hal.o + 0x94de9 (size before relaxing) + .debug_str 0x00000000000947f3 0x2cf ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + 0x94deb (size before relaxing) + .debug_str 0x0000000000094ac2 0x436 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + 0x94af3 (size before relaxing) + .debug_str 0x0000000000094ef8 0x3d6 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + 0x94b4c (size before relaxing) + .debug_str 0x00000000000952ce 0x701 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + 0x94dc0 (size before relaxing) + .debug_str 0x00000000000959cf 0x48 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + 0x94a45 (size before relaxing) + .debug_str 0x0000000000095a17 0xe79 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + 0x95774 (size before relaxing) + .debug_str 0x0000000000096890 0x4c4 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + 0x9500e (size before relaxing) + .debug_str 0x0000000000096d54 0x10b6 ./system/src/newlib/_exit.o 0x6e32 (size before relaxing) - .debug_str 0x000000000008f70f 0x266 ./system/src/newlib/_startup.o + .debug_str 0x0000000000097e0a 0x266 ./system/src/newlib/_startup.o 0x5db6 (size before relaxing) - .debug_str 0x000000000008f975 0x11d8 ./system/src/newlib/_syscalls.o + .debug_str 0x0000000000098070 0x11d8 ./system/src/newlib/_syscalls.o 0x6fdb (size before relaxing) - .debug_str 0x0000000000090b4d 0x77 ./system/src/cortexm/_initialize_hardware.o + .debug_str 0x0000000000099248 0x77 ./system/src/cortexm/_initialize_hardware.o 0x61edb (size before relaxing) - .debug_str 0x0000000000090bc4 0x1ce ./system/src/cortexm/exception_handlers.o + .debug_str 0x00000000000992bf 0x1ce ./system/src/cortexm/exception_handlers.o 0x667d0 (size before relaxing) - .debug_str 0x0000000000090d92 0x4d ./system/src/cmsis/system_stm32f1xx.o + .debug_str 0x000000000009948d 0x4d ./system/src/cmsis/system_stm32f1xx.o 0x61f2f (size before relaxing) - .debug_str 0x0000000000090ddf 0x89 ./src/main.o - 0x8e02f (size before relaxing) - .debug_str 0x0000000000090e68 0x1b ./src/stm32f1xx_hal_msp.o - 0x8ddd3 (size before relaxing) - .debug_str 0x0000000000090e83 0x28 ./src/stm32f1xx_it.o - 0x8da1f (size before relaxing) - .debug_str 0x0000000000090eab 0x51 ./my_src/led.o - 0x8d9d8 (size before relaxing) - .debug_str 0x0000000000090efc 0x34 ./my_src/main2.o - 0x8dad1 (size before relaxing) - .debug_str 0x0000000000090f30 0x46 ./hottislib/PontCoopScheduler.o + .debug_str 0x00000000000994da 0x119 ./src/main.o + 0x95570 (size before relaxing) + .debug_str 0x00000000000995f3 0x25 ./src/stm32f1xx_hal_msp.o + 0x950a7 (size before relaxing) + .debug_str 0x0000000000099618 0x28 ./src/stm32f1xx_it.o + 0x946b5 (size before relaxing) + .debug_str 0x0000000000099640 0x51 ./my_src/led.o + 0x9466e (size before relaxing) + .debug_str 0x0000000000099691 0x42 ./my_src/main2.o + 0x9477d (size before relaxing) + .debug_str 0x00000000000996d3 0x25a ./my_src/oled.o + 0x94c72 (size before relaxing) + .debug_str 0x000000000009992d 0x46 ./hottislib/PontCoopScheduler.o 0x5dc0 (size before relaxing) -.debug_loc 0x0000000000000000 0x17e7 +.debug_loc 0x0000000000000000 0x664c *(.debug_loc) .debug_loc 0x0000000000000000 0x81 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_loc 0x0000000000000081 0x58c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_loc 0x000000000000060d 0x446 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_loc 0x0000000000000a53 0x8ba ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_loc 0x000000000000130d 0x265 ./system/src/newlib/_startup.o - .debug_loc 0x0000000000001572 0x63 ./system/src/newlib/_syscalls.o - .debug_loc 0x00000000000015d5 0xdf ./system/src/cmsis/system_stm32f1xx.o - .debug_loc 0x00000000000016b4 0x21 ./my_src/led.o - .debug_loc 0x00000000000016d5 0x112 ./hottislib/PontCoopScheduler.o + .debug_loc 0x000000000000130d 0x101d ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_loc 0x000000000000232a 0xa3 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_loc 0x00000000000023cd 0x2748 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_loc 0x0000000000004b15 0xbe1 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_loc 0x00000000000056f6 0x265 ./system/src/newlib/_startup.o + .debug_loc 0x000000000000595b 0x63 ./system/src/newlib/_syscalls.o + .debug_loc 0x00000000000059be 0xdf ./system/src/cmsis/system_stm32f1xx.o + .debug_loc 0x0000000000005a9d 0x151 ./src/stm32f1xx_hal_msp.o + .debug_loc 0x0000000000005bee 0x21 ./my_src/led.o + .debug_loc 0x0000000000005c0f 0x92b ./my_src/oled.o + .debug_loc 0x000000000000653a 0x112 ./hottislib/PontCoopScheduler.o .debug_macinfo *(.debug_macinfo) @@ -3492,111 +4478,124 @@ END GROUP *(.debug_varnames) OUTPUT(newcar.elf elf32-littlearm) -.debug_ranges 0x0000000000000000 0x428 +.debug_ranges 0x0000000000000000 0xb80 .debug_ranges 0x0000000000000000 0xa0 ./system/src/stm32f1xx/stm32f1xx_hal.o .debug_ranges 0x00000000000000a0 0x80 ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o .debug_ranges 0x0000000000000120 0x48 ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o .debug_ranges 0x0000000000000168 0x78 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_ranges 0x00000000000001e0 0x18 ./system/src/newlib/_exit.o - .debug_ranges 0x00000000000001f8 0x48 ./system/src/newlib/_startup.o - .debug_ranges 0x0000000000000240 0x20 ./system/src/newlib/_syscalls.o - .debug_ranges 0x0000000000000260 0x18 ./system/src/cortexm/_initialize_hardware.o - .debug_ranges 0x0000000000000278 0x70 ./system/src/cortexm/exception_handlers.o - .debug_ranges 0x00000000000002e8 0x20 ./system/src/cmsis/startup_stm32f103xe.o - .debug_ranges 0x0000000000000308 0x18 ./system/src/cmsis/system_stm32f1xx.o - .debug_ranges 0x0000000000000320 0x30 ./src/main.o - .debug_ranges 0x0000000000000350 0x10 ./src/stm32f1xx_hal_msp.o - .debug_ranges 0x0000000000000360 0x50 ./src/stm32f1xx_it.o - .debug_ranges 0x00000000000003b0 0x18 ./my_src/led.o - .debug_ranges 0x00000000000003c8 0x30 ./my_src/main2.o - .debug_ranges 0x00000000000003f8 0x30 ./hottislib/PontCoopScheduler.o + .debug_ranges 0x00000000000001e0 0x148 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_ranges 0x0000000000000328 0x18 ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_ranges 0x0000000000000340 0x358 ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_ranges 0x0000000000000698 0x128 ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_ranges 0x00000000000007c0 0x18 ./system/src/newlib/_exit.o + .debug_ranges 0x00000000000007d8 0x48 ./system/src/newlib/_startup.o + .debug_ranges 0x0000000000000820 0x20 ./system/src/newlib/_syscalls.o + .debug_ranges 0x0000000000000840 0x18 ./system/src/cortexm/_initialize_hardware.o + .debug_ranges 0x0000000000000858 0x70 ./system/src/cortexm/exception_handlers.o + .debug_ranges 0x00000000000008c8 0x20 ./system/src/cmsis/startup_stm32f103xe.o + .debug_ranges 0x00000000000008e8 0x18 ./system/src/cmsis/system_stm32f1xx.o + .debug_ranges 0x0000000000000900 0x60 ./src/main.o + .debug_ranges 0x0000000000000960 0x38 ./src/stm32f1xx_hal_msp.o + .debug_ranges 0x0000000000000998 0x50 ./src/stm32f1xx_it.o + .debug_ranges 0x00000000000009e8 0x18 ./my_src/led.o + .debug_ranges 0x0000000000000a00 0x30 ./my_src/main2.o + .debug_ranges 0x0000000000000a30 0x120 ./my_src/oled.o + .debug_ranges 0x0000000000000b50 0x30 ./hottislib/PontCoopScheduler.o -.debug_macro 0x0000000000000000 0x1a328 - .debug_macro 0x0000000000000000 0x2c0 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000002c0 0x886 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000b46 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000b5c 0x180 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000cdc 0x2e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000d0a 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000000d2c 0x34e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000000107a 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000010ae 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000010e2 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000001c70 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000123cd 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000012410 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015793 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000157b5 0x4c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015801 0x8d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001588e 0x35 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000158c3 0x9c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001595f 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015975 0x4a ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000159bf 0x97 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015a56 0x30d ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015d63 0xfd ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015e60 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015e70 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015ec2 0x1f ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015ee1 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015f24 0x20 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000015f44 0x187 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000160cb 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000160db 0x5e ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016139 0x1c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016155 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161a7 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161e7 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000161f7 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016237 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001630e 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016324 0x189 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000164ad 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016504 0x778 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000016c7c 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017153 0x141 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017294 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017463 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017611 0x2a ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001763b 0x3c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017677 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000176ce 0x8c ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x000000000001775a 0x250 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x00000000000179aa 0x143 ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017aed 0xae ./system/src/stm32f1xx/stm32f1xx_hal.o - .debug_macro 0x0000000000017b9b 0x29c ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o - .debug_macro 0x0000000000017e37 0x30c ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o - .debug_macro 0x0000000000018143 0x2c0 ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o - .debug_macro 0x0000000000018403 0x19c ./system/src/newlib/_exit.o - .debug_macro 0x000000000001859f 0x10e ./system/src/newlib/_exit.o - .debug_macro 0x00000000000186ad 0x8d ./system/src/newlib/_exit.o - .debug_macro 0x000000000001873a 0x35 ./system/src/newlib/_exit.o - .debug_macro 0x000000000001876f 0x15b ./system/src/newlib/_startup.o - .debug_macro 0x00000000000188ca 0x1d1 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018a9b 0x1c ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ab7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ac7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ad7 0x10 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018ae7 0x35 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018b1c 0x122 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018c3e 0x88 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018cc6 0x10c ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018dd2 0x159 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018f2b 0x16 ./system/src/newlib/_syscalls.o - .debug_macro 0x0000000000018f41 0x8a ./system/src/cortexm/_initialize_hardware.o - .debug_macro 0x0000000000018fcb 0x217 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000191e2 0x3a ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001921c 0x22 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001923e 0x10 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001924e 0xcf ./system/src/cortexm/exception_handlers.o - .debug_macro 0x000000000001931d 0xbe ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000193db 0x10 ./system/src/cortexm/exception_handlers.o - .debug_macro 0x00000000000193eb 0x8c ./system/src/cmsis/system_stm32f1xx.o - .debug_macro 0x0000000000019477 0x2a6 ./src/main.o - .debug_macro 0x000000000001971d 0x29c ./src/stm32f1xx_hal_msp.o - .debug_macro 0x00000000000199b9 0x2a6 ./src/stm32f1xx_it.o - .debug_macro 0x0000000000019c5f 0x2a5 ./my_src/led.o - .debug_macro 0x0000000000019f04 0x10 ./my_src/led.o - .debug_macro 0x0000000000019f14 0x2de ./my_src/main2.o - .debug_macro 0x000000000001a1f2 0x1c ./my_src/main2.o - .debug_macro 0x000000000001a20e 0x11a ./hottislib/PontCoopScheduler.o +.debug_macro 0x0000000000000000 0x1bd0e + .debug_macro 0x0000000000000000 0x2de ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000002de 0x886 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000b64 0xca ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000c2e 0x18c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000dba 0x2e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000de8 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000000e0a 0x34e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000001158 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000000118c 0x34 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000011c0 0xb8e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000001d4e 0x1075d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000124ab 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000124ee 0x3383 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015871 0x22 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015893 0x4c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000158df 0x8d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001596c 0x35 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000159a1 0x9c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015a3d 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015a53 0x4a ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015a9d 0x97 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015b34 0x30d ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015e41 0xfd ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015f3e 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015f4e 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015fa0 0x1f ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000015fbf 0x43 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016002 0x20 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016022 0x187 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000161a9 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000161b9 0x5e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016217 0x1c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016233 0x52 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016285 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000162c5 0x10 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000162d5 0x40 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016315 0xd7 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000163ec 0x16 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016402 0x189 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001658b 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000165e2 0x778 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000016d5a 0x4d7 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017231 0x141 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017372 0x1cf ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017541 0x1ae ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000176ef 0x2a ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017719 0x3c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017755 0x57 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000177ac 0x8c ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017838 0x250 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017a88 0x143 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017bcb 0x1f4 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x0000000000017dbf 0x83e ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000185fd 0x11 ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x000000000001860e 0xae ./system/src/stm32f1xx/stm32f1xx_hal.o + .debug_macro 0x00000000000186bc 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_cortex.o + .debug_macro 0x0000000000018976 0x32a ./system/src/stm32f1xx/stm32f1xx_hal_gpio.o + .debug_macro 0x0000000000018ca0 0x2de ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o + .debug_macro 0x0000000000018f7e 0x2c2 ./system/src/stm32f1xx/stm32f1xx_hal_spi.o + .debug_macro 0x0000000000019240 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o + .debug_macro 0x00000000000194fa 0x2bb ./system/src/stm32f1xx/stm32f1xx_hal_tim.o + .debug_macro 0x00000000000197b5 0x2ba ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o + .debug_macro 0x0000000000019a6f 0x19c ./system/src/newlib/_exit.o + .debug_macro 0x0000000000019c0b 0x10e ./system/src/newlib/_exit.o + .debug_macro 0x0000000000019d19 0x8d ./system/src/newlib/_exit.o + .debug_macro 0x0000000000019da6 0x35 ./system/src/newlib/_exit.o + .debug_macro 0x0000000000019ddb 0x15b ./system/src/newlib/_startup.o + .debug_macro 0x0000000000019f36 0x1d1 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a107 0x1c ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a123 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a133 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a143 0x10 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a153 0x35 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a188 0x122 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a2aa 0x88 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a332 0x10c ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a43e 0x159 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a597 0x16 ./system/src/newlib/_syscalls.o + .debug_macro 0x000000000001a5ad 0x8a ./system/src/cortexm/_initialize_hardware.o + .debug_macro 0x000000000001a637 0x217 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001a84e 0x3a ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001a888 0x22 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001a8aa 0x10 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001a8ba 0xcf ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001a989 0xbe ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001aa47 0x10 ./system/src/cortexm/exception_handlers.o + .debug_macro 0x000000000001aa57 0x8c ./system/src/cmsis/system_stm32f1xx.o + .debug_macro 0x000000000001aae3 0x2c4 ./src/main.o + .debug_macro 0x000000000001ada7 0x2ba ./src/stm32f1xx_hal_msp.o + .debug_macro 0x000000000001b061 0x2c4 ./src/stm32f1xx_it.o + .debug_macro 0x000000000001b325 0x2c3 ./my_src/led.o + .debug_macro 0x000000000001b5e8 0x10 ./my_src/led.o + .debug_macro 0x000000000001b5f8 0x306 ./my_src/main2.o + .debug_macro 0x000000000001b8fe 0x1c ./my_src/main2.o + .debug_macro 0x000000000001b91a 0x2da ./my_src/oled.o + .debug_macro 0x000000000001bbf4 0x11a ./hottislib/PontCoopScheduler.o diff --git a/Debug/src/main.d b/Debug/src/main.d index 8c5d6a7..8302930 100644 --- a/Debug/src/main.d +++ b/Debug/src/main.d @@ -19,6 +19,9 @@ src/main.o: ../src/main.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h \ /home/wn/workspace-stm32/newcar/my_src/main2.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,4 +68,10 @@ src/main.o: ../src/main.c ../system/include/stm32f1xx/stm32f1xx_hal.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: + /home/wn/workspace-stm32/newcar/my_src/main2.h: diff --git a/Debug/src/main.o b/Debug/src/main.o index e63b4f7..3bb615e 100644 Binary files a/Debug/src/main.o and b/Debug/src/main.o differ diff --git a/Debug/src/stm32f1xx_hal_msp.d b/Debug/src/stm32f1xx_hal_msp.d index 2f2fa5c..c995db7 100644 --- a/Debug/src/stm32f1xx_hal_msp.d +++ b/Debug/src/stm32f1xx_hal_msp.d @@ -19,7 +19,10 @@ src/stm32f1xx_hal_msp.o: ../src/stm32f1xx_hal_msp.c \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -64,3 +67,9 @@ src/stm32f1xx_hal_msp.o: ../src/stm32f1xx_hal_msp.c \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/src/stm32f1xx_hal_msp.o b/Debug/src/stm32f1xx_hal_msp.o index bbc0866..cf96c66 100644 Binary files a/Debug/src/stm32f1xx_hal_msp.o and b/Debug/src/stm32f1xx_hal_msp.o differ diff --git a/Debug/src/stm32f1xx_it.d b/Debug/src/stm32f1xx_it.d index 9a8c74d..ba7427b 100644 --- a/Debug/src/stm32f1xx_it.d +++ b/Debug/src/stm32f1xx_it.d @@ -20,6 +20,9 @@ src/stm32f1xx_it.o: ../src/stm32f1xx_it.c \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h \ ../include/stm32f1xx_it.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -66,4 +69,10 @@ src/stm32f1xx_it.o: ../src/stm32f1xx_it.c \ ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: + ../include/stm32f1xx_it.h: diff --git a/Debug/src/stm32f1xx_it.o b/Debug/src/stm32f1xx_it.o index a19b59f..504bdba 100644 Binary files a/Debug/src/stm32f1xx_it.o and b/Debug/src/stm32f1xx_it.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal.d index 06e945a..68fb5f2 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal.o index 20b0d0f..0d2df3f 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d index 49a0f1c..00126df 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_cortex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_cortex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o index d6f7902..e238f24 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_cortex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d index 113dcdc..bb1fcad 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_dma.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_dma.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o index 8dd9e8c..be242f1 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_dma.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d index 6c43a89..db13073 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_flash.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_flash.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o index 5cda21e..c8c4b20 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d index b5b8763..5a6e175 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o index b650f4e..802b5af 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_flash_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d index acbae9f..3733772 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o index bb2c5f3..490c057 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d index 1d747bd..7e7af16 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o index 84dc04a..4de600c 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_gpio_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d index d7a4e56..5047c31 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_pwr.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_pwr.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o index 2ecec67..24be530 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_pwr.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d index 0805d1a..17b813e 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o index 4197394..3032c01 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d index 1b26b2f..95243c3 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o index 3b0062d..991d3b4 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d new file mode 100644 index 0000000..f057435 --- /dev/null +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.d @@ -0,0 +1,76 @@ +system/src/stm32f1xx/stm32f1xx_hal_spi.o: \ + ../system/src/stm32f1xx/stm32f1xx_hal_spi.c \ + ../system/include/stm32f1xx/stm32f1xx_hal.h \ + ../include/stm32f1xx_hal_conf.h ../include/mxconstants.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_def.h \ + ../system/include/cmsis/device/stm32f1xx.h \ + ../system/include/cmsis/device/stm32f103xe.h \ + ../system/include/cmsis/core_cm3.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/device/system_stm32f1xx.h \ + ../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h + +../system/include/stm32f1xx/stm32f1xx_hal.h: + +../include/stm32f1xx_hal_conf.h: + +../include/mxconstants.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc.h: + +../system/include/stm32f1xx/stm32f1xx_hal_def.h: + +../system/include/cmsis/device/stm32f1xx.h: + +../system/include/cmsis/device/stm32f103xe.h: + +../system/include/cmsis/core_cm3.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/device/system_stm32f1xx.h: + +../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_cortex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o new file mode 100644 index 0000000..7fb2a4c Binary files /dev/null and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d new file mode 100644 index 0000000..0308639 --- /dev/null +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d @@ -0,0 +1,76 @@ +system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o: \ + ../system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c \ + ../system/include/stm32f1xx/stm32f1xx_hal.h \ + ../include/stm32f1xx_hal_conf.h ../include/mxconstants.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_def.h \ + ../system/include/cmsis/device/stm32f1xx.h \ + ../system/include/cmsis/device/stm32f103xe.h \ + ../system/include/cmsis/core_cm3.h \ + ../system/include/cmsis/core_cmInstr.h \ + ../system/include/cmsis/cmsis_gcc.h \ + ../system/include/cmsis/core_cmFunc.h \ + ../system/include/cmsis/device/system_stm32f1xx.h \ + ../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h + +../system/include/stm32f1xx/stm32f1xx_hal.h: + +../include/stm32f1xx_hal_conf.h: + +../include/mxconstants.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc.h: + +../system/include/stm32f1xx/stm32f1xx_hal_def.h: + +../system/include/cmsis/device/stm32f1xx.h: + +../system/include/cmsis/device/stm32f103xe.h: + +../system/include/cmsis/core_cm3.h: + +../system/include/cmsis/core_cmInstr.h: + +../system/include/cmsis/cmsis_gcc.h: + +../system/include/cmsis/core_cmFunc.h: + +../system/include/cmsis/device/system_stm32f1xx.h: + +../system/include/stm32f1xx/Legacy/stm32_hal_legacy.h: + +../system/include/stm32f1xx/stm32f1xx_hal_rcc_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio.h: + +../system/include/stm32f1xx/stm32f1xx_hal_gpio_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma.h: + +../system/include/stm32f1xx/stm32f1xx_hal_dma_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_cortex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash.h: + +../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: + +../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o new file mode 100644 index 0000000..743befa Binary files /dev/null and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d index c41fd6d..0547555 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_tim.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_tim.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o index dae0bb6..07d8336 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim.o differ diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d index a9f0a32..46837eb 100644 --- a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d +++ b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d @@ -20,7 +20,10 @@ system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_cortex.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash.h \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h \ - ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h + ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_spi.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim.h \ + ../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h ../system/include/stm32f1xx/stm32f1xx_hal.h: @@ -65,3 +68,9 @@ system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o: \ ../system/include/stm32f1xx/stm32f1xx_hal_flash_ex.h: ../system/include/stm32f1xx/stm32f1xx_hal_pwr.h: + +../system/include/stm32f1xx/stm32f1xx_hal_spi.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim.h: + +../system/include/stm32f1xx/stm32f1xx_hal_tim_ex.h: diff --git a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o index a4f209c..762d7df 100644 Binary files a/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o and b/Debug/system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o differ diff --git a/Debug/system/src/stm32f1xx/subdir.mk b/Debug/system/src/stm32f1xx/subdir.mk index a8d9ebc..8a80c41 100644 --- a/Debug/system/src/stm32f1xx/subdir.mk +++ b/Debug/system/src/stm32f1xx/subdir.mk @@ -14,6 +14,8 @@ C_SRCS += \ ../system/src/stm32f1xx/stm32f1xx_hal_pwr.c \ ../system/src/stm32f1xx/stm32f1xx_hal_rcc.c \ ../system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.c \ +../system/src/stm32f1xx/stm32f1xx_hal_spi.c \ +../system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c \ ../system/src/stm32f1xx/stm32f1xx_hal_tim.c \ ../system/src/stm32f1xx/stm32f1xx_hal_tim_ex.c @@ -28,6 +30,8 @@ OBJS += \ ./system/src/stm32f1xx/stm32f1xx_hal_pwr.o \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc.o \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.o \ +./system/src/stm32f1xx/stm32f1xx_hal_spi.o \ +./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.o \ ./system/src/stm32f1xx/stm32f1xx_hal_tim.o \ ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.o @@ -42,6 +46,8 @@ C_DEPS += \ ./system/src/stm32f1xx/stm32f1xx_hal_pwr.d \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc.d \ ./system/src/stm32f1xx/stm32f1xx_hal_rcc_ex.d \ +./system/src/stm32f1xx/stm32f1xx_hal_spi.d \ +./system/src/stm32f1xx/stm32f1xx_hal_spi_ex.d \ ./system/src/stm32f1xx/stm32f1xx_hal_tim.d \ ./system/src/stm32f1xx/stm32f1xx_hal_tim_ex.d diff --git a/cube/newcar/.mxproject b/cube/newcar/.mxproject index 07b0cc7..fcda3ce 100644 --- a/cube/newcar/.mxproject +++ b/cube/newcar/.mxproject @@ -5,9 +5,9 @@ SourcePath=/home/wn/workspace-stm32/newcar/cube/newcar/Src SourceFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;mxconstants.h;stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c; [PreviousLibFiles] -LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h; +LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xg.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f105xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f107xc.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f102x6.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f101xb.h; [PreviousUsedRideFiles] -SourceFiles=../Src/main.c;../Src/stm32f1xx_it.c;../Src/stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s; +SourceFiles=../Src/main.c;../Src/stm32f1xx_it.c;../Src/stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s; HeaderPath=../Drivers/STM32F1xx_HAL_Driver/Inc;../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Include;../Drivers/CMSIS/Device/ST/STM32F1xx/Include; diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h new file mode 100644 index 0000000..c131bc7 --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.h + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_SPI_H +#define __STM32F1xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI Directional mode state. + This parameter can be a value of @ref SPI_Direction_mode */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + +}SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + +}HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx transfer size */ + + uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx transfer size */ + + uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ + + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ + + HAL_LockTypeDef Lock; /*!< SPI locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +}SPI_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Codes SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ +/** + * @} + */ + + + + +/** @defgroup SPI_mode SPI mode + * @{ + */ +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) + +/** + * @} + */ + +/** @defgroup SPI_Direction_mode SPI Direction mode + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL + +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA + +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) + +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST + +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for STM32F1xx family + * @{ + */ +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) + +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN + +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg); \ +}while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ +}while(0) + + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Mode. + * This parameter can be a value of @ref SPI_mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction_mode + * @retval None + */ +#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__: specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_data_size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__: specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__: specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave select parameter is in allowed range. + * @param __NSS__: specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__: specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__: specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__: specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + + +/* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions --------------------------------------------------------*/ +/** @addtogroup SPI_Private_Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c new file mode 100644 index 0000000..0d873e5 --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + For 8 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + +--------------------------------------------------------------------------------------------------+ + + For 16 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | + +--------------------------------------------------------------------------------------------------+ + + note: + The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + + note: + TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_TxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxISR(SPI_HandleTypeDef *hspi); +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Configure communication direction : 1Line */ + SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Transmit data in 16 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Receive data in 16 Bit mode */ + else + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set to read data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive last data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* If CRC computation is enabled */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set: CRC Received */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + + /* Read CRC to clear RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); + } + else + { + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->RxISR = &SPI_RxISR; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size ; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->RxISR = &SPI_2LinesRxISR; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + { + /* SPI CRC error interrupt occurred ---------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + /* SPI Mode Fault error interrupt occurred --------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Overrun error interrupt occurred -----------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + } + + /* Call the Error call Back in case of Errors */ + if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : - This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback() could be implenetd in the user file. + - The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} + +/** + * @brief Return the SPI error code + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI Error Code + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + + + /** + * @brief Interrupt Handler to close Tx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + + /* Disable ERR interrupt if Receive process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + { + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Tx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to transmit amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + } + /* Transmit data in 16 Bit mode */ + else + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + } + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* calculate and transfer CRC on Tx line */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + SPI_TxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to close Rx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set to read CRC data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC to reset RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if ( (hspi->State != HAL_SPI_STATE_BUSY_RX) + || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) ) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); + + /* if Transmit process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Rx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to receive amount of data in 2Lines mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + if(hspi->RxXferCount==0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to receive amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set CRC Next to calculate CRC on Rx side */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + if(hspi->RxXferCount == 0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set (CRC ready) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State= HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ + return (SPI_VALID_CRC_ERROR); +} +/** + * @} + */ + + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c new file mode 100644 index 0000000..03e1d7e --- /dev/null +++ b/cube/newcar/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Extended SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities SPI extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/** @defgroup SPI_Private_Variables SPI Private Variables + * @{ + */ +/* Variable used to determine if device is impacted by implementation of workaround + related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: + - STM32F101CDE/STM32F103CDE + - Revision ID : Z + - SPI2 + - In receive only mode, with CRC calculation enabled, at the end of the CRC reception, + the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: + + If the value is 0, the complete data transfer is successful. + + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. + If CRCERR is found reset, the complete data transfer is considered successful. +*/ +uint8_t uCRCErrorWorkaroundCheck = 0; +/** + * @} + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + +#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif + +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for + CRC errors wrongly detected */ + /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode. + Revision ID information is only available in Debug mode, so Workaround could not be implemented + to distinguish Rev Z devices (issue present) from more recent version (issue fixed). + So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ + uCRCErrorWorkaroundCheck = 0; +#else + uCRCErrorWorkaroundCheck = 0; +#endif + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check how to handle this CRC error (workaround to be applied or not) */ + /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ + if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) ) + { + if (hspi->Instance->RXCRCR == 0) + { + return (SPI_INVALID_CRC_ERROR); + } + } + return (SPI_VALID_CRC_ERROR); +#else + return (SPI_VALID_CRC_ERROR); +#endif +} +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/cube/newcar/Inc/mxconstants.h b/cube/newcar/Inc/mxconstants.h index 5c470b1..b455401 100644 --- a/cube/newcar/Inc/mxconstants.h +++ b/cube/newcar/Inc/mxconstants.h @@ -43,6 +43,36 @@ #define LED_Pin GPIO_PIN_13 #define LED_GPIO_Port GPIOC +#define MOT4_CNT_Pin GPIO_PIN_0 +#define MOT4_CNT_GPIO_Port GPIOA +#define OLED_DC_Pin GPIO_PIN_1 +#define OLED_DC_GPIO_Port GPIOA +#define OLED_RST_Pin GPIO_PIN_2 +#define OLED_RST_GPIO_Port GPIOA +#define OLED_CS_Pin GPIO_PIN_3 +#define OLED_CS_GPIO_Port GPIOA +#define MOT1_DIR_Pin GPIO_PIN_8 +#define MOT1_DIR_GPIO_Port GPIOE +#define MOT1_PWM_Pin GPIO_PIN_9 +#define MOT1_PWM_GPIO_Port GPIOE +#define MOT2_DIR_Pin GPIO_PIN_10 +#define MOT2_DIR_GPIO_Port GPIOE +#define MOT2_PWM_Pin GPIO_PIN_11 +#define MOT2_PWM_GPIO_Port GPIOE +#define MOT3_DIR_Pin GPIO_PIN_12 +#define MOT3_DIR_GPIO_Port GPIOE +#define MOT3_PWM_Pin GPIO_PIN_13 +#define MOT3_PWM_GPIO_Port GPIOE +#define MOT4_PWM_Pin GPIO_PIN_14 +#define MOT4_PWM_GPIO_Port GPIOE +#define MOT4_DIR_Pin GPIO_PIN_15 +#define MOT4_DIR_GPIO_Port GPIOE +#define MOT1_CNT_Pin GPIO_PIN_15 +#define MOT1_CNT_GPIO_Port GPIOA +#define MOT2_CNT_Pin GPIO_PIN_2 +#define MOT2_CNT_GPIO_Port GPIOD +#define MOT3_CNT_Pin GPIO_PIN_0 +#define MOT3_CNT_GPIO_Port GPIOE /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/cube/newcar/Inc/stm32f1xx_hal_conf.h b/cube/newcar/Inc/stm32f1xx_hal_conf.h index 46779fa..c5a8100 100644 --- a/cube/newcar/Inc/stm32f1xx_hal_conf.h +++ b/cube/newcar/Inc/stm32f1xx_hal_conf.h @@ -75,9 +75,9 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/cube/newcar/Src/main.c b/cube/newcar/Src/main.c index 53d6886..397ec77 100644 --- a/cube/newcar/Src/main.c +++ b/cube/newcar/Src/main.c @@ -38,6 +38,13 @@ /* USER CODE END Includes */ /* Private variables ---------------------------------------------------------*/ +SPI_HandleTypeDef hspi1; + +TIM_HandleTypeDef htim1; +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim4; +TIM_HandleTypeDef htim8; /* USER CODE BEGIN PV */ /* Private variables ---------------------------------------------------------*/ @@ -48,6 +55,15 @@ void SystemClock_Config(void); void Error_Handler(void); static void MX_GPIO_Init(void); +static void MX_SPI1_Init(void); +static void MX_TIM1_Init(void); +static void MX_TIM2_Init(void); +static void MX_TIM3_Init(void); +static void MX_TIM4_Init(void); +static void MX_TIM8_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + /* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ @@ -75,6 +91,12 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_SPI1_Init(); + MX_TIM1_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM4_Init(); + MX_TIM8_Init(); /* USER CODE BEGIN 2 */ @@ -131,6 +153,255 @@ void SystemClock_Config(void) HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); } +/* SPI1 init function */ +static void MX_SPI1_Init(void) +{ + + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH; + hspi1.Init.CLKPhase = SPI_PHASE_2EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + +} + +/* TIM1 init function */ +static void MX_TIM1_Init(void) +{ + + TIM_ClockConfigTypeDef sClockSourceConfig; + TIM_MasterConfigTypeDef sMasterConfig; + TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig; + TIM_OC_InitTypeDef sConfigOC; + + htim1.Instance = TIM1; + htim1.Init.Prescaler = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 0; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + + if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + + sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + sBreakDeadTimeConfig.DeadTime = 0; + sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) + { + Error_Handler(); + } + + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + { + Error_Handler(); + } + + if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + + HAL_TIM_MspPostInit(&htim1); + +} + +/* TIM2 init function */ +static void MX_TIM2_Init(void) +{ + + TIM_SlaveConfigTypeDef sSlaveConfig; + TIM_MasterConfigTypeDef sMasterConfig; + + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 0; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; + sSlaveConfig.InputTrigger = TIM_TS_ETRF; + sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; + sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; + sSlaveConfig.TriggerFilter = 0; + if (HAL_TIM_SlaveConfigSynchronization(&htim2, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + +} + +/* TIM3 init function */ +static void MX_TIM3_Init(void) +{ + + TIM_SlaveConfigTypeDef sSlaveConfig; + TIM_MasterConfigTypeDef sMasterConfig; + + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 0; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; + sSlaveConfig.InputTrigger = TIM_TS_ETRF; + sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; + sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; + sSlaveConfig.TriggerFilter = 0; + if (HAL_TIM_SlaveConfigSynchronization(&htim3, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + +} + +/* TIM4 init function */ +static void MX_TIM4_Init(void) +{ + + TIM_SlaveConfigTypeDef sSlaveConfig; + TIM_MasterConfigTypeDef sMasterConfig; + + htim4.Instance = TIM4; + htim4.Init.Prescaler = 0; + htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + htim4.Init.Period = 0; + htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + if (HAL_TIM_Base_Init(&htim4) != HAL_OK) + { + Error_Handler(); + } + + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; + sSlaveConfig.InputTrigger = TIM_TS_ETRF; + sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; + sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; + sSlaveConfig.TriggerFilter = 0; + if (HAL_TIM_SlaveConfigSynchronization(&htim4, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + +} + +/* TIM8 init function */ +static void MX_TIM8_Init(void) +{ + + TIM_SlaveConfigTypeDef sSlaveConfig; + TIM_MasterConfigTypeDef sMasterConfig; + + htim8.Instance = TIM8; + htim8.Init.Prescaler = 0; + htim8.Init.CounterMode = TIM_COUNTERMODE_UP; + htim8.Init.Period = 0; + htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim8.Init.RepetitionCounter = 0; + if (HAL_TIM_Base_Init(&htim8) != HAL_OK) + { + Error_Handler(); + } + + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1; + sSlaveConfig.InputTrigger = TIM_TS_ETRF; + sSlaveConfig.TriggerPolarity = TIM_TRIGGERPOLARITY_NONINVERTED; + sSlaveConfig.TriggerPrescaler = TIM_TRIGGERPRESCALER_DIV1; + sSlaveConfig.TriggerFilter = 0; + if (HAL_TIM_SlaveConfigSynchronization(&htim8, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + +} + /** Configure pins as * Analog * Input @@ -146,16 +417,36 @@ static void MX_GPIO_Init(void) /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, MOT1_DIR_Pin|MOT2_DIR_Pin|MOT3_DIR_Pin|MOT4_DIR_Pin, GPIO_PIN_RESET); + /*Configure GPIO pin : LED_Pin */ GPIO_InitStruct.Pin = LED_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : OLED_DC_Pin OLED_RST_Pin OLED_CS_Pin */ + GPIO_InitStruct.Pin = OLED_DC_Pin|OLED_RST_Pin|OLED_CS_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : MOT1_DIR_Pin MOT2_DIR_Pin MOT3_DIR_Pin MOT4_DIR_Pin */ + GPIO_InitStruct.Pin = MOT1_DIR_Pin|MOT2_DIR_Pin|MOT3_DIR_Pin|MOT4_DIR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + } /* USER CODE BEGIN 4 */ diff --git a/cube/newcar/Src/stm32f1xx_hal_msp.c b/cube/newcar/Src/stm32f1xx_hal_msp.c index 5b0181d..32cb059 100644 --- a/cube/newcar/Src/stm32f1xx_hal_msp.c +++ b/cube/newcar/Src/stm32f1xx_hal_msp.c @@ -77,6 +77,280 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + } + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + + /**TIM2 GPIO Configuration + PA15 ------> TIM2_ETR + */ + GPIO_InitStruct.Pin = MOT1_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT1_CNT_GPIO_Port, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM2_PARTIAL_1(); + + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + + /**TIM3 GPIO Configuration + PD2 ------> TIM3_ETR + */ + GPIO_InitStruct.Pin = MOT2_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT2_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + + /**TIM4 GPIO Configuration + PE0 ------> TIM4_ETR + */ + GPIO_InitStruct.Pin = MOT3_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT3_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspInit 0 */ + + /* USER CODE END TIM8_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM8_CLK_ENABLE(); + + /**TIM8 GPIO Configuration + PA0-WKUP ------> TIM8_ETR + */ + GPIO_InitStruct.Pin = MOT4_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT4_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM8_MspInit 1 */ + + /* USER CODE END TIM8_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(htim->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspPostInit 0 */ + + /* USER CODE END TIM1_MspPostInit 0 */ + + /**TIM1 GPIO Configuration + PE9 ------> TIM1_CH1 + PE11 ------> TIM1_CH2 + PE13 ------> TIM1_CH3 + PE14 ------> TIM1_CH4 + */ + GPIO_InitStruct.Pin = MOT1_PWM_Pin|MOT2_PWM_Pin|MOT3_PWM_Pin|MOT4_PWM_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM1_ENABLE(); + + /* USER CODE BEGIN TIM1_MspPostInit 1 */ + + /* USER CODE END TIM1_MspPostInit 1 */ + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + + /**TIM2 GPIO Configuration + PA15 ------> TIM2_ETR + */ + HAL_GPIO_DeInit(MOT1_CNT_GPIO_Port, MOT1_CNT_Pin); + + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /**TIM3 GPIO Configuration + PD2 ------> TIM3_ETR + */ + HAL_GPIO_DeInit(MOT2_CNT_GPIO_Port, MOT2_CNT_Pin); + + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + + /**TIM4 GPIO Configuration + PE0 ------> TIM4_ETR + */ + HAL_GPIO_DeInit(MOT3_CNT_GPIO_Port, MOT3_CNT_Pin); + + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspDeInit 0 */ + + /* USER CODE END TIM8_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM8_CLK_DISABLE(); + + /**TIM8 GPIO Configuration + PA0-WKUP ------> TIM8_ETR + */ + HAL_GPIO_DeInit(MOT4_CNT_GPIO_Port, MOT4_CNT_Pin); + + /* USER CODE BEGIN TIM8_MspDeInit 1 */ + + /* USER CODE END TIM8_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/cube/newcar/newcar.ioc b/cube/newcar/newcar.ioc index e5cfbe2..142448a 100644 --- a/cube/newcar/newcar.ioc +++ b/cube/newcar/newcar.ioc @@ -4,17 +4,46 @@ KeepUserPlacement=false Mcu.Family=STM32F1 Mcu.IP0=NVIC Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IPNb=3 +Mcu.IP2=SPI1 +Mcu.IP3=SYS +Mcu.IP4=TIM1 +Mcu.IP5=TIM2 +Mcu.IP6=TIM3 +Mcu.IP7=TIM4 +Mcu.IP8=TIM8 +Mcu.IPNb=9 Mcu.Name=STM32F103V(C-D-E)Tx Mcu.Package=LQFP100 Mcu.Pin0=PC13-TAMPER-RTC Mcu.Pin1=OSC_IN +Mcu.Pin10=PE8 +Mcu.Pin11=PE9 +Mcu.Pin12=PE10 +Mcu.Pin13=PE11 +Mcu.Pin14=PE12 +Mcu.Pin15=PE13 +Mcu.Pin16=PE14 +Mcu.Pin17=PE15 +Mcu.Pin18=PA13 +Mcu.Pin19=PA14 Mcu.Pin2=OSC_OUT -Mcu.Pin3=PA13 -Mcu.Pin4=PA14 -Mcu.Pin5=VP_SYS_VS_Systick -Mcu.PinsNb=6 +Mcu.Pin20=PA15 +Mcu.Pin21=PD2 +Mcu.Pin22=PE0 +Mcu.Pin23=VP_SYS_VS_Systick +Mcu.Pin24=VP_TIM1_VS_ClockSourceINT +Mcu.Pin25=VP_TIM2_VS_ControllerModeClock +Mcu.Pin26=VP_TIM3_VS_ControllerModeClock +Mcu.Pin27=VP_TIM4_VS_ControllerModeClock +Mcu.Pin28=VP_TIM8_VS_ControllerModeClock +Mcu.Pin3=PA0-WKUP +Mcu.Pin4=PA1 +Mcu.Pin5=PA2 +Mcu.Pin6=PA3 +Mcu.Pin7=PA5 +Mcu.Pin8=PA6 +Mcu.Pin9=PA7 +Mcu.PinsNb=29 Mcu.UserConstants= Mcu.UserName=STM32F103VCTx MxCube.Version=4.16.1 @@ -33,10 +62,34 @@ OSC_IN.Mode=HSE-External-Oscillator OSC_IN.Signal=RCC_OSC_IN OSC_OUT.Mode=HSE-External-Oscillator OSC_OUT.Signal=RCC_OSC_OUT +PA0-WKUP.GPIOParameters=GPIO_Label +PA0-WKUP.GPIO_Label=MOT4_CNT +PA0-WKUP.Signal=S_TIM8_ETR +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=OLED_DC +PA1.Locked=true +PA1.Signal=GPIO_Output PA13.Mode=Serial_Wire PA13.Signal=SYS_JTMS-SWDIO PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK +PA15.GPIOParameters=GPIO_Label +PA15.GPIO_Label=MOT1_CNT +PA15.Signal=S_TIM2_CH1_ETR +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=OLED_RST +PA2.Locked=true +PA2.Signal=GPIO_Output +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=OLED_CS +PA3.Locked=true +PA3.Signal=GPIO_Output +PA5.Mode=Full_Duplex_Master +PA5.Signal=SPI1_SCK +PA6.Mode=Full_Duplex_Master +PA6.Signal=SPI1_MISO +PA7.Mode=Full_Duplex_Master +PA7.Signal=SPI1_MOSI PC13-TAMPER-RTC.GPIOParameters=GPIO_Label PC13-TAMPER-RTC.GPIO_Label=LED PC13-TAMPER-RTC.Locked=true @@ -50,6 +103,40 @@ PCC.Seq0=0 PCC.Series=STM32F1 PCC.Temperature=25 PCC.Vdd=3.3 +PD2.GPIOParameters=GPIO_Label +PD2.GPIO_Label=MOT2_CNT +PD2.Signal=S_TIM3_ETR +PE0.GPIOParameters=GPIO_Label +PE0.GPIO_Label=MOT3_CNT +PE0.Signal=S_TIM4_ETR +PE10.GPIOParameters=GPIO_Label +PE10.GPIO_Label=MOT2_DIR +PE10.Locked=true +PE10.Signal=GPIO_Output +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=MOT2_PWM +PE11.Signal=S_TIM1_CH2 +PE12.GPIOParameters=GPIO_Label +PE12.GPIO_Label=MOT3_DIR +PE12.Locked=true +PE12.Signal=GPIO_Output +PE13.GPIOParameters=GPIO_Label +PE13.GPIO_Label=MOT3_PWM +PE13.Signal=S_TIM1_CH3 +PE14.GPIOParameters=GPIO_Label +PE14.GPIO_Label=MOT4_PWM +PE14.Signal=S_TIM1_CH4 +PE15.GPIOParameters=GPIO_Label +PE15.GPIO_Label=MOT4_DIR +PE15.Locked=true +PE15.Signal=GPIO_Output +PE8.GPIOParameters=GPIO_Label +PE8.GPIO_Label=MOT1_DIR +PE8.Locked=true +PE8.Signal=GPIO_Output +PE9.GPIOParameters=GPIO_Label +PE9.GPIO_Label=MOT1_PWM +PE9.Signal=S_TIM1_CH1 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=2 @@ -72,7 +159,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=SW4STM32 ProjectManager.ToolChainLocation=/home/wn/workspace-stm32/newcar/cube/newcar ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false,2-MX_SPI1_Init-SPI1-false,3-MX_TIM1_Init-TIM1-false,4-MX_TIM2_Init-TIM2-false,5-MX_TIM3_Init-TIM3-false,6-MX_TIM4_Init-TIM4-false,7-MX_TIM8_Init-TIM8-false RCC.ADCFreqValue=36000000 RCC.AHBFreq_Value=72000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 @@ -100,6 +187,42 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.TimSysFreq_Value=72000000 RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 +SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1 +SH.S_TIM1_CH1.ConfNb=1 +SH.S_TIM1_CH2.0=TIM1_CH2,PWM Generation2 CH2 +SH.S_TIM1_CH2.ConfNb=1 +SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3 +SH.S_TIM1_CH3.ConfNb=1 +SH.S_TIM1_CH4.0=TIM1_CH4,PWM Generation4 CH4 +SH.S_TIM1_CH4.ConfNb=1 +SH.S_TIM2_CH1_ETR.0=TIM2_ETR,TriggerSource_ETR +SH.S_TIM2_CH1_ETR.ConfNb=1 +SH.S_TIM3_ETR.0=TIM3_ETR,TriggerSource_ETR +SH.S_TIM3_ETR.ConfNb=1 +SH.S_TIM4_ETR.0=TIM4_ETR,TriggerSource_ETR +SH.S_TIM4_ETR.ConfNb=1 +SH.S_TIM8_ETR.0=TIM8_ETR,TriggerSource_ETR +SH.S_TIM8_ETR.ConfNb=1 +SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 +SPI1.CLKPhase=SPI_PHASE_2EDGE +SPI1.CLKPolarity=SPI_POLARITY_HIGH +SPI1.CalculateBaudRate=4.5 MBits/s +SPI1.IPParameters=Mode,BaudRatePrescaler,CalculateBaudRate,CLKPhase,CLKPolarity +SPI1.Mode=SPI_MODE_MASTER +TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 +TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 +TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM1.IPParameters=Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4 VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM1_VS_ClockSourceINT.Mode=Internal +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT +VP_TIM2_VS_ControllerModeClock.Mode=Clock Mode +VP_TIM2_VS_ControllerModeClock.Signal=TIM2_VS_ControllerModeClock +VP_TIM3_VS_ControllerModeClock.Mode=Clock Mode +VP_TIM3_VS_ControllerModeClock.Signal=TIM3_VS_ControllerModeClock +VP_TIM4_VS_ControllerModeClock.Mode=Clock Mode +VP_TIM4_VS_ControllerModeClock.Signal=TIM4_VS_ControllerModeClock +VP_TIM8_VS_ControllerModeClock.Mode=Clock Mode +VP_TIM8_VS_ControllerModeClock.Signal=TIM8_VS_ControllerModeClock board=newcar diff --git a/cube/newcar/newcar.pdf b/cube/newcar/newcar.pdf new file mode 100644 index 0000000..2ec2dad Binary files /dev/null and b/cube/newcar/newcar.pdf differ diff --git a/cube/newcar/newcar.txt b/cube/newcar/newcar.txt new file mode 100644 index 0000000..da23bbf --- /dev/null +++ b/cube/newcar/newcar.txt @@ -0,0 +1,84 @@ +Configuration newcar +STM32CubeMX 4.16.1 +Date 03/31/2018 +MCU STM32F103VCTx + + + +PERIPHERALS MODES FUNCTIONS PINS +RCC Crystal/Ceramic Resonator RCC_OSC_IN OSC_IN +RCC Crystal/Ceramic Resonator RCC_OSC_OUT OSC_OUT +SPI1 Full-Duplex Master SPI1_MISO PA6 +SPI1 Full-Duplex Master SPI1_MOSI PA7 +SPI1 Full-Duplex Master SPI1_SCK PA5 +SYS Serial Wire SYS_JTCK-SWCLK PA14 +SYS Serial Wire SYS_JTMS-SWDIO PA13 +SYS SysTick SYS_VS_Systick VP_SYS_VS_Systick +TIM1 Internal Clock TIM1_VS_ClockSourceINT VP_TIM1_VS_ClockSourceINT +TIM1 PWM Generation CH1 TIM1_CH1 PE9 +TIM1 PWM Generation CH2 TIM1_CH2 PE11 +TIM1 PWM Generation CH3 TIM1_CH3 PE13 +TIM1 PWM Generation CH4 TIM1_CH4 PE14 +TIM2 External Clock Mode 1 TIM2_VS_ControllerModeClock VP_TIM2_VS_ControllerModeClock +TIM2 ETR1 TIM2_ETR PA15 +TIM3 External Clock Mode 1 TIM3_VS_ControllerModeClock VP_TIM3_VS_ControllerModeClock +TIM3 ETR1 TIM3_ETR PD2 +TIM4 External Clock Mode 1 TIM4_VS_ControllerModeClock VP_TIM4_VS_ControllerModeClock +TIM4 ETR1 TIM4_ETR PE0 +TIM8 External Clock Mode 1 TIM8_VS_ControllerModeClock VP_TIM8_VS_ControllerModeClock +TIM8 ETR1 TIM8_ETR PA0-WKUP + + + +Pin Nb PINs FUNCTIONs LABELs +7 PC13-TAMPER-RTC GPIO_Output LED +12 OSC_IN RCC_OSC_IN +13 OSC_OUT RCC_OSC_OUT +23 PA0-WKUP TIM8_ETR MOT4_CNT +24 PA1 GPIO_Output OLED_DC +25 PA2 GPIO_Output OLED_RST +26 PA3 GPIO_Output OLED_CS +30 PA5 SPI1_SCK +31 PA6 SPI1_MISO +32 PA7 SPI1_MOSI +39 PE8 GPIO_Output MOT1_DIR +40 PE9 TIM1_CH1 MOT1_PWM +41 PE10 GPIO_Output MOT2_DIR +42 PE11 TIM1_CH2 MOT2_PWM +43 PE12 GPIO_Output MOT3_DIR +44 PE13 TIM1_CH3 MOT3_PWM +45 PE14 TIM1_CH4 MOT4_PWM +46 PE15 GPIO_Output MOT4_DIR +72 PA13 SYS_JTMS-SWDIO +76 PA14 SYS_JTCK-SWCLK +77 PA15 TIM2_ETR MOT1_CNT +83 PD2 TIM3_ETR MOT2_CNT +97 PE0 TIM4_ETR MOT3_CNT + + + +SOFTWARE PROJECT + +Project Settings : +Project Name : newcar +Project Folder : /home/wn/workspace-stm32/newcar/cube/newcar +Toolchain / IDE : SW4STM32 +Firmware Package Name and Version : STM32Cube FW_F1 V1.4.0 + + +Code Generation Settings : +STM32Cube Firmware Library Package : Copy only the necessary library files +Generate peripheral initialization as a pair of '.c/.h' files per peripherals : No +Backup previously generated files when re-generating : No +Delete previously generated files when not re-generated : Yes +Set all free pins as analog (to optimize the power consumption) : No + + +Toolchains Settings : +Compiler Optimizations : Balanced Size/Speed + + + + + + diff --git a/include/mxconstants.h b/include/mxconstants.h index 5c470b1..b455401 100644 --- a/include/mxconstants.h +++ b/include/mxconstants.h @@ -43,6 +43,36 @@ #define LED_Pin GPIO_PIN_13 #define LED_GPIO_Port GPIOC +#define MOT4_CNT_Pin GPIO_PIN_0 +#define MOT4_CNT_GPIO_Port GPIOA +#define OLED_DC_Pin GPIO_PIN_1 +#define OLED_DC_GPIO_Port GPIOA +#define OLED_RST_Pin GPIO_PIN_2 +#define OLED_RST_GPIO_Port GPIOA +#define OLED_CS_Pin GPIO_PIN_3 +#define OLED_CS_GPIO_Port GPIOA +#define MOT1_DIR_Pin GPIO_PIN_8 +#define MOT1_DIR_GPIO_Port GPIOE +#define MOT1_PWM_Pin GPIO_PIN_9 +#define MOT1_PWM_GPIO_Port GPIOE +#define MOT2_DIR_Pin GPIO_PIN_10 +#define MOT2_DIR_GPIO_Port GPIOE +#define MOT2_PWM_Pin GPIO_PIN_11 +#define MOT2_PWM_GPIO_Port GPIOE +#define MOT3_DIR_Pin GPIO_PIN_12 +#define MOT3_DIR_GPIO_Port GPIOE +#define MOT3_PWM_Pin GPIO_PIN_13 +#define MOT3_PWM_GPIO_Port GPIOE +#define MOT4_PWM_Pin GPIO_PIN_14 +#define MOT4_PWM_GPIO_Port GPIOE +#define MOT4_DIR_Pin GPIO_PIN_15 +#define MOT4_DIR_GPIO_Port GPIOE +#define MOT1_CNT_Pin GPIO_PIN_15 +#define MOT1_CNT_GPIO_Port GPIOA +#define MOT2_CNT_Pin GPIO_PIN_2 +#define MOT2_CNT_GPIO_Port GPIOD +#define MOT3_CNT_Pin GPIO_PIN_0 +#define MOT3_CNT_GPIO_Port GPIOE /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ diff --git a/include/stm32f1xx_hal_conf.h b/include/stm32f1xx_hal_conf.h index 46779fa..c5a8100 100644 --- a/include/stm32f1xx_hal_conf.h +++ b/include/stm32f1xx_hal_conf.h @@ -75,9 +75,9 @@ /*#define HAL_SD_MODULE_ENABLED */ /*#define HAL_SDRAM_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED /*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ diff --git a/my_src/main2.c b/my_src/main2.c index 33d5a15..e73ca9d 100644 --- a/my_src/main2.c +++ b/my_src/main2.c @@ -21,7 +21,7 @@ #include "stm32f1xx_hal.h" #include "led.h" - +#include "oled.h" void my_setup_1() { @@ -43,6 +43,7 @@ void my_errorHandler() { void my_setup_2() { blinkInit(); + LED_P8x16Str(0, 0, "Hallo"); } diff --git a/my_src/oled-fonts.h b/my_src/oled-fonts.h new file mode 100644 index 0000000..b0d935c --- /dev/null +++ b/my_src/oled-fonts.h @@ -0,0 +1,226 @@ +/* + * oled-fonts.h + * + * Created on: May 29, 2017 + * Author: wn + */ + +#ifndef OLED_FONTS_H_ +#define OLED_FONTS_H_ + + +/* + * Code found at http://www.instructables.com/id/How-to-use-OLED-display-arduino-module/ + * Thank you very much! + * Adapted from Arduino to STM32 HAL by wollud1969 + */ + + + +const unsigned char F6x8[][6] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // sp + { 0x00, 0x00, 0x00, 0x2f, 0x00, 0x00 }, // ! + { 0x00, 0x00, 0x07, 0x00, 0x07, 0x00 }, // " + { 0x00, 0x14, 0x7f, 0x14, 0x7f, 0x14 }, // # + { 0x00, 0x24, 0x2a, 0x7f, 0x2a, 0x12 }, // $ + { 0x00, 0x62, 0x64, 0x08, 0x13, 0x23 }, // % + { 0x00, 0x36, 0x49, 0x55, 0x22, 0x50 }, // & + { 0x00, 0x00, 0x05, 0x03, 0x00, 0x00 }, // ' + { 0x00, 0x00, 0x1c, 0x22, 0x41, 0x00 }, // ( + { 0x00, 0x00, 0x41, 0x22, 0x1c, 0x00 }, // ) + { 0x00, 0x14, 0x08, 0x3E, 0x08, 0x14 }, // * + { 0x00, 0x08, 0x08, 0x3E, 0x08, 0x08 }, // + + { 0x00, 0x00, 0x00, 0xA0, 0x60, 0x00 }, // , + { 0x00, 0x08, 0x08, 0x08, 0x08, 0x08 }, // - + { 0x00, 0x00, 0x60, 0x60, 0x00, 0x00 }, // . + { 0x00, 0x20, 0x10, 0x08, 0x04, 0x02 }, // / + { 0x00, 0x3E, 0x51, 0x49, 0x45, 0x3E }, // 0 + { 0x00, 0x00, 0x42, 0x7F, 0x40, 0x00 }, // 1 + { 0x00, 0x42, 0x61, 0x51, 0x49, 0x46 }, // 2 + { 0x00, 0x21, 0x41, 0x45, 0x4B, 0x31 }, // 3 + { 0x00, 0x18, 0x14, 0x12, 0x7F, 0x10 }, // 4 + { 0x00, 0x27, 0x45, 0x45, 0x45, 0x39 }, // 5 + { 0x00, 0x3C, 0x4A, 0x49, 0x49, 0x30 }, // 6 + { 0x00, 0x01, 0x71, 0x09, 0x05, 0x03 }, // 7 + { 0x00, 0x36, 0x49, 0x49, 0x49, 0x36 }, // 8 + { 0x00, 0x06, 0x49, 0x49, 0x29, 0x1E }, // 9 + { 0x00, 0x00, 0x36, 0x36, 0x00, 0x00 }, // : + { 0x00, 0x00, 0x56, 0x36, 0x00, 0x00 }, // ; + { 0x00, 0x08, 0x14, 0x22, 0x41, 0x00 }, // < + { 0x00, 0x14, 0x14, 0x14, 0x14, 0x14 }, // = + { 0x00, 0x00, 0x41, 0x22, 0x14, 0x08 }, // > + { 0x00, 0x02, 0x01, 0x51, 0x09, 0x06 }, // ? + { 0x00, 0x32, 0x49, 0x59, 0x51, 0x3E }, // @ + { 0x00, 0x7C, 0x12, 0x11, 0x12, 0x7C }, // A + { 0x00, 0x7F, 0x49, 0x49, 0x49, 0x36 }, // B + { 0x00, 0x3E, 0x41, 0x41, 0x41, 0x22 }, // C + { 0x00, 0x7F, 0x41, 0x41, 0x22, 0x1C }, // D + { 0x00, 0x7F, 0x49, 0x49, 0x49, 0x41 }, // E + { 0x00, 0x7F, 0x09, 0x09, 0x09, 0x01 }, // F + { 0x00, 0x3E, 0x41, 0x49, 0x49, 0x7A }, // G + { 0x00, 0x7F, 0x08, 0x08, 0x08, 0x7F }, // H + { 0x00, 0x00, 0x41, 0x7F, 0x41, 0x00 }, // I + { 0x00, 0x20, 0x40, 0x41, 0x3F, 0x01 }, // J + { 0x00, 0x7F, 0x08, 0x14, 0x22, 0x41 }, // K + { 0x00, 0x7F, 0x40, 0x40, 0x40, 0x40 }, // L + { 0x00, 0x7F, 0x02, 0x0C, 0x02, 0x7F }, // M + { 0x00, 0x7F, 0x04, 0x08, 0x10, 0x7F }, // N + { 0x00, 0x3E, 0x41, 0x41, 0x41, 0x3E }, // O + { 0x00, 0x7F, 0x09, 0x09, 0x09, 0x06 }, // P + { 0x00, 0x3E, 0x41, 0x51, 0x21, 0x5E }, // Q + { 0x00, 0x7F, 0x09, 0x19, 0x29, 0x46 }, // R + { 0x00, 0x46, 0x49, 0x49, 0x49, 0x31 }, // S + { 0x00, 0x01, 0x01, 0x7F, 0x01, 0x01 }, // T + { 0x00, 0x3F, 0x40, 0x40, 0x40, 0x3F }, // U + { 0x00, 0x1F, 0x20, 0x40, 0x20, 0x1F }, // V + { 0x00, 0x3F, 0x40, 0x38, 0x40, 0x3F }, // W + { 0x00, 0x63, 0x14, 0x08, 0x14, 0x63 }, // X + { 0x00, 0x07, 0x08, 0x70, 0x08, 0x07 }, // Y + { 0x00, 0x61, 0x51, 0x49, 0x45, 0x43 }, // Z + { 0x00, 0x00, 0x7F, 0x41, 0x41, 0x00 }, // [ 91 + { 0x00, 0x02, 0x04 ,0x08, 0x10, 0x20 }, // \92 + { 0x00, 0x00, 0x41, 0x41, 0x7F, 0x00 }, // ] + { 0x00, 0x04, 0x02, 0x01, 0x02, 0x04 }, // ^ + { 0x00, 0x40, 0x40, 0x40, 0x40, 0x40 }, // _ + { 0x00, 0x00, 0x01, 0x02, 0x04, 0x00 }, // ' + { 0x00, 0x20, 0x54, 0x54, 0x54, 0x78 }, // a + { 0x00, 0x7F, 0x48, 0x44, 0x44, 0x38 }, // b + { 0x00, 0x38, 0x44, 0x44, 0x44, 0x20 }, // c + { 0x00, 0x38, 0x44, 0x44, 0x48, 0x7F }, // d + { 0x00, 0x38, 0x54, 0x54, 0x54, 0x18 }, // e + { 0x00, 0x08, 0x7E, 0x09, 0x01, 0x02 }, // f + { 0x00, 0x18, 0xA4, 0xA4, 0xA4, 0x7C }, // g + { 0x00, 0x7F, 0x08, 0x04, 0x04, 0x78 }, // h + { 0x00, 0x00, 0x44, 0x7D, 0x40, 0x00 }, // i + { 0x00, 0x40, 0x80, 0x84, 0x7D, 0x00 }, // j + { 0x00, 0x7F, 0x10, 0x28, 0x44, 0x00 }, // k + { 0x00, 0x00, 0x41, 0x7F, 0x40, 0x00 }, // l + { 0x00, 0x7C, 0x04, 0x18, 0x04, 0x78 }, // m + { 0x00, 0x7C, 0x08, 0x04, 0x04, 0x78 }, // n + { 0x00, 0x38, 0x44, 0x44, 0x44, 0x38 }, // o + { 0x00, 0xFC, 0x24, 0x24, 0x24, 0x18 }, // p + { 0x00, 0x18, 0x24, 0x24, 0x18, 0xFC }, // q + { 0x00, 0x7C, 0x08, 0x04, 0x04, 0x08 }, // r + { 0x00, 0x48, 0x54, 0x54, 0x54, 0x20 }, // s + { 0x00, 0x04, 0x3F, 0x44, 0x40, 0x20 }, // t + { 0x00, 0x3C, 0x40, 0x40, 0x20, 0x7C }, // u + { 0x00, 0x1C, 0x20, 0x40, 0x20, 0x1C }, // v + { 0x00, 0x3C, 0x40, 0x30, 0x40, 0x3C }, // w + { 0x00, 0x44, 0x28, 0x10, 0x28, 0x44 }, // x + { 0x00, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C }, // y + { 0x00, 0x44, 0x64, 0x54, 0x4C, 0x44 }, // z + { 0x14, 0x14, 0x14, 0x14, 0x14, 0x14 } // horiz lines +}; + + + + + + + + +const unsigned char F8X16[]= +{ + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,// 0 + 0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00,//!1 + 0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//"2 + 0x40,0xC0,0x78,0x40,0xC0,0x78,0x40,0x00,0x04,0x3F,0x04,0x04,0x3F,0x04,0x04,0x00,//#3 + 0x00,0x70,0x88,0xFC,0x08,0x30,0x00,0x00,0x00,0x18,0x20,0xFF,0x21,0x1E,0x00,0x00,//$4 + 0xF0,0x08,0xF0,0x00,0xE0,0x18,0x00,0x00,0x00,0x21,0x1C,0x03,0x1E,0x21,0x1E,0x00,//%5 + 0x00,0xF0,0x08,0x88,0x70,0x00,0x00,0x00,0x1E,0x21,0x23,0x24,0x19,0x27,0x21,0x10,//&6 + 0x10,0x16,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//'7 + 0x00,0x00,0x00,0xE0,0x18,0x04,0x02,0x00,0x00,0x00,0x00,0x07,0x18,0x20,0x40,0x00,//(8 + 0x00,0x02,0x04,0x18,0xE0,0x00,0x00,0x00,0x00,0x40,0x20,0x18,0x07,0x00,0x00,0x00,//)9 + 0x40,0x40,0x80,0xF0,0x80,0x40,0x40,0x00,0x02,0x02,0x01,0x0F,0x01,0x02,0x02,0x00,//*10 + 0x00,0x00,0x00,0xF0,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x1F,0x01,0x01,0x01,0x00,//+11 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xB0,0x70,0x00,0x00,0x00,0x00,0x00,//,12 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01,0x01,0x01,//-13 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,0x00,0x00,//.14 + 0x00,0x00,0x00,0x00,0x80,0x60,0x18,0x04,0x00,0x60,0x18,0x06,0x01,0x00,0x00,0x00,///15 + 0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x0F,0x10,0x20,0x20,0x10,0x0F,0x00,//016 + 0x00,0x10,0x10,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//117 + 0x00,0x70,0x08,0x08,0x08,0x88,0x70,0x00,0x00,0x30,0x28,0x24,0x22,0x21,0x30,0x00,//218 + 0x00,0x30,0x08,0x88,0x88,0x48,0x30,0x00,0x00,0x18,0x20,0x20,0x20,0x11,0x0E,0x00,//319 + 0x00,0x00,0xC0,0x20,0x10,0xF8,0x00,0x00,0x00,0x07,0x04,0x24,0x24,0x3F,0x24,0x00,//420 + 0x00,0xF8,0x08,0x88,0x88,0x08,0x08,0x00,0x00,0x19,0x21,0x20,0x20,0x11,0x0E,0x00,//521 + 0x00,0xE0,0x10,0x88,0x88,0x18,0x00,0x00,0x00,0x0F,0x11,0x20,0x20,0x11,0x0E,0x00,//622 + 0x00,0x38,0x08,0x08,0xC8,0x38,0x08,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,//723 + 0x00,0x70,0x88,0x08,0x08,0x88,0x70,0x00,0x00,0x1C,0x22,0x21,0x21,0x22,0x1C,0x00,//824 + 0x00,0xE0,0x10,0x08,0x08,0x10,0xE0,0x00,0x00,0x00,0x31,0x22,0x22,0x11,0x0F,0x00,//925 + 0x00,0x00,0x00,0xC0,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x00,//:26 + 0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x60,0x00,0x00,0x00,0x00,//;27 + 0x00,0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00,0x01,0x02,0x04,0x08,0x10,0x20,0x00,//<28 + 0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x00,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x00,//=29 + 0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00,0x00,0x20,0x10,0x08,0x04,0x02,0x01,0x00,//>30 + 0x00,0x70,0x48,0x08,0x08,0x08,0xF0,0x00,0x00,0x00,0x00,0x30,0x36,0x01,0x00,0x00,//?31 + 0xC0,0x30,0xC8,0x28,0xE8,0x10,0xE0,0x00,0x07,0x18,0x27,0x24,0x23,0x14,0x0B,0x00,//@32 + 0x00,0x00,0xC0,0x38,0xE0,0x00,0x00,0x00,0x20,0x3C,0x23,0x02,0x02,0x27,0x38,0x20,//A33 + 0x08,0xF8,0x88,0x88,0x88,0x70,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x11,0x0E,0x00,//B34 + 0xC0,0x30,0x08,0x08,0x08,0x08,0x38,0x00,0x07,0x18,0x20,0x20,0x20,0x10,0x08,0x00,//C35 + 0x08,0xF8,0x08,0x08,0x08,0x10,0xE0,0x00,0x20,0x3F,0x20,0x20,0x20,0x10,0x0F,0x00,//D36 + 0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x20,0x23,0x20,0x18,0x00,//E37 + 0x08,0xF8,0x88,0x88,0xE8,0x08,0x10,0x00,0x20,0x3F,0x20,0x00,0x03,0x00,0x00,0x00,//F38 + 0xC0,0x30,0x08,0x08,0x08,0x38,0x00,0x00,0x07,0x18,0x20,0x20,0x22,0x1E,0x02,0x00,//G39 + 0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x20,0x3F,0x21,0x01,0x01,0x21,0x3F,0x20,//H40 + 0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//I41 + 0x00,0x00,0x08,0x08,0xF8,0x08,0x08,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,0x00,//J42 + 0x08,0xF8,0x88,0xC0,0x28,0x18,0x08,0x00,0x20,0x3F,0x20,0x01,0x26,0x38,0x20,0x00,//K43 + 0x08,0xF8,0x08,0x00,0x00,0x00,0x00,0x00,0x20,0x3F,0x20,0x20,0x20,0x20,0x30,0x00,//L44 + 0x08,0xF8,0xF8,0x00,0xF8,0xF8,0x08,0x00,0x20,0x3F,0x00,0x3F,0x00,0x3F,0x20,0x00,//M45 + 0x08,0xF8,0x30,0xC0,0x00,0x08,0xF8,0x08,0x20,0x3F,0x20,0x00,0x07,0x18,0x3F,0x00,//N46 + 0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x10,0x20,0x20,0x20,0x10,0x0F,0x00,//O47 + 0x08,0xF8,0x08,0x08,0x08,0x08,0xF0,0x00,0x20,0x3F,0x21,0x01,0x01,0x01,0x00,0x00,//P48 + 0xE0,0x10,0x08,0x08,0x08,0x10,0xE0,0x00,0x0F,0x18,0x24,0x24,0x38,0x50,0x4F,0x00,//Q49 + 0x08,0xF8,0x88,0x88,0x88,0x88,0x70,0x00,0x20,0x3F,0x20,0x00,0x03,0x0C,0x30,0x20,//R50 + 0x00,0x70,0x88,0x08,0x08,0x08,0x38,0x00,0x00,0x38,0x20,0x21,0x21,0x22,0x1C,0x00,//S51 + 0x18,0x08,0x08,0xF8,0x08,0x08,0x18,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//T52 + 0x08,0xF8,0x08,0x00,0x00,0x08,0xF8,0x08,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//U53 + 0x08,0x78,0x88,0x00,0x00,0xC8,0x38,0x08,0x00,0x00,0x07,0x38,0x0E,0x01,0x00,0x00,//V54 + 0xF8,0x08,0x00,0xF8,0x00,0x08,0xF8,0x00,0x03,0x3C,0x07,0x00,0x07,0x3C,0x03,0x00,//W55 + 0x08,0x18,0x68,0x80,0x80,0x68,0x18,0x08,0x20,0x30,0x2C,0x03,0x03,0x2C,0x30,0x20,//X56 + 0x08,0x38,0xC8,0x00,0xC8,0x38,0x08,0x00,0x00,0x00,0x20,0x3F,0x20,0x00,0x00,0x00,//Y57 + 0x10,0x08,0x08,0x08,0xC8,0x38,0x08,0x00,0x20,0x38,0x26,0x21,0x20,0x20,0x18,0x00,//Z58 + 0x00,0x00,0x00,0xFE,0x02,0x02,0x02,0x00,0x00,0x00,0x00,0x7F,0x40,0x40,0x40,0x00,//[59 + 0x00,0x0C,0x30,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x06,0x38,0xC0,0x00,//\60 + 0x00,0x02,0x02,0x02,0xFE,0x00,0x00,0x00,0x00,0x40,0x40,0x40,0x7F,0x00,0x00,0x00,//]61 + 0x00,0x00,0x04,0x02,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//^62 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,//_63 + 0x00,0x02,0x02,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//`64 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x19,0x24,0x22,0x22,0x22,0x3F,0x20,//a65 + 0x08,0xF8,0x00,0x80,0x80,0x00,0x00,0x00,0x00,0x3F,0x11,0x20,0x20,0x11,0x0E,0x00,//b66 + 0x00,0x00,0x00,0x80,0x80,0x80,0x00,0x00,0x00,0x0E,0x11,0x20,0x20,0x20,0x11,0x00,//c67 + 0x00,0x00,0x00,0x80,0x80,0x88,0xF8,0x00,0x00,0x0E,0x11,0x20,0x20,0x10,0x3F,0x20,//d68 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x22,0x13,0x00,//e69 + 0x00,0x80,0x80,0xF0,0x88,0x88,0x88,0x18,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//f70 + 0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x6B,0x94,0x94,0x94,0x93,0x60,0x00,//g71 + 0x08,0xF8,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//h72 + 0x00,0x80,0x98,0x98,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//i73 + 0x00,0x00,0x00,0x80,0x98,0x98,0x00,0x00,0x00,0xC0,0x80,0x80,0x80,0x7F,0x00,0x00,//j74 + 0x08,0xF8,0x00,0x00,0x80,0x80,0x80,0x00,0x20,0x3F,0x24,0x02,0x2D,0x30,0x20,0x00,//k75 + 0x00,0x08,0x08,0xF8,0x00,0x00,0x00,0x00,0x00,0x20,0x20,0x3F,0x20,0x20,0x00,0x00,//l76 + 0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x20,0x3F,0x20,0x00,0x3F,0x20,0x00,0x3F,//m77 + 0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x3F,0x21,0x00,0x00,0x20,0x3F,0x20,//n78 + 0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x00,0x1F,0x20,0x20,0x20,0x20,0x1F,0x00,//o79 + 0x80,0x80,0x00,0x80,0x80,0x00,0x00,0x00,0x80,0xFF,0xA1,0x20,0x20,0x11,0x0E,0x00,//p80 + 0x00,0x00,0x00,0x80,0x80,0x80,0x80,0x00,0x00,0x0E,0x11,0x20,0x20,0xA0,0xFF,0x80,//q81 + 0x80,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x20,0x20,0x3F,0x21,0x20,0x00,0x01,0x00,//r82 + 0x00,0x00,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x33,0x24,0x24,0x24,0x24,0x19,0x00,//s83 + 0x00,0x80,0x80,0xE0,0x80,0x80,0x00,0x00,0x00,0x00,0x00,0x1F,0x20,0x20,0x00,0x00,//t84 + 0x80,0x80,0x00,0x00,0x00,0x80,0x80,0x00,0x00,0x1F,0x20,0x20,0x20,0x10,0x3F,0x20,//unsigned char5 + 0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x00,0x01,0x0E,0x30,0x08,0x06,0x01,0x00,//v86 + 0x80,0x80,0x00,0x80,0x00,0x80,0x80,0x80,0x0F,0x30,0x0C,0x03,0x0C,0x30,0x0F,0x00,//w87 + 0x00,0x80,0x80,0x00,0x80,0x80,0x80,0x00,0x00,0x20,0x31,0x2E,0x0E,0x31,0x20,0x00,//x88 + 0x80,0x80,0x80,0x00,0x00,0x80,0x80,0x80,0x80,0x81,0x8E,0x70,0x18,0x06,0x01,0x00,//y89 + 0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x00,0x00,0x21,0x30,0x2C,0x22,0x21,0x30,0x00,//z90 + 0x00,0x00,0x00,0x00,0x80,0x7C,0x02,0x02,0x00,0x00,0x00,0x00,0x00,0x3F,0x40,0x40,//{91 + 0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,//|92 + 0x00,0x02,0x02,0x7C,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x3F,0x00,0x00,0x00,0x00,//}93 + 0x00,0x06,0x01,0x01,0x02,0x02,0x04,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//~94 + +}; + + + + +#endif /* OLED_FONTS_H_ */ diff --git a/my_src/oled.c b/my_src/oled.c new file mode 100644 index 0000000..27c3df4 --- /dev/null +++ b/my_src/oled.c @@ -0,0 +1,525 @@ +/* + * Code found at http://www.instructables.com/id/How-to-use-OLED-display-arduino-module/ + * Thank you very much! + * Adapted from Arduino to STM32 HAL by wollud1969 + */ + + +#include "oled.h" +#include "oled-fonts.h" +#include "stm32f1xx_hal.h" + + + +#define HIGH GPIO_PIN_SET +#define LOW GPIO_PIN_RESET + + +// DO: SPI Clk, D1: SPI Data + + +extern SPI_HandleTypeDef hspi1; + + + + + + +static void __LEDPIN_RST(GPIO_PinState v) { + HAL_GPIO_WritePin(OLED_RST_GPIO_Port, OLED_RST_Pin, v); +} + +static void __LEDPIN_DC(GPIO_PinState v) { + HAL_GPIO_WritePin(OLED_DC_GPIO_Port, OLED_DC_Pin, v); +} + +static void __LEDPIN_CS(GPIO_PinState v) { + HAL_GPIO_WritePin(OLED_CS_GPIO_Port, OLED_CS_Pin, v); +} + +void LED_WrDat(unsigned char data) +{ + __LEDPIN_CS(LOW); + __LEDPIN_DC(HIGH); + + HAL_SPI_Transmit(&hspi1, &data, 1, 0); + + __LEDPIN_CS(HIGH); +} +void LED_WrCmd(unsigned char cmd) +{ + __LEDPIN_CS(LOW); + __LEDPIN_DC(LOW); + + HAL_SPI_Transmit(&hspi1, &cmd, 1, 0); + + __LEDPIN_CS(HIGH); +} +void LED_Set_Pos(unsigned char x, unsigned char y) +{ + LED_WrCmd(0xb0+y); + LED_WrCmd(((x&0xf0)>>4)|0x10); + LED_WrCmd((x&0x0f)|0x00); +} + + +void LED_Fill(unsigned char bmp_data) +{ + unsigned char y,x; + + for(y=0;y<8;y++) + { + LED_WrCmd(0xb0+y); + LED_WrCmd(0x00); + LED_WrCmd(0x10); + for(x=0;x<128;x++) + LED_WrDat(bmp_data); + } +} + + + +void LED_CLS(void) +{ + unsigned char y,x; + for(y=0;y<8;y++) + { + LED_WrCmd(0xb0+y); + LED_WrCmd(0x00); + LED_WrCmd(0x10); + for(x=0;x<128;x++) + LED_WrDat(0); + } +} + +void LED_DLY_ms(unsigned int ms) +{ + uint32_t start = HAL_GetTick(); + while (HAL_GetTick() < start + ms); +} + +void SetStartColumn(unsigned char d) +{ + LED_WrCmd(0x00+d%16); // Set Lower Column Start Address for Page Addressing Mode + // Default => 0x00 + LED_WrCmd(0x10+d/16); // Set Higher Column Start Address for Page Addressing Mode + // Default => 0x10 +} + +void SetAddressingMode(unsigned char d) +{ + LED_WrCmd(0x20); // Set Memory Addressing Mode + LED_WrCmd(d); // Default => 0x02 + // 0x00 => Horizontal Addressing Mode + // 0x01 => Vertical Addressing Mode + // 0x02 => Page Addressing Mode +} + +void SetColumnAddress(unsigned char a, unsigned char b) +{ + LED_WrCmd(0x21); // Set Column Address + LED_WrCmd(a); // Default => 0x00 (Column Start Address) + LED_WrCmd(b); // Default => 0x7F (Column End Address) +} + +void SetPageAddress(unsigned char a, unsigned char b) +{ + LED_WrCmd(0x22); // Set Page Address + LED_WrCmd(a); // Default => 0x00 (Page Start Address) + LED_WrCmd(b); // Default => 0x07 (Page End Address) +} + +void SetStartLine(unsigned char d) +{ + LED_WrCmd(0x40|d); // Set Display Start Line + // Default => 0x40 (0x00) +} + +void SetContrastControl(unsigned char d) +{ + LED_WrCmd(0x81); // Set Contrast Control + LED_WrCmd(d); // Default => 0x7F +} + +void Set_Charge_Pump(unsigned char d) +{ + LED_WrCmd(0x8D); // Set Charge Pump + LED_WrCmd(0x10|d); // Default => 0x10 + // 0x10 (0x00) => Disable Charge Pump + // 0x14 (0x04) => Enable Charge Pump +} + +void Set_Segment_Remap(unsigned char d) +{ + LED_WrCmd(0xA0|d); // Set Segment Re-Map + // Default => 0xA0 + // 0xA0 (0x00) => Column Address 0 Mapped to SEG0 + // 0xA1 (0x01) => Column Address 0 Mapped to SEG127 +} + +void Set_Entire_Display(unsigned char d) +{ + LED_WrCmd(0xA4|d); // Set Entire Display On / Off + // Default => 0xA4 + // 0xA4 (0x00) => Normal Display + // 0xA5 (0x01) => Entire Display On +} + +void Set_Inverse_Display(unsigned char d) +{ + LED_WrCmd(0xA6|d); // Set Inverse Display On/Off + // Default => 0xA6 + // 0xA6 (0x00) => Normal Display + // 0xA7 (0x01) => Inverse Display On +} + +void Set_Multiplex_Ratio(unsigned char d) +{ + LED_WrCmd(0xA8); // Set Multiplex Ratio + LED_WrCmd(d); // Default => 0x3F (1/64 Duty) +} + +void Set_Display_On_Off(unsigned char d) +{ + LED_WrCmd(0xAE|d); // Set Display On/Off + // Default => 0xAE + // 0xAE (0x00) => Display Off + // 0xAF (0x01) => Display On +} + +void SetStartPage(unsigned char d) +{ + LED_WrCmd(0xB0|d); // Set Page Start Address for Page Addressing Mode + // Default => 0xB0 (0x00) +} + +void Set_Common_Remap(unsigned char d) +{ + LED_WrCmd(0xC0|d); // Set COM Output Scan Direction + // Default => 0xC0 + // 0xC0 (0x00) => Scan from COM0 to 63 + // 0xC8 (0x08) => Scan from COM63 to 0 +} + +void Set_Display_Offset(unsigned char d) +{ + LED_WrCmd(0xD3); // Set Display Offset + LED_WrCmd(d); // Default => 0x00 +} + +void Set_Display_Clock(unsigned char d) +{ + LED_WrCmd(0xD5); // Set Display Clock Divide Ratio / Oscillator Frequency + LED_WrCmd(d); // Default => 0x80 + // D[3:0] => Display Clock Divider + // D[7:4] => Oscillator Frequency +} + +void Set_Precharge_Period(unsigned char d) +{ + LED_WrCmd(0xD9); // Set Pre-Charge Period + LED_WrCmd(d); // Default => 0x22 (2 Display Clocks [Phase 2] / 2 Display Clocks [Phase 1]) + // D[3:0] => Phase 1 Period in 1~15 Display Clocks + // D[7:4] => Phase 2 Period in 1~15 Display Clocks +} + +void Set_Common_Config(unsigned char d) +{ + LED_WrCmd(0xDA); // Set COM Pins Hardware Configuration + LED_WrCmd(0x02|d); // Default => 0x12 (0x10) + // Alternative COM Pin Configuration + // Disable COM Left/Right Re-Map +} + +void Set_VCOMH(unsigned char d) +{ + LED_WrCmd(0xDB); // Set VCOMH Deselect Level + LED_WrCmd(d); // Default => 0x20 (0.77*VCC) +} + +void Set_NOP(void) +{ + LED_WrCmd(0xE3); // Command for No Operation +} + +void oledInit(void) +{ + // LEDPIN_Init(); + // LED_PORT=0X0F; + //LED_SCLH;;; + //LED_RSTL;;; + //digitalWrite(SCL_PIN,HIGH);;; + __LEDPIN_RST(LOW); + // for(i=0;i<100;i++)asm("nop"); + LED_DLY_ms(50); + //LED_RSTH;;; + __LEDPIN_RST(HIGH); + + Set_Display_On_Off(0x00); // Display Off (0x00/0x01) + Set_Display_Clock(0x80); // Set Clock as 100 Frames/Sec + Set_Multiplex_Ratio(0x3F); // 1/64 Duty (0x0F~0x3F) + Set_Display_Offset(0x00); // Shift Mapping RAM Counter (0x00~0x3F) + SetStartLine(0x00); // Set Mapping RAM Display Start Line (0x00~0x3F) + Set_Charge_Pump(0x04); // Enable Embedded DC/DC Converter (0x00/0x04) + SetAddressingMode(0x02); // Set Page Addressing Mode (0x00/0x01/0x02) + Set_Segment_Remap(0x01); // Set SEG/Column Mapping + Set_Common_Remap(0x08); // Set COM/Row Scan Direction + Set_Common_Config(0x10); // Set Sequential Configuration (0x00/0x10) + SetContrastControl(0xCF); // Set SEG Output Current + Set_Precharge_Period(0xF1); // Set Pre-Charge as 15 Clocks & Discharge as 1 Clock + Set_VCOMH(0x40); // Set VCOM Deselect Level + Set_Entire_Display(0x00); // Disable Entire Display On (0x00/0x01) + Set_Inverse_Display(0x00); // Disable Inverse Display On (0x00/0x01) + Set_Display_On_Off(0x01); // Display On (0x00/0x01) + LED_Fill(0x00); //clear all + LED_Set_Pos(0,0); +} + + +void LED_P6x8Char(unsigned char x,unsigned char y,unsigned char ch) +{ + unsigned char c=0,i=0; + + c =ch-32; + if(x>122) + { + x=0; + y++; + } + LED_Set_Pos(x,y); + for(i=0;i<6;i++) + { + LED_WrDat(F6x8[c][i]); + } +} + +void LED_P6x8Str(unsigned char x,unsigned char y,char ch[]) +{ + unsigned char c=0,i=0,j=0; + while (ch[j]!='\0') + { + c =ch[j]-32; + if(x>126) + { + x=0; + y++; + } + LED_Set_Pos(x,y); + for(i=0;i<6;i++) + { + LED_WrDat(F6x8[c][i]); + } + x+=6; + j++; + } +} + +void LED_P8x16Str(unsigned char x,unsigned char y,char ch[]) +{ + unsigned char c=0,i=0,j=0; + while (ch[j]!='\0') + { + c =ch[j]-32; + if(x>120) + { + x=0; + y++; + } + LED_Set_Pos(x,y); + for(i=0;i<8;i++) + { + LED_WrDat(F8X16[(c<<4)+i]); + } + LED_Set_Pos(x,y+1); + for(i=0;i<8;i++) + { + LED_WrDat(F8X16[(c<<4)+i+8]); + } + x+=8; + j++; + } +} + + + +void LED_PrintBMP(unsigned char x0,unsigned char y0,unsigned char x1,unsigned char y1,unsigned char bmp[]) +{ + int ii=0; + unsigned char x,y; + for(y=y0;y<=y1;y++) + { + LED_Set_Pos(x0,y); + for(x=x0;xInstance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + + if(hspi->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PA5 ------> SPI1_SCK + PA6 ------> SPI1_MISO + PA7 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + + } + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + + /**TIM2 GPIO Configuration + PA15 ------> TIM2_ETR + */ + GPIO_InitStruct.Pin = MOT1_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT1_CNT_GPIO_Port, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM2_PARTIAL_1(); + + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + + /**TIM3 GPIO Configuration + PD2 ------> TIM3_ETR + */ + GPIO_InitStruct.Pin = MOT2_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT2_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspInit 0 */ + + /* USER CODE END TIM4_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM4_CLK_ENABLE(); + + /**TIM4 GPIO Configuration + PE0 ------> TIM4_ETR + */ + GPIO_InitStruct.Pin = MOT3_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT3_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM4_MspInit 1 */ + + /* USER CODE END TIM4_MspInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspInit 0 */ + + /* USER CODE END TIM8_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_TIM8_CLK_ENABLE(); + + /**TIM8 GPIO Configuration + PA0-WKUP ------> TIM8_ETR + */ + GPIO_InitStruct.Pin = MOT4_CNT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(MOT4_CNT_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM8_MspInit 1 */ + + /* USER CODE END TIM8_MspInit 1 */ + } + +} + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(htim->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspPostInit 0 */ + + /* USER CODE END TIM1_MspPostInit 0 */ + + /**TIM1 GPIO Configuration + PE9 ------> TIM1_CH1 + PE11 ------> TIM1_CH2 + PE13 ------> TIM1_CH3 + PE14 ------> TIM1_CH4 + */ + GPIO_InitStruct.Pin = MOT1_PWM_Pin|MOT2_PWM_Pin|MOT3_PWM_Pin|MOT4_PWM_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + __HAL_AFIO_REMAP_TIM1_ENABLE(); + + /* USER CODE BEGIN TIM1_MspPostInit 1 */ + + /* USER CODE END TIM1_MspPostInit 1 */ + } + +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) +{ + + if(htim_base->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + + /**TIM2 GPIO Configuration + PA15 ------> TIM2_ETR + */ + HAL_GPIO_DeInit(MOT1_CNT_GPIO_Port, MOT1_CNT_Pin); + + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + + /**TIM3 GPIO Configuration + PD2 ------> TIM3_ETR + */ + HAL_GPIO_DeInit(MOT2_CNT_GPIO_Port, MOT2_CNT_Pin); + + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM4) + { + /* USER CODE BEGIN TIM4_MspDeInit 0 */ + + /* USER CODE END TIM4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM4_CLK_DISABLE(); + + /**TIM4 GPIO Configuration + PE0 ------> TIM4_ETR + */ + HAL_GPIO_DeInit(MOT3_CNT_GPIO_Port, MOT3_CNT_Pin); + + /* USER CODE BEGIN TIM4_MspDeInit 1 */ + + /* USER CODE END TIM4_MspDeInit 1 */ + } + else if(htim_base->Instance==TIM8) + { + /* USER CODE BEGIN TIM8_MspDeInit 0 */ + + /* USER CODE END TIM8_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM8_CLK_DISABLE(); + + /**TIM8 GPIO Configuration + PA0-WKUP ------> TIM8_ETR + */ + HAL_GPIO_DeInit(MOT4_CNT_GPIO_Port, MOT4_CNT_Pin); + + /* USER CODE BEGIN TIM8_MspDeInit 1 */ + + /* USER CODE END TIM8_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/system/include/stm32f1xx/stm32f1xx_hal_spi.h b/system/include/stm32f1xx/stm32f1xx_hal_spi.h new file mode 100644 index 0000000..c131bc7 --- /dev/null +++ b/system/include/stm32f1xx/stm32f1xx_hal_spi.h @@ -0,0 +1,674 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.h + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_SPI_H +#define __STM32F1xx_HAL_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal_def.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint32_t Direction; /*!< Specifies the SPI Directional mode state. + This parameter can be a value of @ref SPI_Direction_mode */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ + +}SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ + HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ + +}HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx transfer size */ + + uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx transfer size */ + + uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ + + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ + + HAL_LockTypeDef Lock; /*!< SPI locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +}SPI_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Codes SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ +/** + * @} + */ + + + + +/** @defgroup SPI_mode SPI mode + * @{ + */ +#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) + +/** + * @} + */ + +/** @defgroup SPI_Direction_mode SPI Direction mode + * @{ + */ +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE + +/** + * @} + */ + +/** @defgroup SPI_data_size SPI data size + * @{ + */ +#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_16BIT SPI_CR1_DFF + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL + +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA + +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) + +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST + +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI mode disable + * @brief SPI TI Mode not supported for STM32F1xx family + * @{ + */ +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) + +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN + +/** + * @} + */ + +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flag_definition SPI Flag definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY + +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check if the specified SPI interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg); \ +}while(0) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ +}while(0) + + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Mode. + * This parameter can be a value of @ref SPI_mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction_mode + * @retval None + */ +#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__: specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_data_size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__: specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__: specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave select parameter is in allowed range. + * @param __NSS__: specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__: specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__: specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__: specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) + +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + + +/* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions --------------------------------------------------------*/ +/** @addtogroup SPI_Private_Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_HAL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f1xx/stm32f1xx_hal_spi.c b/system/src/stm32f1xx/stm32f1xx_hal_spi.c new file mode 100644 index 0000000..0d873e5 --- /dev/null +++ b/system/src/stm32f1xx/stm32f1xx_hal_spi.c @@ -0,0 +1,2410 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel + + (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* + Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + For 8 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + +--------------------------------------------------------------------------------------------------+ + + For 16 bits SPI data size transfers : + +--------------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==================================================================================================| + | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | + | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | + |=========|================|===========|===========|===========|===========|===========|===========| + | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | + | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | + +--------------------------------------------------------------------------------------------------+ + + note: + The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + + note: + TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ + +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_TxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); +static void SPI_RxISR(SPI_HandleTypeDef *hspi); +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialiaze the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx periperal. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the SPI peripheral + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief SPI MSP Init + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspInit could be implenetd in the user file + */ +} + +/** + * @brief SPI MSP DeInit + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit could be implenetd in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Configure communication direction : 1Line */ + SPI_1LINE_TX(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Transmit data in 16 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + /* Receive data in 16 Bit mode */ + else + { + while(hspi->RxXferCount > 1) + { + /* Wait until RXNE flag is set to read data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Receive last data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive last data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* If CRC computation is enabled */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set: CRC Received */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + + /* Read CRC to clear RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + /* Receive the last byte */ + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + hspi->RxXferCount--; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + } + if(hspi->TxXferCount == 0) + { + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->RxXferCount--; + } + else + { + while(hspi->TxXferCount > 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + if(hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; + } + } + } + + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + return HAL_TIMEOUT; + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + } + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + SPI_RESET_CRC(hspi); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); + } + else + { + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->RxISR = &SPI_RxISR; + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size ; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer to be + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->TxISR = &SPI_TxISR; + hspi->pTxBuffPtr = pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->RxISR = &SPI_2LinesRxISR; + hspi->pRxBuffPtr = pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->TxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + if(hspi->State == HAL_SPI_STATE_READY) + { + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Configure communication */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pRxBuffPtr = pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +{ + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + { + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Configure communication */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = 0; + hspi->TxISR = 0; + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } + + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pauses the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resumes the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stops the DMA Transfer. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) + { + HAL_DMA_Abort(hspi->hdmatx); + } + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) + { + HAL_DMA_Abort(hspi->hdmarx); + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief This function handles SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Tramitter ---------------------------------------------------*/ + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + { + /* SPI CRC error interrupt occurred ---------------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + /* SPI Mode Fault error interrupt occurred --------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Overrun error interrupt occurred -----------------------------------*/ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + { + if(hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + } + + /* Call the Error call Back in case of Errors */ + if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file + */ +} + +/** + * @brief SPI error callbacks + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ + __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + /* NOTE : - This function Should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback() could be implenetd in the user file. + - The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI state + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +{ + return hspi->State; +} + +/** + * @brief Return the SPI error code + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI Error Code + */ +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +{ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + + + /** + * @brief Interrupt Handler to close Tx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + + /* Disable ERR interrupt if Receive process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + { + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Tx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to transmit amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + hspi->Instance->DR = (*hspi->pTxBuffPtr++); + } + /* Transmit data in 16 Bit mode */ + else + { + hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); + hspi->pTxBuffPtr+=2; + } + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0) + { + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* calculate and transfer CRC on Tx line */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + SPI_TxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to close Rx transfer + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0; + + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set to read CRC data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC to reset RXNE flag */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if ( (hspi->State != HAL_SPI_STATE_BUSY_RX) + || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) ) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + } + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); + + /* if Transmit process is finished */ + if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Check if we are in Rx or in Rx/Tx Mode */ + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + /* Set state to READY before run the Callback Complete */ + hspi->State = HAL_SPI_STATE_READY; + /* Call Error call back in case of Error */ + HAL_SPI_ErrorCallback(hspi); + } + } +} + +/** + * @brief Interrupt Handler to receive amount of data in 2Lines mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + if(hspi->RxXferCount==0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief Interrupt Handler to receive amount of data in no-blocking mode + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + } + /* Receive data in 16 Bit mode */ + else + { + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr+=2; + } + hspi->RxXferCount--; + + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set CRC Next to calculate CRC on Rx side */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } + + if(hspi->RxXferCount == 0) + { + SPI_RxCloseIRQHandler(hspi); + } +} + +/** + * @brief DMA SPI transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + hspi->TxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + } + + /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* DMA Normal mode */ + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag is set (CRC ready) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Wait until RXNE flag is reset */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } + } + else + { + HAL_SPI_RxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + __IO uint16_t tmpreg = 0; + + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + { + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Check if CRC is done on going (RXNE flag set) */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) + { + /* Wait until RXNE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + + /* Wait until TXE flag is set to send data */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Wait until Busy flag is reset before disabling SPI */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + + hspi->State = HAL_SPI_STATE_READY; + + /* Check if Errors has been detected during transfer */ + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + HAL_SPI_TxRxCpltCallback(hspi); + } +} + +/** + * @brief DMA SPI half transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_RxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI Half transmit receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_SPI_TxRxHalfCpltCallback(hspi); +} + +/** + * @brief DMA SPI communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->TxXferCount = 0; + hspi->RxXferCount = 0; + hspi->State= HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief This function handles SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if(Status == RESET) + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + else + { + while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ + return (SPI_VALID_CRC_ERROR); +} +/** + * @} + */ + + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c b/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c new file mode 100644 index 0000000..03e1d7e --- /dev/null +++ b/system/src/stm32f1xx/stm32f1xx_hal_spi_ex.c @@ -0,0 +1,217 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_spi_ex.c + * @author MCD Application Team + * @version V1.0.4 + * @date 29-April-2016 + * @brief Extended SPI HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities SPI extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/** @defgroup SPI_Private_Variables SPI Private Variables + * @{ + */ +/* Variable used to determine if device is impacted by implementation of workaround + related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: + - STM32F101CDE/STM32F103CDE + - Revision ID : Z + - SPI2 + - In receive only mode, with CRC calculation enabled, at the end of the CRC reception, + the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC: + + If the value is 0, the complete data transfer is successful. + + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. + If CRCERR is found reset, the complete data transfer is considered successful. +*/ +uint8_t uCRCErrorWorkaroundCheck = 0; +/** + * @} + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * + * @{ + */ + +/** + * @brief Initializes the SPI according to the specified parameters + * in the SPI_InitTypeDef and create the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if(hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + + if(hspi->State == HAL_SPI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disble the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); + + /* Configure : NSS management */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + +#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif + +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for + CRC errors wrongly detected */ + /* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode. + Revision ID information is only available in Debug mode, so Workaround could not be implemented + to distinguish Rev Z devices (issue present) from more recent version (issue fixed). + So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ + uCRCErrorWorkaroundCheck = 0; +#else + uCRCErrorWorkaroundCheck = 0; +#endif + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors + * according to SPI instance, Device type, and revision ID. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR). +*/ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) +{ +#if defined (STM32F101xE) || defined (STM32F103xE) + /* Check how to handle this CRC error (workaround to be applied or not) */ + /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ + if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) ) + { + if (hspi->Instance->RXCRCR == 0) + { + return (SPI_INVALID_CRC_ERROR); + } + } + return (SPI_VALID_CRC_ERROR); +#else + return (SPI_VALID_CRC_ERROR); +#endif +} +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/