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fix load registers

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This commit is contained in:
Wolfgang Hottgenroth
2019-07-13 21:39:54 +01:00
parent 21c9bd0eb1
commit 5a9a6d67f0
2 changed files with 5 additions and 2 deletions
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7
src/RegisterDatapoint.py
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@ -3,6 +3,7 @@ from pymodbus.pdu import ExceptionResponse
from pymodbus.exceptions import ModbusIOException from pymodbus.exceptions import ModbusIOException
import MqttProcessor import MqttProcessor
import logging import logging
import pickle
class DatapointException(Exception): pass class DatapointException(Exception): pass
@ -142,7 +143,7 @@ def loadRegisterList(registerList):
with open(registerList, 'rb') as f: with open(registerList, 'rb') as f:
datapoints = pickle.load(f) datapoints = pickle.load(f)
RegisterDatapoint.checkRegisterList(datapoints, reset=True) checkRegisterList(datapoints)
newDatapoints = [] newDatapoints = []
for dp in datapoints: for dp in datapoints:
@ -152,11 +153,13 @@ def loadRegisterList(registerList):
newDatapoints.append(ndp) newDatapoints.append(ndp)
logging.getLogger('loadRegisterList').debug("Datapoint loaded: {0!s}".format(ndp)) logging.getLogger('loadRegisterList').debug("Datapoint loaded: {0!s}".format(ndp))
RegisterDatapoint.checkRegisterList(newDatapoints, reset=True) checkRegisterList(newDatapoints, reset=True)
with open(registerList, 'wb') as f: with open(registerList, 'wb') as f:
pickle.dump(newDatapoints, f) pickle.dump(newDatapoints, f)
return newDatapoints
def checkRegisterList(registers, reset=False): def checkRegisterList(registers, reset=False):
for r in registers: for r in registers:

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src/registers.pkl
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