drop used submodules

.gitmodules

@@ -1,15 +1,3 @@
-[submodule "content/themes/paper"]
-	path = content/themes/paper
-	url = https://github.com/nanxiaobei/hugo-paper
 [submodule "content/themes/ananke"]
 	path = content/themes/ananke
 	url = https://github.com/theNewDynamic/gohugo-theme-ananke.git
-[submodule "content/themes/hugo-book"]
-	path = content/themes/hugo-book
-	url = https://github.com/alex-shpak/hugo-book
-[submodule "content/themes/archie"]
-	path = content/themes/archie
-	url = https://github.com/athul/archie.git
-[submodule "content/themes/ed"]
-	path = content/themes/ed
-	url = https://github.com/sergeyklay/gohugo-theme-ed

content/content/_index.md

@@ -1,5 +1,4 @@
 ---
 title: "Minimal Setups"
 ---
-This is the Minimal Setups page
 

content/content/about.md

@@ -6,9 +6,10 @@ menu:
 ---
 ## About
 
-This is the about page
 
 
+[Wolfgang Hottgenroth](mailto:woho@hottis.de)
+
 
 
 `ReleaseTag = %RELEASETAG%`

content/content/articles/rgb-driver.md

@@ -0,0 +1,131 @@
+## Generating signals for PL 9823 using a MSP430
+
+### Debugging
+
+```
+mspdebug rf2500 gdb
+
+msp430-gdb -x firmware.gdb
+```
+
+Attention: the gdb in the TI toolchain package is broken, use the one from Debian
+
+
+
+### Signals Working Cycler
+
+These signals are related to code under tag `cycler_works_include_output_stage`.
+
+First octets:
+
+![](/cycler_working_first_octets.png)
+
+Last octets:
+
+![](/cycler_working_last_octets.png)
+
+Schematics and legend for signals:
+
+![](/schematics.jpeg)
+
+#### Some more explanations
+
+Consider above schematics and the screen shot "Last octets" from the oscilloscope.
+
+![](/timing.png)
+
+Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22.
+The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and 
+restart of the counter and reset when the counter matches the associated compare value.
+
+So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge.
+
+![](/74hc74-function-table.png)
+
+The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope).
+
+The interrupt service routine `shifter_isr` is triggered by the overflow and restart of the timer, this interrupt service routine provides the next bit to be 
+signaled on P1.0. This bit is stored at the falling edge of P2.4 (long pulse) in the flipflop.
+
+The short pulse (P2.1, D1) is ANDed using a 74HC08 with the inverted output of the flipflop, the long pulse (P2.4, D0) is ANDed with the non-inverted output of
+the flipflop, the ANDed results are ORed using a 74HC32.
+
+So, at the output of the OR gate (yellow on the oscilloscope) we get a long pulse for a 1 at P1.0 provided by the ISR and a short pulse for a 0 at P1.0.
+
+The routine `drawscreen` takes color values from the "frame buffer" beginning at `screendata` and translated them into the red, green and blue values and provides these values, first red, then green and finally blue to the ISR via the `DATA_REGISTER`.
+
+The ISR cycles over the `DATA_REGISTER` and presents the bits at P1.0.
+
+Additionally, when the first bit of a full draw screen cycle is presented at P1.0 by the ISR, it also sets the data enable signal at P1.1 and when the last bit has been provided it disabled the data enable signal. This signal is also synchronized using a flipflop and used to enable the short/long pulses using an AND gate.
+
+
+
+### Timing
+
+Complete cycle: 2.48us
+
+![](/pulse_complete.png)
+
+Short pulse: 550ns
+
+![](/pulse_short.png)
+
+Long pulse: 1.18us
+
+![](/pulse_long.png)
+
+
+### Load Time
+
+During of loading data into five LEDs: 297us
+
+![](/five_leds.png)
+
+During of loading data into six LEDs: 297us
+
+![](/six_leds.png)
+
+
+| # of LEDs | Load Time measured | calculated |
+| --------- | ------------------ | ---------- |
+| 5         | 297us              |            | 
+| 6         | 354us              | 356.4us    |
+| 10        |                    | 594us      |
+| 100       |                    | 5.9ms      |
+| 200       |                    | 11.8ms     |
+
+
+### Reset Circuitry
+
+It appears that the output voltage of the power supply raises that slow, that the MCU
+will not handle the reset correctly.
+
+The following circuitry should generate a valid reset signal far enough from the raise 
+of the supply voltage:
+
+![](/reset-circuit.jpeg)
+
+The circuit generates the following signals:
+
+![](/reset-signal.png)
+
+##### Reference voltage (green):
+
+```math
+U_ref = 3.3V \frac{22k\Omega}{22k\Omega + 10k\Omega} = 2.2V
+```  
+  
+
+##### Trigger voltage (purple):
+
+```math
+U_trigg = 3.3V \frac{330k\Omega}{330k\Omega + 82k\Omega} = 2.64V
+```  
+  
+
+##### RC constant:
+
+```math
+\tau = 82k\Omega \cdot 100nF = 8.2ms
+```  
+

content/content/articles/test06.md

@@ -1,5 +0,0 @@
-+++
-date = '2025-01-12T19:33:39+01:00'
-draft = false
-title = 'Test06'
-+++

content/content/articles/tetris.md

@@ -1,14 +1,14 @@
 # Tetris - Hardware and Software
 
-![](./docs/IMG_4936.jpg)
+![](/IMG_4936.jpg)
 
 Update Amplifier (separate input circuitry per PSG, it appears, that a silent PSG has a DC level on its output which is summarized to the AC output of the working PSG, so two input circuits with individual couping capacitor):
 
-![](./docs/IMG_4941.jpg)
+![](/IMG_4941.jpg)
 
 Update of the power switch of the amplifier (at appears, that the small transistor couldn't deliver enough current):
 
-![](./docs/IMG_4958.jpeg)
+![](/IMG_4958.jpeg)
 
 This Tetris implementation consists of a hardware and a software (running on that hardware).
 
@@ -26,7 +26,7 @@ The buttons are debounced using RC circuitry and Schmitt triggers and connected
 
 The peripherial microcontrollers and the EEPROM are connected via SPI including individual chip select lines.
 
-![](./docs/game-ctrl.jpg)
+![](/game-ctrl.jpg)
 
 
 ## Play Ground Canvas
@@ -37,9 +37,9 @@ The play ground is implemented using a 10 * 20 matrix of PL9823 RGB LEDs which a
 
 The communcation with the game play controller is implemented as a sequences of tuples of LED address (0 to 211) and color code. A single octet of 253 where the LED address is expected is taken as the end-of-telegram mark. Readiness to receive a telegram is signaled to the game play controller via a single line connected to a GPIO of the game play controller.
 
-![](./docs/rgb-driver.jpg)
+![](/rgb-driver.jpg)
 
-Details are here https://gitea.hottis.de/wn/tetris/src/branch/main/rgb-driver/readme.md
+[Details are here]({{< ref "rgb-driver.md" >}} "Details are here")
 
 
 ## Score Display
@@ -50,7 +50,7 @@ In the first place, a MAX7221 was meant to be used for connecting a multiple dig
 
 Communication with the game play controller is just a 16 bit number to be displayed.
 
-![](./docs/display-driver.jpg)
+![](/display-driver.jpg)
 
 
 ## Sound Effects
@@ -63,8 +63,8 @@ An amplifier following the proposal of the AY-3-8913 datasheet is implemented us
 
 The clock generator proposed by the AY-3-8913 does not work reliably, so an alternative design from "The Art of Electronics" has been used.
 
-![](./docs/sound-driver-1.jpg) 
+![](/sound-driver-1.jpg) 
-![](./docs/sound-driver-2.png) 
+![](/sound-driver-2.png) 
-![](./docs/sound-driver-3.jpg) 
+![](/sound-driver-3.jpg) 
-![](./docs/sound-driver-4.jpg) 
+![](/sound-driver-4.jpg)