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Wolfgang Hottgenroth
2025-12-24 17:20:02 +01:00
parent bbc2b54b87
commit fe4f3941fa
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2
content/snippets/0020-debouncing.md
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@@ -29,7 +29,7 @@ When also the time the button was pressed is relevant and when it is especially
Since I couldn't remember the approaches I read about earlier I've sketched this state machine: Since I couldn't remember the approaches I read about earlier I've sketched this state machine:
![](/static/20180430110848869_0001.jpg) ![](20180430110848869_0001.jpg)
(The double-lined states are action-states which send out the related information.) (The double-lined states are action-states which send out the related information.)

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content/snippets/0170-rgb-driver.md
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@@ -23,21 +23,21 @@ These signals are related to code under tag `cycler_works_include_output_stage`.
First octets: First octets:
![](/static/cycler_working_first_octets.png) ![](cycler_working_first_octets.png)
Last octets: Last octets:
![](/static/cycler_working_last_octets.png) ![](cycler_working_last_octets.png)
Schematics and legend for signals: Schematics and legend for signals:
![](/static/schematics.jpeg) ![](schematics.jpeg)
#### Some more explanations #### Some more explanations
Consider above schematics and the screen shot "Last octets" from the oscilloscope. Consider above schematics and the screen shot "Last octets" from the oscilloscope.
![](/static/timing.png) ![](timing.png)
Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22. Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22.
The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and
@@ -45,7 +45,7 @@ restart of the counter and reset when the counter matches the associated compare
So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge. So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge.
![](/static/74hc74-function-table.png) ![](74hc74-function-table.png)
The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope). The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope).
@@ -69,26 +69,26 @@ Additionally, when the first bit of a full draw screen cycle is presented at P1.
Complete cycle: 2.48us Complete cycle: 2.48us
![](/static/pulse_complete.png) ![](pulse_complete.png)
Short pulse: 550ns Short pulse: 550ns
![](/static/pulse_short.png) ![](pulse_short.png)
Long pulse: 1.18us Long pulse: 1.18us
![](/static/pulse_long.png) ![](pulse_long.png)
### Load Time ### Load Time
During of loading data into five LEDs: 297us During of loading data into five LEDs: 297us
![](/static/five_leds.png) ![](five_leds.png)
During of loading data into six LEDs: 297us During of loading data into six LEDs: 297us
![](/static/six_leds.png) ![](six_leds.png)
| # of LEDs | Load Time measured | calculated | | # of LEDs | Load Time measured | calculated |
@@ -108,11 +108,11 @@ will not handle the reset correctly.
The following circuitry should generate a valid reset signal far enough from the raise The following circuitry should generate a valid reset signal far enough from the raise
of the supply voltage: of the supply voltage:
![](/static/reset-circuit.jpeg) ![](reset-circuit.jpeg)
The circuit generates the following signals: The circuit generates the following signals:
![](/static/reset-signal.png) ![](reset-signal.png)
##### Reference voltage (green): ##### Reference voltage (green):

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content/snippets/0190-tetris.md
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@@ -5,15 +5,15 @@ date: 2024-05-27
# Tetris - Hardware and Software # Tetris - Hardware and Software
![](/static/IMG_4936.jpg) ![](IMG_4936.jpg)
Update Amplifier (separate input circuitry per PSG, it appears, that a silent PSG has a DC level on its output which is summarized to the AC output of the working PSG, so two input circuits with individual couping capacitor): Update Amplifier (separate input circuitry per PSG, it appears, that a silent PSG has a DC level on its output which is summarized to the AC output of the working PSG, so two input circuits with individual couping capacitor):
![](/static/IMG_4941.jpg) ![](IMG_4941.jpg)
Update of the power switch of the amplifier (at appears, that the small transistor couldn't deliver enough current): Update of the power switch of the amplifier (at appears, that the small transistor couldn't deliver enough current):
![](/static/IMG_4958.jpeg) ![](IMG_4958.jpeg)
This Tetris implementation consists of a hardware and a software (running on that hardware). This Tetris implementation consists of a hardware and a software (running on that hardware).
@@ -31,7 +31,7 @@ The buttons are debounced using RC circuitry and Schmitt triggers and connected
The peripherial microcontrollers and the EEPROM are connected via SPI including individual chip select lines. The peripherial microcontrollers and the EEPROM are connected via SPI including individual chip select lines.
![](/static/game-ctrl.jpg) ![](game-ctrl.jpg)
## Play Ground Canvas ## Play Ground Canvas
@@ -42,7 +42,7 @@ The play ground is implemented using a 10 * 20 matrix of PL9823 RGB LEDs which a
The communcation with the game play controller is implemented as a sequences of tuples of LED address (0 to 211) and color code. A single octet of 253 where the LED address is expected is taken as the end-of-telegram mark. Readiness to receive a telegram is signaled to the game play controller via a single line connected to a GPIO of the game play controller. The communcation with the game play controller is implemented as a sequences of tuples of LED address (0 to 211) and color code. A single octet of 253 where the LED address is expected is taken as the end-of-telegram mark. Readiness to receive a telegram is signaled to the game play controller via a single line connected to a GPIO of the game play controller.
![](/static/rgb-driver.jpg) ![](rgb-driver.jpg)
[Details are here]({{< ref "rgb-driver.md" >}} "Details are here") [Details are here]({{< ref "rgb-driver.md" >}} "Details are here")
@@ -55,7 +55,7 @@ In the first place, a MAX7221 was meant to be used for connecting a multiple dig
Communication with the game play controller is just a 16 bit number to be displayed. Communication with the game play controller is just a 16 bit number to be displayed.
![](/static/display-driver.jpg) ![](display-driver.jpg)
## Sound Effects ## Sound Effects
@@ -68,8 +68,8 @@ An amplifier following the proposal of the AY-3-8913 datasheet is implemented us
The clock generator proposed by the AY-3-8913 does not work reliably, so an alternative design from "The Art of Electronics" has been used. The clock generator proposed by the AY-3-8913 does not work reliably, so an alternative design from "The Art of Electronics" has been used.
![](/static/sound-driver-1.jpg) ![](sound-driver-1.jpg)
![](/static/sound-driver-2.png) ![](sound-driver-2.png)
![](/static/sound-driver-3.jpg) ![](sound-driver-3.jpg)
![](/static/sound-driver-4.jpg) ![](sound-driver-4.jpg)

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content/snippets/0200-theremin.md
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@@ -4,11 +4,11 @@ date: 2013-07-01
--> -->
A [Theremin](https://en.wikipedia.org/wiki/Theremin) is a rather old electronic music instrument, invented in 1928. It is played by approaching hands to two antennas, without touching them. One antenna is used to manipulate the frequeny of the tone, the other one to manipulate the volume. A [Theremin](https://en.wikipedia.org/wiki/Theremin) is a rather old electronic music instrument, invented in 1928. It is played by approaching hands to two antennas, without touching them. One antenna is used to manipulate the frequeny of the tone, the other one to manipulate the volume.
![](/static/foto-am-30-06-13-um-20-021.jpg) ![](foto-am-30-06-13-um-20-021.jpg)
This is just another Theremin. Only basic structure of the circuit was taken from many other published Theremin circuits. This is just another Theremin. Only basic structure of the circuit was taken from many other published Theremin circuits.
![](/static/scan_005006-1024x654.jpg) ![](scan_005006-1024x654.jpg)
Completely new (or at least not found during my Theremin googling) is the digital zero-calibration. Completely new (or at least not found during my Theremin googling) is the digital zero-calibration.
@@ -29,25 +29,25 @@ When both frequencies are exactly the same, one part of the sum appears as a DC
If one oscillator is de-tuned by only a few Hz'`s, one part are this few Hz'`s (a very low, hearable frequency) and the other part is still (roughly) the doubled frequency (a high frequency). The high frequency part can now be suppressed using a lowpass-filter. If one oscillator is de-tuned by only a few Hz'`s, one part are this few Hz'`s (a very low, hearable frequency) and the other part is still (roughly) the doubled frequency (a high frequency). The high frequency part can now be suppressed using a lowpass-filter.
Multiplication of two signals can be done using an analog four quadrant multiplier, like the AD633. So, this is the schematic of the mixer+filter block: Multiplication of two signals can be done using an analog four quadrant multiplier, like the AD633. So, this is the schematic of the mixer+filter block:
![](/static/scan_005006_5-1024x717.jpg) ![](scan_005006_5-1024x717.jpg)
The output signal of this block is the difference of the detuning of the one oscillator. The output signal of this block is the difference of the detuning of the one oscillator.
Detuning of the oscillator will be achieved by approaching the hand to the antenna of the oscillator. Detuning of the oscillator will be achieved by approaching the hand to the antenna of the oscillator.
![](/static/scan_005006_3.jpg) ![](scan_005006_3.jpg)
The antenna acts as a kind of a capacitive sensor and by approaching the hand a very small amount of capacity is added into the LC resonator. The antenna acts as a kind of a capacitive sensor and by approaching the hand a very small amount of capacity is added into the LC resonator.
The other oscillator is a fix-frequency oscillator which can be tuned to swing on the same frequency as the first oscillator in a not detuned state. The other oscillator is a fix-frequency oscillator which can be tuned to swing on the same frequency as the first oscillator in a not detuned state.
![](/static/scan_005006_4.jpg) ![](scan_005006_4.jpg)
This tuning is achieved by biasing the two varactor diodes. This tuning is achieved by biasing the two varactor diodes.
Here is automated tuning circuit steps in: Here is automated tuning circuit steps in:
![](/static/scan_005006_6.jpg) ![](scan_005006_6.jpg)
The low-frequency output signal of the mixer+filter block is provided through a 2-to-1 multiplexer (the four NAND-gates) into a microcontroller. The microcontroller measures the frequency and as long as it is above a frequency $\epsilon$ of say 10Hz, the bias voltage $U_{tune}$ is increased. The low-frequency output signal of the mixer+filter block is provided through a 2-to-1 multiplexer (the four NAND-gates) into a microcontroller. The microcontroller measures the frequency and as long as it is above a frequency $\epsilon$ of say 10Hz, the bias voltage $U_{tune}$ is increased.
@@ -55,7 +55,7 @@ These both oscillators with mixer+filter and one channel of the zero-calibration
The low-frequency, hearable, signal and the volume-control signal are brought together in the volume-control circuit The low-frequency, hearable, signal and the volume-control signal are brought together in the volume-control circuit
![](/static/scan_005006_2-1024x553.jpg) ![](scan_005006_2-1024x553.jpg)
Here, the low-frequency signal $U_{Lf1}$ is passed through a high-pass filter. The high-pass filter is calculated that way that the whole detunable frequency range comes onto the ramp of the filter. So, the not detuned output signal of the mixer+filter is a DC signal, which is suppressed completely by the high-pass filter (beginning of the ramp) and the maximum detuned output signal of about 2kHz matched roughly to the end of the ramp. This filtered signal is rectified and only the negative half-wave of the signal passes the diode. This half-wave signal is sieved by the larger capacitor to get a DC signal between 0 and the maximum amplitude which passed the fiter. This negative DC signal is fed into the FET, which is configured as a voltage controlled resistor. This voltage controlled resistor and the fix resistor (5k6) are building a voltage controlled voltage divider. The hearable frequency signal $U_{Lf2}$ is fed into this voltage divider  and passed to an amplifier. Here, the low-frequency signal $U_{Lf1}$ is passed through a high-pass filter. The high-pass filter is calculated that way that the whole detunable frequency range comes onto the ramp of the filter. So, the not detuned output signal of the mixer+filter is a DC signal, which is suppressed completely by the high-pass filter (beginning of the ramp) and the maximum detuned output signal of about 2kHz matched roughly to the end of the ramp. This filtered signal is rectified and only the negative half-wave of the signal passes the diode. This half-wave signal is sieved by the larger capacitor to get a DC signal between 0 and the maximum amplitude which passed the fiter. This negative DC signal is fed into the FET, which is configured as a voltage controlled resistor. This voltage controlled resistor and the fix resistor (5k6) are building a voltage controlled voltage divider. The hearable frequency signal $U_{Lf2}$ is fed into this voltage divider  and passed to an amplifier.

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content/snippets/0210-three-phase-inverter-ng.md
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@@ -7,15 +7,15 @@ I wrote in October about my first try to build a simple three phase inverter, se
In this experiment I put everything on one STM32 microcontroller. Here I used the DMA feature to feed data into the PWM counter and I calculated the sine values at start-up time on the microcontroller. Additionally I put in the driver for a CAN interface, however, it is not yet supported in the firmware. In this experiment I put everything on one STM32 microcontroller. Here I used the DMA feature to feed data into the PWM counter and I calculated the sine values at start-up time on the microcontroller. Additionally I put in the driver for a CAN interface, however, it is not yet supported in the firmware.
![](/static/img_0140.jpg) ![](img_0140.jpg)
From top to bottom you see the CAN driver, the STM32 board, opto coupler to separate logic and power part and then from right to left in the bottom half the low-side/high-side MOSFET drivers and the MOSFETs. From top to bottom you see the CAN driver, the STM32 board, opto coupler to separate logic and power part and then from right to left in the bottom half the low-side/high-side MOSFET drivers and the MOSFETs.
![](/static/img_0144.jpg) ![](img_0144.jpg)
The power supply consists of a traditional transformer and (top right) the rectifier and capacitors for the power part, together with the 12V regulator for the drivers and (top left) the regulators for 3.3V and 5V for the logic part. The power supply consists of a traditional transformer and (top right) the rectifier and capacitors for the power part, together with the 12V regulator for the drivers and (top left) the regulators for 3.3V and 5V for the logic part.
![](/static/img_0146.jpg) ![](img_0146.jpg)
The motor is the same as in the earlier experiment - I don't have too much of them. And everything is put onto one board: The motor is the same as in the earlier experiment - I don't have too much of them. And everything is put onto one board:

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content/snippets/0220-three-phase-inverter.md
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@@ -8,37 +8,37 @@ Already when I was still in school, about 30 years ago, I was curious to make an
Now, I tried it again, not longer using MOSFETs but IGBTs with free-wheeling diode. Moreover, I used some microcontrollers and sine values to feed a PWM to get a sine-alike signal shape. And this time I was able with three phases to drive an asynchronous motor. Now, I tried it again, not longer using MOSFETs but IGBTs with free-wheeling diode. Moreover, I used some microcontrollers and sine values to feed a PWM to get a sine-alike signal shape. And this time I was able with three phases to drive an asynchronous motor.
![](/static/img_0053.jpg) ![](img_0053.jpg)
The signal shaping is done with four MSP430 controllers, three as PWMs to drive the bridge and one to coordinate and control the three PWMs. The PWM controller is decoupled from the IGBT driver (IR2184) using optic couplers. The signal shaping is done with four MSP430 controllers, three as PWMs to drive the bridge and one to coordinate and control the three PWMs. The PWM controller is decoupled from the IGBT driver (IR2184) using optic couplers.
![](/static/img_0054-e1476437702547.jpg) ![](img_0054-e1476437702547.jpg)
The bridge is a three phase IGBT module is a 6MB120F-060 I got for a few euros at ebay. The bridge is a three phase IGBT module is a 6MB120F-060 I got for a few euros at ebay.
![](/static/img_0055-e1476437685461.jpg) ![](img_0055-e1476437685461.jpg)
To avoid high voltages in my setup I got a 24V async motor, also from ebay. To avoid high voltages in my setup I got a 24V async motor, also from ebay.
![](/static/img_0056.jpg) ![](img_0056.jpg)
The PWMs generate the signal from a sine table generated using Excel. Those I got this signal: The PWMs generate the signal from a sine table generated using Excel. Those I got this signal:
![](/static/inverter0_2016-09-23-4.png) ![](inverter0_2016-09-23-4.png)
The main task of the coordinator is the start the PWMs with a phase shift of 120° (digital line 1, 2 and 3): The main task of the coordinator is the start the PWMs with a phase shift of 120° (digital line 1, 2 and 3):
![](/static/2016-10-13_1.png) ![](2016-10-13_1.png)
Currently the PWMs start with random polarity. The interesting signals are the digital lines 4, 5 and 6. Currently the PWMs start with random polarity. The interesting signals are the digital lines 4, 5 and 6.
Sometimes the motor runs: Sometimes the motor runs:
![](/static/2016-10-13_works.png) ![](2016-10-13_works.png)
But sometimes not: But sometimes not:
![](/static/2016-10-13_works_not.png) ![](2016-10-13_works_not.png)
The firmware is available here [https://gitea.hottis.de/wn/inverter0](https://gitea.hottis.de/wn/inverter0) and [https://gitea.hottis.de/wn/inverter0ctrl](https://gitea.hottis.de/wn/inverter0ctrl). The firmware is available here [https://gitea.hottis.de/wn/inverter0](https://gitea.hottis.de/wn/inverter0) and [https://gitea.hottis.de/wn/inverter0ctrl](https://gitea.hottis.de/wn/inverter0ctrl).

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content/snippets/0230-timeserver2.md
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@@ -10,8 +10,8 @@ date: 2025-03-13
[Details at ntppool.org](https://www.ntppool.org/scores/93.241.86.156) [Details at ntppool.org](https://www.ntppool.org/scores/93.241.86.156)
## Harrison ## Harrison
![](/static/IMG_6089.jpg) ![](IMG_6089.jpg)
![](/static/IMG_6088.jpg) ![](IMG_6088.jpg)
Setup details for this machine are here: [https://gitea.hottis.de/wn/harrison-setup](https://gitea.hottis.de/wn/harrison-setup). Setup details for this machine are here: [https://gitea.hottis.de/wn/harrison-setup](https://gitea.hottis.de/wn/harrison-setup).
@@ -31,7 +31,7 @@ refclock nmea unit 0 mode 0x10 minpoll 4 maxpoll 4 path /dev/ttyS0 ppspath /dev/
## David ## David
![](/static/IMG_6045.jpg) ![](IMG_6045.jpg)
Details on the setup of this machine are described here: [https://minimal-setups.de/blog/timeserver/](https://minimal-setups.de/blog/timeserver/). Details on the setup of this machine are described here: [https://minimal-setups.de/blog/timeserver/](https://minimal-setups.de/blog/timeserver/).

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content/snippets/0240-timeserver.md
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@@ -4,7 +4,7 @@ date: 2025-02-11
--> -->
![](/static/IMG_6045.jpg) ![](IMG_6045.jpg)
This server utilizes `ntpsec` on Debian on a BeagleBone Black with a UBlox GPS module. This server utilizes `ntpsec` on Debian on a BeagleBone Black with a UBlox GPS module.

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content/snippets/0250-configuring-a-mikrotik.md
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@@ -108,7 +108,7 @@ The both mentioned lists `CLIENTS` and `SERVICES` are maintained at `/ip/firewal
To be honest, this special case is described in the [Mikrotik documentation](https://help.mikrotik.com/docs/spaces/ROS/pages/3211299/NAT#NAT-HairpinNAT), but I didn't understood it and had to learn it myself with an interesting test setup To be honest, this special case is described in the [Mikrotik documentation](https://help.mikrotik.com/docs/spaces/ROS/pages/3211299/NAT#NAT-HairpinNAT), but I didn't understood it and had to learn it myself with an interesting test setup
![](/static/IMG_6139.jpg) ![](IMG_6139.jpg)
(From the left to the right: client, server and admin console, in the background router and switch, on the router from the left to the right: (pseudo) WAN uplink (ethernet to my current local network), direct conncection to admin console, VLAN trunk link to the switch, client and server are connected to different VLANs on the switch) (From the left to the right: client, server and admin console, in the background router and switch, on the router from the left to the right: (pseudo) WAN uplink (ethernet to my current local network), direct conncection to admin console, VLAN trunk link to the switch, client and server are connected to different VLANs on the switch)

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sync_from_obsidian.sh
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@@ -1,14 +1,14 @@
#!/bin/bash #!/bin/bash
set -ex set -ex
SRC_DIR=~/Obsiadian/default SRC_DIR=~/Obsidian/default
SRC_PUBLIC=${SRC_DIR}/Public SRC_PUBLIC_DIR=${SRC_DIR}/Public
SRC_PUBLIC_STATIC=${SRC_DIR}/Public_Static SRC_PUBLIC_STATIC_DIR=${SRC_DIR}/Public_Static
DEST_DIR=~/Workspace/minimal-setups/content DEST_DIR=~/Workspace/minimal-setups/content
DEST_PUBLIC_DIR=${DEST_DIR}/snippets DEST_PUBLIC_DIR=${DEST_DIR}/snippets
DEST_PUBLIC_STATIC_DIR=${DEST_DIR}/static DEST_PUBLIC_STATIC_DIR=${DEST_DIR}/static
rsync -av ${SRC_PUBLIC_DIR} ${DEST_PUBLIC_DIR} rsync -av ${SRC_PUBLIC_DIR}/ ${DEST_PUBLIC_DIR}
rsync -av ${SRC_PUBLIC_STATIC_DIR} ${DEST_PUBLIC_STATIC_DIR} rsync -av ${SRC_PUBLIC_STATIC_DIR}/ ${DEST_PUBLIC_STATIC_DIR}