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Wolfgang Hottgenroth
2025-12-24 17:20:02 +01:00
parent bbc2b54b87
commit fe4f3941fa
10 changed files with 51 additions and 51 deletions
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content/snippets/0170-rgb-driver.md
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@@ -23,21 +23,21 @@ These signals are related to code under tag `cycler_works_include_output_stage`.
First octets:
![](/static/cycler_working_first_octets.png)
![](cycler_working_first_octets.png)
Last octets:
![](/static/cycler_working_last_octets.png)
![](cycler_working_last_octets.png)
Schematics and legend for signals:
![](/static/schematics.jpeg)
![](schematics.jpeg)
#### Some more explanations
Consider above schematics and the screen shot "Last octets" from the oscilloscope.
![](/static/timing.png)
![](timing.png)
Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22.
The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and
@@ -45,7 +45,7 @@ restart of the counter and reset when the counter matches the associated compare
So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge.
![](/static/74hc74-function-table.png)
![](74hc74-function-table.png)
The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope).
@@ -69,26 +69,26 @@ Additionally, when the first bit of a full draw screen cycle is presented at P1.
Complete cycle: 2.48us
![](/static/pulse_complete.png)
![](pulse_complete.png)
Short pulse: 550ns
![](/static/pulse_short.png)
![](pulse_short.png)
Long pulse: 1.18us
![](/static/pulse_long.png)
![](pulse_long.png)
### Load Time
During of loading data into five LEDs: 297us
![](/static/five_leds.png)
![](five_leds.png)
During of loading data into six LEDs: 297us
![](/static/six_leds.png)
![](six_leds.png)
| # of LEDs | Load Time measured | calculated |
@@ -108,11 +108,11 @@ will not handle the reset correctly.
The following circuitry should generate a valid reset signal far enough from the raise
of the supply voltage:
![](/static/reset-circuit.jpeg)
![](reset-circuit.jpeg)
The circuit generates the following signals:
![](/static/reset-signal.png)
![](reset-signal.png)
##### Reference voltage (green):