wn/minimal-setups
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

images

Browse Source
This commit is contained in:
Wolfgang Hottgenroth
2025-01-13 14:30:18 +01:00
parent 10dace876e
commit 6e26675c0b
2 changed files with 21 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
content/content/articles/rgb-driver.md
View File

@ -18,21 +18,21 @@ These signals are related to code under tag `cycler_works_include_output_stage`.
First octets: First octets:
![](./docs/cycler_working_first_octets.png) ![](/cycler_working_first_octets.png)
Last octets: Last octets:
![](./docs/cycler_working_last_octets.png) ![](/cycler_working_last_octets.png)
Schematics and legend for signals: Schematics and legend for signals:
![](./docs/schematics.jpeg) ![](/schematics.jpeg)
#### Some more explanations #### Some more explanations
Consider above schematics and the screen shot "Last octets" from the oscilloscope. Consider above schematics and the screen shot "Last octets" from the oscilloscope.
![](./docs/timing.png) ![](/timing.png)
Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22. Timer TA1 is running in "up mode" to the value 45 set in compare register `TA1CCR0`. The compare registers `TA1CCR1` is set to 10, `TA1CCR2` is set to 22.
The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and The output mode of the timer is set to "Reset/Set", which means the GPIO associated with `TA1CCR1` (P2.1) and `TA1CCR2` (P2.4) are set at the overflow and
@ -40,7 +40,7 @@ restart of the counter and reset when the counter matches the associated compare
So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge. So, on P2.1 (D1 on the oscilloscope) we have a long pulse and at P2.4 (D0 on the oscilloscope) we have a short pulse, with synchronous raising edge.
![](./docs/74hc74-function-table.png) ![](/74hc74-function-table.png)
The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope). The inverted signal P2.4 is connected to the Clock input of a 74HC74 D-flipflop, the data input of the flipflop is connected to GPIO P1.0 (D2 on the oscilloscope).
@ -64,26 +64,26 @@ Additionally, when the first bit of a full draw screen cycle is presented at P1.
Complete cycle: 2.48us Complete cycle: 2.48us
![](./docs/pulse_complete.png) ![](/pulse_complete.png)
Short pulse: 550ns Short pulse: 550ns
![](./docs/pulse_short.png) ![](/pulse_short.png)
Long pulse: 1.18us Long pulse: 1.18us
![](./docs/pulse_long.png) ![](/pulse_long.png)
### Load Time ### Load Time
During of loading data into five LEDs: 297us During of loading data into five LEDs: 297us
![](./docs/five_leds.png) ![](/five_leds.png)
During of loading data into six LEDs: 297us During of loading data into six LEDs: 297us
![](./docs/six_leds.png) ![](/six_leds.png)
| # of LEDs | Load Time measured | calculated | | # of LEDs | Load Time measured | calculated |
@ -103,11 +103,11 @@ will not handle the reset correctly.
The following circuitry should generate a valid reset signal far enough from the raise The following circuitry should generate a valid reset signal far enough from the raise
of the supply voltage: of the supply voltage:
![](./docs/reset-circuit.jpeg) ![](/reset-circuit.jpeg)
The circuit generates the following signals: The circuit generates the following signals:
![](./docs/reset-signal.png) ![](/reset-signal.png)
##### Reference voltage (green): ##### Reference voltage (green):

18
content/content/articles/tetris.md
View File

@ -4,11 +4,11 @@
Update Amplifier (separate input circuitry per PSG, it appears, that a silent PSG has a DC level on its output which is summarized to the AC output of the working PSG, so two input circuits with individual couping capacitor): Update Amplifier (separate input circuitry per PSG, it appears, that a silent PSG has a DC level on its output which is summarized to the AC output of the working PSG, so two input circuits with individual couping capacitor):
![](IMG_4941.jpg) ![](/IMG_4941.jpg)
Update of the power switch of the amplifier (at appears, that the small transistor couldn't deliver enough current): Update of the power switch of the amplifier (at appears, that the small transistor couldn't deliver enough current):
![](./docs/IMG_4958.jpeg) ![](/IMG_4958.jpeg)
This Tetris implementation consists of a hardware and a software (running on that hardware). This Tetris implementation consists of a hardware and a software (running on that hardware).
@ -26,7 +26,7 @@ The buttons are debounced using RC circuitry and Schmitt triggers and connected
The peripherial microcontrollers and the EEPROM are connected via SPI including individual chip select lines. The peripherial microcontrollers and the EEPROM are connected via SPI including individual chip select lines.
![](./docs/game-ctrl.jpg) ![](/game-ctrl.jpg)
## Play Ground Canvas ## Play Ground Canvas
@ -37,7 +37,7 @@ The play ground is implemented using a 10 * 20 matrix of PL9823 RGB LEDs which a
The communcation with the game play controller is implemented as a sequences of tuples of LED address (0 to 211) and color code. A single octet of 253 where the LED address is expected is taken as the end-of-telegram mark. Readiness to receive a telegram is signaled to the game play controller via a single line connected to a GPIO of the game play controller. The communcation with the game play controller is implemented as a sequences of tuples of LED address (0 to 211) and color code. A single octet of 253 where the LED address is expected is taken as the end-of-telegram mark. Readiness to receive a telegram is signaled to the game play controller via a single line connected to a GPIO of the game play controller.
![](./docs/rgb-driver.jpg) ![](/rgb-driver.jpg)
[Details are here]({{< ref "rgb-driver.md" >}} "Details are here") [Details are here]({{< ref "rgb-driver.md" >}} "Details are here")
@ -50,7 +50,7 @@ In the first place, a MAX7221 was meant to be used for connecting a multiple dig
Communication with the game play controller is just a 16 bit number to be displayed. Communication with the game play controller is just a 16 bit number to be displayed.
![](./docs/display-driver.jpg) ![](/display-driver.jpg)
## Sound Effects ## Sound Effects
@ -63,8 +63,8 @@ An amplifier following the proposal of the AY-3-8913 datasheet is implemented us
The clock generator proposed by the AY-3-8913 does not work reliably, so an alternative design from "The Art of Electronics" has been used. The clock generator proposed by the AY-3-8913 does not work reliably, so an alternative design from "The Art of Electronics" has been used.
![](./docs/sound-driver-1.jpg) ![](/sound-driver-1.jpg)
![](./docs/sound-driver-2.png) ![](/sound-driver-2.png)
![](./docs/sound-driver-3.jpg) ![](/sound-driver-3.jpg)
![](./docs/sound-driver-4.jpg) ![](/sound-driver-4.jpg)