enable hardware watchdog

This commit is contained in:
2020-12-27 11:48:10 +01:00
parent d6cd63083d
commit 1ed0c07c66
31 changed files with 3878 additions and 105 deletions

View File

@ -2014,10 +2014,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
return HAL_OK;
}
inline void dts(uint8_t v) {
while (v--) HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_10);
}
/**
* @brief This function handles UART interrupt request.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
@ -2026,8 +2022,6 @@ inline void dts(uint8_t v) {
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
HAL_GPIO_TogglePin(GPIOE, GPIO_PIN_12);
uint32_t isrflags = READ_REG(huart->Instance->SR);
uint32_t cr1its = READ_REG(huart->Instance->CR1);
uint32_t cr3its = READ_REG(huart->Instance->CR3);
@ -2038,10 +2032,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
if (errorflags == RESET)
{
/* UART in mode Receiver -------------------------------------------------*/
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
dts(1);
UART_Receive_IT(huart);
return;
}
@ -2050,7 +2043,6 @@ dts(1);
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
dts(2);
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
{
@ -2078,14 +2070,10 @@ dts(2);
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
{
dts(3);
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
dts(4);
UART_Receive_IT(huart);
} else {
dts(5);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,