Socket APIs: Todo List

Socket APIs
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Todo List
Member _WIZCHIP_
You should select one, 5100, 5200 ,5500 or etc.

ex> #define _WIZCHIP_ 5500
Member _WIZCHIP_IO_BASE_
Should re-define it to fit your system when BUS IF Mode (_WIZCHIP_IO_MODE_BUS_, _WIZCHIP_IO_MODE_BUS_DIR_, _WIZCHIP_IO_MODE_BUS_INDIR_).

ex> #define _WIZCHIP_IO_BASE_ 0x00008000
Member _WIZCHIP_IO_MODE_
Should select interface mode as chip.
  • _WIZCHIP_IO_MODE_SPI_
    -_WIZCHIP_IO_MODE_SPI_VDM_ : Valid only in _WIZCHIP_ == 5500
    -_WIZCHIP_IO_MODE_SPI_FDM_ : Valid only in _WIZCHIP_ == 5500
  • _WIZCHIP_IO_MODE_BUS_
    • _WIZCHIP_IO_MODE_BUS_DIR_
    • _WIZCHIP_IO_MODE_BUS_INDIR_
  • Others will be defined in future.

    ex> #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_
Member reg_wizchip_bus_cbfunc (uint8_t(*bus_rb)(uint32_t addr), void(*bus_wb)(uint32_t addr, uint8_t wb))
Describe wizchip_bus_readbyte and wizchip_bus_writebyte function or register your functions.
Member reg_wizchip_cris_cbfunc (void(*cris_en)(void), void(*cris_ex)(void))
Describe WIZCHIP_CRITICAL_ENTER and WIZCHIP_CRITICAL_EXIT marco or register your functions.
Member reg_wizchip_cs_cbfunc (void(*cs_sel)(void), void(*cs_desel)(void))
Describe wizchip_cs_select and wizchip_cs_deselect function or register your functions.
Member reg_wizchip_spi_cbfunc (uint8_t(*spi_rb)(void), void(*spi_wb)(uint8_t wb))
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Member reg_wizchip_spiburst_cbfunc (void(*spi_rb)(uint8_t *pBuf, uint16_t len), void(*spi_wb)(uint8_t *pBuf, uint16_t len))
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Modules

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Modules
Here is a list of all modules:
[detail level 123]
o 1. WIZnet socket APIs | WIZnet socket APIs are based on Berkeley socket APIs, thus it has much similar name and interface. But there is a little bit of difference
o 2. WIZnet Extra Functions | These functions is optional function. It could be replaced at WIZCHIP I/O function because they were made by WIZCHIP I/O functions
o DATA TYPE |
o W5100 | WHIZCHIP register defines and I/O functions of W5100
| o WIZCHIP I/O functions | This supports the basic I/O functions for WIZCHIP register
| | o Basic I/O function | These are basic input/output functions to read values from register or write values to register
| | o Common register access functions | These are functions to access common registers
| | \ Socket register access functions | These are functions to access socket registers
| \ WIZCHIP register | WIZCHIP register defines register group of W5100
| o Common register | Common register group It set the basic for the networking It set the configuration such as interrupt, network information, ICMP, etc
| \ Socket register | Socket register group Socket register configures and control SOCKETn which is necessary to data communication
o W5200 | WHIZCHIP register defines and I/O functions of W5200
| o WIZCHIP I/O functions | This supports the basic I/O functions for WIZCHIP register
| | o Basic I/O function | These are basic input/output functions to read values from register or write values to register
| | o Common register access functions | These are functions to access common registers
| | \ Socket register access functions | These are functions to access socket registers
| \ WIZCHIP register | WIZCHIP register defines register group of W5200
| o Common register | Common register group It set the basic for the networking It set the configuration such as interrupt, network information, ICMP, etc
| \ Socket register | Socket register group Socket register configures and control SOCKETn which is necessary to data communication
\ W5500 | WHIZCHIP register defines and I/O functions of W5500
o WIZCHIP I/O functions | This supports the basic I/O functions for WIZCHIP register
| o Basic I/O function | These are basic input/output functions to read values from register or write values to register
| o Common register access functions | These are functions to access common registers
| \ Socket register access functions | These are functions to access socket registers
\ WIZCHIP register | WHIZCHIP register defines register group of W5500
o Common register | Common register group It set the basic for the networking It set the configuration such as interrupt, network information, ICMP, etc
\ Socket register | Socket register group. Socket register configures and control SOCKETn which is necessary to data communication
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: 1. WIZnet socket APIs

Functions
1. WIZnet socket APIs

WIZnet socket APIs are based on Berkeley socket APIs, thus it has much similar name and interface. But there is a little bit of difference. More...

Functions

int8_t | socket (uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag)
Open a socket. More...
int8_t | close (uint8_t sn)
Close a socket. More...
int8_t | listen (uint8_t sn)
Listen to a connection request from a client. More...
int8_t | connect (uint8_t sn, uint8_t *addr, uint16_t port)
Try to connect a server. More...
int8_t | disconnect (uint8_t sn)
Try to disconnect a connection socket. More...
int32_t | send (uint8_t sn, uint8_t *buf, uint16_t len)
Send data to the connected peer in TCP socket. More...
int32_t | recv (uint8_t sn, uint8_t *buf, uint16_t len)
Receive data from the connected peer. More...
int32_t | sendto (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t port)
Sends datagram to the peer with destination IP address and port number passed as parameter. More...
int32_t | recvfrom (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t *port)
Receive datagram of UDP or MACRAW. More...
int8_t | ctlsocket (uint8_t sn, ctlsock_type cstype, void *arg)
Control socket. More...
int8_t | setsockopt (uint8_t sn, sockopt_type sotype, void *arg)
set socket options More...
int8_t | getsockopt (uint8_t sn, sockopt_type sotype, void *arg)
get socket options More...

Detailed Description

WIZnet socket APIs are based on Berkeley socket APIs, thus it has much similar name and interface. But there is a little bit of difference.

Comparison between WIZnet and Berkeley SOCKET APIs

API | WIZnet | Berkeley
socket() | O | O
bind() | X | O
listen() | O | O
connect() | O | O
accept() | X | O
recv() | O | O
send() | O | O
recvfrom() | O | O
sendto() | O | O
closesocket() | O close() & disconnect() | O

There are bind() and accept() functions in Berkeley SOCKET API but, not in WIZnet SOCKET API. Because socket() of WIZnet is not only creating a SOCKET but also binding a local port number, and listen() of WIZnet is not only listening to connection request from client but also accepting the connection request.
When you program "TCP SERVER" with Berkeley SOCKET API, you can use only one listen port. When the listen SOCKET accepts a connection request from a client, it keeps listening. After accepting the connection request, a new SOCKET is created and the new SOCKET is used in communication with the client.
Following figure shows network flow diagram by Berkeley SOCKET API.

<Berkeley SOCKET API>

But, When you program "TCP SERVER" with WIZnet SOCKET API, you can use as many as 8 listen SOCKET with same port number.
Because there's no accept() in WIZnet SOCKET APIs, when the listen SOCKET accepts a connection request from a client, it is changed in order to communicate with the client. And the changed SOCKET is not listening any more and is dedicated for communicating with the client.
If there're many listen SOCKET with same listen port number and a client requests a connection, the SOCKET which has the smallest SOCKET number accepts the request and is changed as communication SOCKET.
Following figure shows network flow diagram by WIZnet SOCKET API.

<WIZnet SOCKET API>

Function Documentation

int8_t socket | ( | uint8_t | sn,
 |  | uint8_t | protocol,
 |  | uint16_t | port,
 |  | uint8_t | flag
 | ) |  |

Open a socket.

Initializes the socket with 'sn' passed as parameter and open.

Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
protocol | Protocol type to operate such as TCP, UDP and MACRAW.
port | Port number to be bined.
flag Socket flags as SF_ETHER_OWN, SF_IGMP_VER2, SF_TCP_NODELAY, SF_MULTI_ENABLE, SF_IO_NONBLOCK and so on.
Valid flags only in W5500 : SF_BROAD_BLOCK, SF_MULTI_BLOCK, SF_IPv6_BLOCK, and SF_UNI_BLOCK.
See Also
Sn_MR
Returns
Success : The socket number 'sn' passed as parameter
Fail :
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_SOCKMODE - Not support socket mode as TCP, UDP, and so on.
SOCKERR_SOCKFLAG - Invaild socket flag.

Definition at line 94 of file socket.c.

References CHECK_SOCKNUM, close(), getSIPR, getSn_CR, getSn_SR, setSn_CR, setSn_MR, setSn_PORT, SF_IGMP_VER2, SF_IO_NONBLOCK, SF_MULTI_ENABLE, SF_TCP_NODELAY, SF_UNI_BLOCK, Sn_CR_OPEN, Sn_MR_IPRAW, Sn_MR_MACRAW, Sn_MR_PPPoE, Sn_MR_TCP, Sn_MR_UDP, SOCK_ANY_PORT_NUM, SOCK_CLOSED, SOCKERR_SOCKFLAG, SOCKERR_SOCKINIT, and SOCKERR_SOCKMODE.

int8_t close ( uint8_t sn)

Close a socket.

It closes the socket with 'sn' passed as parameter.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
Success : SOCK_OK
Fail : SOCKERR_SOCKNUM - Invalid socket number

Definition at line 165 of file socket.c.

References CHECK_SOCKNUM, getSn_CR, getSn_SR, setSn_CR, setSn_IR, Sn_CR_CLOSE, SOCK_CLOSED, and SOCK_OK.

Referenced by disconnect(), listen(), recv(), recvfrom(), send(), and socket().

int8_t listen ( uint8_t sn)

Listen to a connection request from a client.

It is listening to a connection request from a client. If connection request is accepted successfully, the connection is established. Socket sn is used in passive(server) mode.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
Success : SOCK_OK
Fail :
SOCKERR_SOCKINIT - Socket is not initialized
SOCKERR_SOCKCLOSED - Socket closed unexpectedly.

Definition at line 184 of file socket.c.

References CHECK_SOCKINIT, CHECK_SOCKMODE, CHECK_SOCKNUM, close(), getSn_CR, getSn_SR, setSn_CR, Sn_CR_LISTEN, Sn_MR_TCP, SOCK_CLOSED, SOCK_LISTEN, SOCK_OK, and SOCKERR_SOCKCLOSED.

int8_t connect | ( | uint8_t | sn,
 |  | uint8_t * | addr,
 |  | uint16_t | port
 | ) |  |

Try to connect a server.

It requests connection to the server with destination IP address and port number passed as parameter.

Note
It is valid only in TCP client mode. In block io mode, it does not return until connection is completed. In Non-block io mode, it return SOCK_BUSY immediately.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
addr | Pointer variable of destination IP address. It should be allocated 4 bytes.
port | Destination port number.
Returns
Success : SOCK_OK
Fail :
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_SOCKMODE - Invalid socket mode
SOCKERR_SOCKINIT - Socket is not initialized
SOCKERR_IPINVALID - Wrong server IP address
SOCKERR_PORTZERO - Server port zero
SOCKERR_TIMEOUT - Timeout occurred during request connection
SOCK_BUSY - In non-block io mode, it returned immediately

Definition at line 203 of file socket.c.

References CHECK_SOCKINIT, CHECK_SOCKMODE, CHECK_SOCKNUM, getSn_CR, getSn_IR, getSn_SR, setSn_CR, setSn_DIPR, setSn_DPORT, setSn_IR, Sn_CR_CONNECT, Sn_IR_TIMEOUT, Sn_MR_TCP, SOCK_BUSY, SOCK_CLOSED, SOCK_ESTABLISHED, SOCK_OK, SOCKERR_IPINVALID, SOCKERR_PORTZERO, SOCKERR_SOCKCLOSED, and SOCKERR_TIMEOUT.

int8_t disconnect ( uint8_t sn)

Try to disconnect a connection socket.

It sends request message to disconnect the TCP socket 'sn' passed as parameter to the server or client.

Note
It is valid only in TCP server or client mode.
In block io mode, it does not return until disconnection is completed.
In Non-block io mode, it return SOCK_BUSY immediately.
Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
Success : SOCK_OK
Fail :
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_SOCKMODE - Invalid operation in the socket
SOCKERR_TIMEOUT - Timeout occurred
SOCK_BUSY - Socket is busy.

Definition at line 243 of file socket.c.

References CHECK_SOCKMODE, CHECK_SOCKNUM, close(), getSn_CR, getSn_IR, getSn_SR, setSn_CR, Sn_CR_DISCON, Sn_IR_TIMEOUT, Sn_MR_TCP, SOCK_BUSY, SOCK_CLOSED, SOCK_OK, and SOCKERR_TIMEOUT.

int32_t send | ( | uint8_t | sn,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

Send data to the connected peer in TCP socket.

It is used to send outgoing data to the connected socket.

Note
It is valid only in TCP server or client mode. It can't send data greater than socket buffer size.
In block io mode, It doesn't return until data send is completed - socket buffer size is greater than data.
In non-block io mode, It return SOCK_BUSY immediately when socket buffer is not enough.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
buf | Pointer buffer containing data to be sent.
len | The byte length of data in buf.
Returns
Success : The sent data size
Fail :
SOCKERR_SOCKSTATUS - Invalid socket status for socket operation
SOCKERR_TIMEOUT - Timeout occurred
SOCKERR_SOCKMODE - Invalid operation in the socket
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_DATALEN - zero data length
SOCK_BUSY - Socket is busy.

Definition at line 263 of file socket.c.

References CHECK_SOCKDATA, CHECK_SOCKMODE, CHECK_SOCKNUM, close(), getSn_CR, getSn_IR, getSn_SR, getSn_TX_FSR(), getSn_TX_RD, getSn_TxMAX, setSn_CR, setSn_IR, Sn_CR_SEND, Sn_IR_SENDOK, Sn_IR_TIMEOUT, Sn_MR_TCP, SOCK_BUSY, SOCK_CLOSE_WAIT, SOCK_ESTABLISHED, SOCKERR_SOCKSTATUS, SOCKERR_TIMEOUT, and wiz_send_data().

int32_t recv | ( | uint8_t | sn,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

Receive data from the connected peer.

It is used to read incoming data from the connected socket.
It waits for data as much as the application wants to receive.

Note
It is valid only in TCP server or client mode. It can't receive data greater than socket buffer size.
In block io mode, it doesn't return until data reception is completed - data is filled as len in socket buffer.
In non-block io mode, it return SOCK_BUSY immediately when len is greater than data size in socket buffer.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
buf | Pointer buffer to read incoming data.
len | The max data length of data in buf.
Returns
Success : The real received data size
Fail :
SOCKERR_SOCKSTATUS - Invalid socket status for socket operation
SOCKERR_SOCKMODE - Invalid operation in the socket
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_DATALEN - zero data length
SOCK_BUSY - Socket is busy.

Definition at line 326 of file socket.c.

References CHECK_SOCKDATA, CHECK_SOCKMODE, CHECK_SOCKNUM, close(), getSn_CR, getSn_RX_RSR(), getSn_RxMAX, getSn_SR, getSn_TX_FSR(), getSn_TxMAX, setSn_CR, Sn_CR_RECV, Sn_MR_TCP, SOCK_BUSY, SOCK_CLOSE_WAIT, SOCK_ESTABLISHED, SOCKERR_SOCKSTATUS, and wiz_recv_data().

int32_t sendto | ( | uint8_t | sn,
 |  | uint8_t * | buf,
 |  | uint16_t | len,
 |  | uint8_t * | addr,
 |  | uint16_t | port
 | ) |  |

Sends datagram to the peer with destination IP address and port number passed as parameter.

It sends datagram of UDP or MACRAW to the peer with destination IP address and port number passed as parameter.
Even if the connectionless socket has been previously connected to a specific address, the address and port number parameters override the destination address for that particular datagram only.

Note
In block io mode, It doesn't return until data send is completed - socket buffer size is greater than len. In non-block io mode, It return SOCK_BUSY immediately when socket buffer is not enough.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
buf | Pointer buffer to send outgoing data.
len | The byte length of data in buf.
addr | Pointer variable of destination IP address. It should be allocated 4 bytes.
port | Destination port number.
Returns
Success : The sent data size
Fail :
SOCKERR_SOCKNUM - Invalid socket number
SOCKERR_SOCKMODE - Invalid operation in the socket
SOCKERR_SOCKSTATUS - Invalid socket status for socket operation
SOCKERR_DATALEN - zero data length
SOCKERR_IPINVALID - Wrong server IP address
SOCKERR_PORTZERO - Server port zero
SOCKERR_SOCKCLOSED - Socket unexpectedly closed
SOCKERR_TIMEOUT - Timeout occurred
SOCK_BUSY - Socket is busy.

Definition at line 369 of file socket.c.

References CHECK_SOCKDATA, CHECK_SOCKNUM, getSIPR, getSn_CR, getSn_IR, getSn_MR, getSn_SR, getSn_TX_FSR(), getSn_TxMAX, getSUBR, setSn_CR, setSn_DIPR, setSn_DPORT, setSn_IR, setSUBR, Sn_CR_SEND, Sn_IR_SENDOK, Sn_IR_TIMEOUT, Sn_MR_MACRAW, Sn_MR_UDP, SOCK_BUSY, SOCK_CLOSED, SOCK_MACRAW, SOCK_UDP, SOCKERR_IPINVALID, SOCKERR_PORTZERO, SOCKERR_SOCKCLOSED, SOCKERR_SOCKMODE, SOCKERR_SOCKSTATUS, SOCKERR_TIMEOUT, and wiz_send_data().

int32_t recvfrom | ( | uint8_t | sn,
 |  | uint8_t * | buf,
 |  | uint16_t | len,
 |  | uint8_t * | addr,
 |  | uint16_t * | port
 | ) |  |

Receive datagram of UDP or MACRAW.

This function is an application I/F function which is used to receive the data in other then TCP mode.
This function is used to receive UDP and MAC_RAW mode, and handle the header as well. This function can divide to received the packet data. On the MACRAW SOCKET, the addr and port parameters are ignored.

Note
In block io mode, it doesn't return until data reception is completed - data is filled as len in socket buffer In non-block io mode, it return SOCK_BUSY immediately when len is greater than data size in socket buffer.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
buf | Pointer buffer to read incoming data.
len | The max data length of data in buf. When the received packet size <= len, receives data as packet sized. When others, receives data as len.
addr | Pointer variable of destination IP address. It should be allocated 4 bytes. It is valid only when the first call recvfrom for receiving the packet. When it is valid, packinfo[7] should be set as '1' after call getsockopt(sn, SO_PACKINFO, &packinfo).
port | Pointer variable of destination port number. It is valid only when the first call recvform for receiving the packet. When it is valid, packinfo[7] should be set as '1' after call getsockopt(sn, SO_PACKINFO, &packinfo).
Returns
Success : This function return real received data size for success.
Fail : SOCKERR_DATALEN - zero data length
SOCKERR_SOCKMODE - Invalid operation in the socket
SOCKERR_SOCKNUM - Invalid socket number
SOCKBUSY - Socket is busy.

Definition at line 460 of file socket.c.

References CHECK_SOCKDATA, CHECK_SOCKNUM, close(), getSn_CR, getSn_MR, getSn_RX_RSR(), getSn_SR, PACK_COMPLETED, PACK_FIRST, PACK_REMAINED, setSn_CR, Sn_CR_RECV, Sn_MR_IPRAW, Sn_MR_MACRAW, Sn_MR_PPPoE, Sn_MR_UDP, SOCK_BUSY, SOCK_CLOSED, SOCKERR_SOCKCLOSED, SOCKERR_SOCKMODE, SOCKFATAL_PACKLEN, wiz_recv_data(), and wiz_recv_ignore().

int8_t ctlsocket | ( | uint8_t | sn,
 |  | ctlsock_type | cstype,
 |  | void * | arg
 | ) |  |

Control socket.

Control IO mode, Interrupt & Mask of socket and get the socket buffer information. Refer to ctlsock_type.

Parameters
sn | socket number
cstype | type of control socket. refer to ctlsock_type.
arg Data type and value is determined according to ctlsock_type.
cstype data type value
CS_SET_IOMODE
CS_GET_IOMODE 		uint8_t SOCK_IO_BLOCK SOCK_IO_NONBLOCK
CS_GET_MAXTXBUF
CS_GET_MAXRXBUF 		uint16_t 0 ~ 16K
CS_CLR_INTERRUPT
CS_GET_INTERRUPT
CS_SET_INTMASK
CS_GET_INTMASK 		sockint_kind SIK_CONNECTED, etc.
Returns
Success SOCK_OK
fail SOCKERR_ARG - Invalid argument

Definition at line 583 of file socket.c.

References CHECK_SOCKNUM, CS_CLR_INTERRUPT, CS_GET_INTERRUPT, CS_GET_INTMASK, CS_GET_IOMODE, CS_GET_MAXRXBUF, CS_GET_MAXTXBUF, CS_SET_INTMASK, CS_SET_IOMODE, getSn_IMR, getSn_IR, getSn_RxMAX, getSn_TxMAX, setSn_IMR, setSn_IR, SIK_ALL, SOCK_IO_BLOCK, SOCK_IO_NONBLOCK, SOCK_OK, and SOCKERR_ARG.

int8_t setsockopt | ( | uint8_t | sn,
 |  | sockopt_type | sotype,
 |  | void * | arg
 | ) |  |

set socket options

Set socket option like as TTL, MSS, TOS, and so on. Refer to sockopt_type.

Parameters
sn | socket number
sotype | socket option type. refer to sockopt_type
arg Data type and value is determined according to sotype.
sotype | data type | value
SO_TTL | uint8_t | 0 ~ 255
SO_TOS | uint8_t | 0 ~ 255
SO_MSS | uint16_t | 0 ~ 65535
SO_DESTIP | uint8_t[4]
SO_DESTPORT | uint16_t | 0 ~ 65535
SO_KEEPALIVESEND | null | null
SO_KEEPALIVEAUTO | uint8_t | 0 ~ 255
Returns
  • Success : SOCK_OK
  • Fail
    • SOCKERR_SOCKNUM - Invalid Socket number
    • SOCKERR_SOCKMODE - Invalid socket mode
    • SOCKERR_SOCKOPT - Invalid socket option or its value
    • SOCKERR_TIMEOUT - Timeout occurred when sending keep-alive packet

Definition at line 629 of file socket.c.

References CHECK_SOCKMODE, CHECK_SOCKNUM, getSn_CR, getSn_IR, getSn_KPALVTR, setSn_CR, setSn_DIPR, setSn_DPORT, setSn_IR, setSn_KPALVTR, setSn_MSSR, setSn_TOS, setSn_TTL, Sn_CR_SEND_KEEP, Sn_IR_TIMEOUT, Sn_MR_TCP, SO_DESTIP, SO_DESTPORT, SO_KEEPALIVEAUTO, SO_KEEPALIVESEND, SO_MSS, SO_TOS, SO_TTL, SOCK_OK, SOCKERR_ARG, SOCKERR_SOCKOPT, and SOCKERR_TIMEOUT.

int8_t getsockopt | ( | uint8_t | sn,
 |  | sockopt_type | sotype,
 |  | void * | arg
 | ) |  |

get socket options

Get socket option like as FLAG, TTL, MSS, and so on. Refer to sockopt_type

Parameters
sn | socket number
sotype | socket option type. refer to sockopt_type
arg Data type and value is determined according to sotype.
sotype | data type | value
SO_FLAG | uint8_t | SF_ETHER_OWN, etc...
SO_TOS | uint8_t | 0 ~ 255
SO_MSS | uint16_t | 0 ~ 65535
SO_DESTIP | uint8_t[4]
SO_DESTPORT | uint16_t
SO_KEEPALIVEAUTO | uint8_t | 0 ~ 255
SO_SENDBUF | uint16_t | 0 ~ 65535
SO_RECVBUF | uint16_t | 0 ~ 65535
SO_STATUS | uint8_t | SOCK_ESTABLISHED, etc..
SO_REMAINSIZE | uint16_t | 0~ 65535
SO_PACKINFO | uint8_t | PACK_FIRST, etc...
Returns
  • Success : SOCK_OK
  • Fail
    • SOCKERR_SOCKNUM - Invalid Socket number
    • SOCKERR_SOCKOPT - Invalid socket option or its value
    • SOCKERR_SOCKMODE - Invalid socket mode
Note
The option as PACK_REMAINED and SO_PACKINFO is valid only in NON-TCP mode and after call recvfrom().
When SO_PACKINFO value is PACK_FIRST and the return value of recvfrom() is zero, This means the zero byte UDP data(UDP Header only) received.

Definition at line 682 of file socket.c.

References CHECK_SOCKMODE, CHECK_SOCKNUM, getSn_DIPR, getSn_DPORT, getSn_KPALVTR, getSn_MR, getSn_MSSR, getSn_RX_RSR(), getSn_SR, getSn_TOS, getSn_TTL, getSn_TX_FSR(), Sn_MR_TCP, SO_DESTIP, SO_DESTPORT, SO_FLAG, SO_KEEPALIVEAUTO, SO_MSS, SO_PACKINFO, SO_RECVBUF, SO_REMAINSIZE, SO_SENDBUF, SO_STATUS, SO_TOS, SO_TTL, SOCK_OK, and SOCKERR_SOCKOPT.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: 2. WIZnet Extra Functions

Functions
2. WIZnet Extra Functions

These functions is optional function. It could be replaced at WIZCHIP I/O function because they were made by WIZCHIP I/O functions. More...

Functions

int8_t | ctlwizchip (ctlwizchip_type cwtype, void *arg)
Controls to the WIZCHIP. More...
int8_t | ctlnetwork (ctlnetwork_type cntype, void *arg)
Controls to network. More...
void | wizchip_sw_reset (void)
Reset WIZCHIP by softly. More...
int8_t | wizchip_init (uint8_t *txsize, uint8_t *rxsize)
Initializes WIZCHIP with socket buffer size. More...
void | wizchip_clrinterrupt (intr_kind intr)
Clear Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterrupt (void)
Get Interrupt of WIZCHIP. More...
void | wizchip_setinterruptmask (intr_kind intr)
Mask or Unmask Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterruptmask (void)
Get Interrupt mask of WIZCHIP. More...
void | wizphy_setphyconf (wiz_PhyConf *phyconf)
Set the phy information for WIZCHIP without power mode. More...
void | wizphy_getphyconf (wiz_PhyConf *phyconf)
Get phy configuration information. More...
void | wizphy_getphystat (wiz_PhyConf *phyconf)
Get phy status. More...
int8_t | wizphy_setphypmode (uint8_t pmode)
set the power mode of phy inside WIZCHIP. Refer to PHYCFGR in W5500, PHYSTATUS in W5200 More...
void | wizchip_setnetinfo (wiz_NetInfo *pnetinfo)
Set the network information for WIZCHIP. More...
void | wizchip_getnetinfo (wiz_NetInfo *pnetinfo)
Get the network information for WIZCHIP. More...
int8_t | wizchip_setnetmode (netmode_type netmode)
Set the network mode such WOL, PPPoE, Ping Block, and etc. More...
netmode_type | wizchip_getnetmode (void)
Get the network mode such WOL, PPPoE, Ping Block, and etc. More...
void | wizchip_settimeout (wiz_NetTimeout *nettime)
Set retry time value(RTR) and retry count(RCR). More...
void | wizchip_gettimeout (wiz_NetTimeout *nettime)
Get retry time value(RTR) and retry count(RCR). More...

Detailed Description

These functions is optional function. It could be replaced at WIZCHIP I/O function because they were made by WIZCHIP I/O functions.

There are functions of configuring WIZCHIP, network, interrupt, phy, network information and timer.

Function Documentation

int8_t ctlwizchip | ( | ctlwizchip_type | cwtype,
 |  | void * | arg
 | ) |  |

Controls to the WIZCHIP.

Resets WIZCHIP & internal PHY, Configures PHY mode, Monitor PHY(Link,Speed,Half/Full/Auto), controls interrupt & mask and so on.

Parameters
cwtype | : Decides to the control type
arg | : arg type is dependent on cwtype.
Returns
0 : Success
-1 : Fail because of invalid ctlwizchip_type or unsupported ctlwizchip_type in WIZCHIP

Definition at line 263 of file wizchip_conf.c.

References _WIZCHIP_SOCK_NUM_, CW_CLR_INTERRUPT, CW_GET_ID, CW_GET_INTERRUPT, CW_GET_INTRMASK, CW_GET_INTRTIME, CW_GET_PHYCONF, CW_GET_PHYLINK, CW_GET_PHYPOWMODE, CW_GET_PHYSTATUS, CW_INIT_WIZCHIP, CW_RESET_PHY, CW_RESET_WIZCHIP, CW_SET_INTRMASK, CW_SET_INTRTIME, CW_SET_PHYCONF, CW_SET_PHYPOWMODE, getINTLEVEL, __WIZCHIP::id, setINTLEVEL, wizchip_clrinterrupt(), wizchip_getinterrupt(), wizchip_getinterruptmask(), wizchip_init(), wizchip_setinterruptmask(), wizchip_sw_reset(), wizphy_getphyconf(), wizphy_getphylink(), wizphy_getphypmode(), wizphy_reset(), wizphy_setphyconf(), and wizphy_setphypmode().

int8_t ctlnetwork | ( | ctlnetwork_type | cntype,
 |  | void * | arg
 | ) |  |

Controls to network.

Controls to network environment, mode, timeout and so on.

Parameters
cntype | : Input. Decides to the control type
arg | : Inout. arg type is dependent on cntype.
Returns
-1 : Fail because of invalid ctlnetwork_type or unsupported ctlnetwork_type in WIZCHIP
0 : Success

Definition at line 343 of file wizchip_conf.c.

References CN_GET_NETINFO, CN_GET_NETMODE, CN_GET_TIMEOUT, CN_SET_NETINFO, CN_SET_NETMODE, CN_SET_TIMEOUT, wizchip_getnetinfo(), wizchip_getnetmode(), wizchip_gettimeout(), wizchip_setnetinfo(), wizchip_setnetmode(), and wizchip_settimeout().

void wizchip_sw_reset ( void )

Reset WIZCHIP by softly.

Definition at line 371 of file wizchip_conf.c.

References getGAR, getMR, getSHAR, getSIPR, getSUBR, MR_RST, setGAR, setMR, setSHAR, setSIPR, and setSUBR.

Referenced by ctlwizchip(), and wizchip_init().

int8_t wizchip_init | ( | uint8_t * | txsize,
 |  | uint8_t * | rxsize
 | ) |  |

Initializes WIZCHIP with socket buffer size.

Parameters
txsize | Socket tx buffer sizes. If null, initialized the default size 2KB.
rxsize | Socket rx buffer sizes. If null, initialized the default size 2KB.
Returns
0 : succcess
-1 : fail. Invalid buffer size

Definition at line 385 of file wizchip_conf.c.

References _WIZCHIP_SOCK_NUM_, setSn_RXBUF_SIZE, setSn_TXBUF_SIZE, and wizchip_sw_reset().

Referenced by ctlwizchip().

void wizchip_clrinterrupt ( intr_kind intr)

Clear Interrupt of WIZCHIP.

Parameters
intr : intr_kind value operated OR. It can type-cast to uint16_t.

Definition at line 411 of file wizchip_conf.c.

References setIR, and setSIR.

Referenced by ctlwizchip().

intr_kind wizchip_getinterrupt ( void )

Get Interrupt of WIZCHIP.

Returns
intr_kind value operated OR. It can type-cast to uint16_t.

Definition at line 435 of file wizchip_conf.c.

References getIR, and getSIR.

Referenced by ctlwizchip().

void wizchip_setinterruptmask ( intr_kind intr)

Mask or Unmask Interrupt of WIZCHIP.

Parameters
intr : intr_kind value operated OR. It can type-cast to uint16_t.

Definition at line 459 of file wizchip_conf.c.

References setIMR, and setSIMR.

Referenced by ctlwizchip().

intr_kind wizchip_getinterruptmask ( void )

Get Interrupt mask of WIZCHIP.

Returns
: The operated OR vaule of intr_kind. It can type-cast to uint16_t.

Definition at line 480 of file wizchip_conf.c.

References getIMR, and getSIMR.

Referenced by ctlwizchip().

void wizphy_setphyconf ( wiz_PhyConf * phyconf)

Set the phy information for WIZCHIP without power mode.

Parameters
phyconf : wiz_PhyConf

Definition at line 556 of file wizchip_conf.c.

References wiz_PhyConf_t::by, wiz_PhyConf_t::duplex, wiz_PhyConf_t::mode, PHY_CONFBY_SW, PHY_DUPLEX_FULL, PHY_MODE_AUTONEGO, PHY_SPEED_100, PHYCFGR_OPMD, PHYCFGR_OPMDC_100F, PHYCFGR_OPMDC_100H, PHYCFGR_OPMDC_10F, PHYCFGR_OPMDC_10H, PHYCFGR_OPMDC_ALLA, setPHYCFGR, wiz_PhyConf_t::speed, and wizphy_reset().

Referenced by ctlwizchip().

void wizphy_getphyconf ( wiz_PhyConf * phyconf)

Get phy configuration information.

Parameters
phyconf : wiz_PhyConf

Definition at line 586 of file wizchip_conf.c.

References wiz_PhyConf_t::by, wiz_PhyConf_t::duplex, getPHYCFGR, wiz_PhyConf_t::mode, PHY_CONFBY_HW, PHY_CONFBY_SW, PHY_DUPLEX_FULL, PHY_DUPLEX_HALF, PHY_MODE_AUTONEGO, PHY_MODE_MANUAL, PHY_SPEED_10, PHY_SPEED_100, PHYCFGR_OPMD, PHYCFGR_OPMDC_100F, PHYCFGR_OPMDC_100FA, PHYCFGR_OPMDC_100H, PHYCFGR_OPMDC_10F, PHYCFGR_OPMDC_ALLA, and wiz_PhyConf_t::speed.

Referenced by ctlwizchip().

void wizphy_getphystat ( wiz_PhyConf * phyconf)

Get phy status.

Parameters
phyconf : wiz_PhyConf

Definition at line 625 of file wizchip_conf.c.

References wiz_PhyConf_t::duplex, getPHYCFGR, PHY_DUPLEX_FULL, PHY_DUPLEX_HALF, PHY_SPEED_10, PHY_SPEED_100, PHYCFGR_DPX_FULL, PHYCFGR_SPD_100, and wiz_PhyConf_t::speed.

int8_t wizphy_setphypmode ( uint8_t pmode)

set the power mode of phy inside WIZCHIP. Refer to PHYCFGR in W5500, PHYSTATUS in W5200

Parameters
pmode Settig value of power down mode.

Definition at line 632 of file wizchip_conf.c.

References getPHYCFGR, PHY_POWER_DOWN, PHYCFGR_OPMD, PHYCFGR_OPMDC_ALLA, PHYCFGR_OPMDC_PDOWN, setPHYCFGR, and wizphy_reset().

Referenced by ctlwizchip().

void wizchip_setnetinfo ( wiz_NetInfo * pnetinfo)

Set the network information for WIZCHIP.

Parameters
pnetinfo : wizNetInfo

Definition at line 658 of file wizchip_conf.c.

References wiz_NetInfo_t::dhcp, wiz_NetInfo_t::dns, wiz_NetInfo_t::gw, wiz_NetInfo_t::ip, wiz_NetInfo_t::mac, setGAR, setSHAR, setSIPR, setSUBR, and wiz_NetInfo_t::sn.

Referenced by ctlnetwork().

void wizchip_getnetinfo ( wiz_NetInfo * pnetinfo)

Get the network information for WIZCHIP.

Parameters
pnetinfo : wizNetInfo

Definition at line 671 of file wizchip_conf.c.

References wiz_NetInfo_t::dhcp, wiz_NetInfo_t::dns, getGAR, getSHAR, getSIPR, getSUBR, wiz_NetInfo_t::gw, wiz_NetInfo_t::ip, wiz_NetInfo_t::mac, and wiz_NetInfo_t::sn.

Referenced by ctlnetwork().

int8_t wizchip_setnetmode ( netmode_type netmode)

Set the network mode such WOL, PPPoE, Ping Block, and etc.

Parameters
pnetinfo Value of network mode. Refer to netmode_type.

Definition at line 684 of file wizchip_conf.c.

References getMR, NM_FORCEARP, NM_PINGBLOCK, NM_PPPOE, NM_WAKEONLAN, and setMR.

Referenced by ctlnetwork().

netmode_type wizchip_getnetmode ( void )

Get the network mode such WOL, PPPoE, Ping Block, and etc.

Returns
Value of network mode. Refer to netmode_type.

Definition at line 698 of file wizchip_conf.c.

References getMR.

Referenced by ctlnetwork().

void wizchip_settimeout ( wiz_NetTimeout * nettime)

Set retry time value(RTR) and retry count(RCR).

RTR configures the retransmission timeout period and RCR configures the number of time of retransmission.

Parameters
nettime RTR value and RCR value. Refer to wiz_NetTimeout.

Definition at line 703 of file wizchip_conf.c.

References wiz_NetTimeout_t::retry_cnt, setRCR, setRTR, and wiz_NetTimeout_t::time_100us.

Referenced by ctlnetwork().

void wizchip_gettimeout ( wiz_NetTimeout * nettime)

Get retry time value(RTR) and retry count(RCR).

RTR configures the retransmission timeout period and RCR configures the number of time of retransmission.

Parameters
nettime RTR value and RCR value. Refer to wiz_NetTimeout.

Definition at line 709 of file wizchip_conf.c.

References getRCR, getRTR, wiz_NetTimeout_t::retry_cnt, and wiz_NetTimeout_t::time_100us.

Referenced by ctlnetwork().

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: DATA TYPE

Classes | Typedefs | Enumerations
DATA TYPE

Classes

struct | __WIZCHIP
The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions. More...
struct | wiz_PhyConf_t
struct | wiz_NetInfo_t
struct | wiz_NetTimeout_t

Typedefs

typedef struct __WIZCHIP | _WIZCHIP
The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions. More...
typedef struct wiz_PhyConf_t | wiz_PhyConf
typedef struct wiz_NetInfo_t | wiz_NetInfo
typedef struct wiz_NetTimeout_t | wiz_NetTimeout

Enumerations

enum sockint_kind {
SIK_CONNECTED = (1 << 0), SIK_DISCONNECTED = (1 << 1), SIK_RECEIVED = (1 << 2), SIK_TIMEOUT = (1 << 3),
SIK_SENT = (1 << 4), SIK_ALL = 0x1F
}
The kind of Socket Interrupt. More...
enum ctlsock_type {
CS_SET_IOMODE, CS_GET_IOMODE, CS_GET_MAXTXBUF, CS_GET_MAXRXBUF,
CS_CLR_INTERRUPT, CS_GET_INTERRUPT, CS_SET_INTMASK, CS_GET_INTMASK
}
The type of ctlsocket(). More...
enum sockopt_type {
SO_FLAG, SO_TTL, SO_TOS, SO_MSS,
SO_DESTIP, SO_DESTPORT, SO_KEEPALIVESEND, SO_KEEPALIVEAUTO,
SO_SENDBUF, SO_RECVBUF, SO_STATUS, SO_REMAINSIZE,
SO_PACKINFO
}
The type of socket option in setsockopt() or getsockopt() More...
enum ctlwizchip_type {
CW_RESET_WIZCHIP, CW_INIT_WIZCHIP, CW_GET_INTERRUPT, CW_CLR_INTERRUPT,
CW_SET_INTRMASK, CW_GET_INTRMASK, CW_SET_INTRTIME, CW_GET_INTRTIME,
CW_GET_ID, CW_RESET_PHY, CW_SET_PHYCONF, CW_GET_PHYCONF,
CW_GET_PHYSTATUS, CW_SET_PHYPOWMODE, CW_GET_PHYPOWMODE, CW_GET_PHYLINK
}
enum ctlnetwork_type {
CN_SET_NETINFO, CN_GET_NETINFO, CN_SET_NETMODE, CN_GET_NETMODE,
CN_SET_TIMEOUT, CN_GET_TIMEOUT
}
enum intr_kind {
IK_WOL = (1 << 4), IK_PPPOE_TERMINATED = (1 << 5), IK_DEST_UNREACH = (1 << 6), IK_IP_CONFLICT = (1 << 7),
IK_SOCK_0 = (1 << 8), IK_SOCK_1 = (1 << 9), IK_SOCK_2 = (1 << 10), IK_SOCK_3 = (1 << 11),
IK_SOCK_4 = (1 << 12), IK_SOCK_5 = (1 << 13), IK_SOCK_6 = (1 << 14), IK_SOCK_7 = (1 << 15),
IK_SOCK_ALL = (0xFF << 8)
}
enum | dhcp_mode { NETINFO_STATIC = 1, NETINFO_DHCP }
enum | netmode_type { NM_FORCEARP = (1<<1), NM_WAKEONLAN = (1<<5), NM_PINGBLOCK = (1<<4), NM_PPPOE = (1<<3) }

Detailed Description

Typedef Documentation

typedef struct __WIZCHIP _WIZCHIP

The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions.

typedef struct wiz_PhyConf_t wiz_PhyConf

It configures PHY configuration when CW_SET PHYCONF or CW_GET_PHYCONF in W5500, and it indicates the real PHY status configured by HW or SW in all WIZCHIP.
Valid only in W5500.

typedef struct wiz_NetInfo_t wiz_NetInfo

Network Information for WIZCHIP

typedef struct wiz_NetTimeout_t wiz_NetTimeout

Used in CN_SET_TIMEOUT or CN_GET_TIMEOUT of ctlwizchip() for timeout configruation.

Enumeration Type Documentation

enum sockint_kind

The kind of Socket Interrupt.

See Also
Sn_IR, Sn_IMR, setSn_IR(), getSn_IR(), setSn_IMR(), getSn_IMR()
Enumerator
SIK_CONNECTED | connected
SIK_DISCONNECTED | disconnected
SIK_RECEIVED | data received
SIK_TIMEOUT | timeout occurred
SIK_SENT | send ok
SIK_ALL | all interrupt

Definition at line 337 of file socket.h.

enum ctlsock_type

The type of ctlsocket().

Enumerator
CS_SET_IOMODE | set socket IO mode with SOCK_IO_BLOCK or SOCK_IO_NONBLOCK
CS_GET_IOMODE | get socket IO mode
CS_GET_MAXTXBUF | get the size of socket buffer allocated in TX memory
CS_GET_MAXRXBUF | get the size of socket buffer allocated in RX memory
CS_CLR_INTERRUPT | clear the interrupt of socket with sockint_kind
CS_GET_INTERRUPT | get the socket interrupt. refer to sockint_kind
CS_SET_INTMASK | set the interrupt mask of socket with sockint_kind, Not supported in W5100
CS_GET_INTMASK | get the masked interrupt of socket. refer to sockint_kind, Not supported in W5100

Definition at line 351 of file socket.h.

enum sockopt_type

The type of socket option in setsockopt() or getsockopt()

Enumerator
SO_FLAG | Valid only in getsockopt(), For set flag of socket refer to flag in socket().
SO_TTL | Set/Get TTL. Sn_TTL ( setSn_TTL(), getSn_TTL() )
SO_TOS | Set/Get TOS. Sn_TOS ( setSn_TOS(), getSn_TOS() )
SO_MSS | Set/Get MSS. Sn_MSSR ( setSn_MSSR(), getSn_MSSR() )
SO_DESTIP | Set/Get the destination IP address. Sn_DIPR ( setSn_DIPR(), getSn_DIPR() )
SO_DESTPORT | Set/Get the destination Port number. Sn_DPORT ( setSn_DPORT(), getSn_DPORT() )
SO_KEEPALIVESEND | Valid only in setsockopt. Manually send keep-alive packet in TCP mode, Not supported in W5100.
SO_KEEPALIVEAUTO | Set/Get keep-alive auto transmission timer in TCP mode, Not supported in W5100, W5200.
SO_SENDBUF | Valid only in getsockopt. Get the free data size of Socekt TX buffer. Sn_TX_FSR, getSn_TX_FSR()
SO_RECVBUF | Valid only in getsockopt. Get the received data size in socket RX buffer. Sn_RX_RSR, getSn_RX_RSR()
SO_STATUS | Valid only in getsockopt. Get the socket status. Sn_SR, getSn_SR()
SO_REMAINSIZE | Valid only in getsockopt. Get the remained packet size in other then TCP mode.
SO_PACKINFO | Valid only in getsockopt. Get the packet information as PACK_FIRST, PACK_REMAINED, and PACK_COMPLETED in other then TCP mode.

Definition at line 370 of file socket.h.

enum ctlwizchip_type

WIZCHIP control type enumration used in ctlwizchip().

Enumerator
CW_RESET_WIZCHIP | Resets WIZCHIP by softly.
CW_INIT_WIZCHIP | Initializes to WIZCHIP with SOCKET buffer size 2 or 1 dimension array typed uint8_t.
CW_GET_INTERRUPT | Get Interrupt status of WIZCHIP.
CW_CLR_INTERRUPT | Clears interrupt.
CW_SET_INTRMASK | Masks interrupt.
CW_GET_INTRMASK | Get interrupt mask.
CW_SET_INTRTIME | Set interval time between the current and next interrupt.
CW_GET_INTRTIME | Set interval time between the current and next interrupt.
CW_GET_ID | Gets WIZCHIP name.
CW_RESET_PHY | Resets internal PHY. Valid Only W5500.
CW_SET_PHYCONF | When PHY configured by internal register, PHY operation mode (Manual/Auto, 10/100, Half/Full). Valid Only W5000.
CW_GET_PHYCONF | Get PHY operation mode in internal register. Valid Only W5500.
CW_GET_PHYSTATUS | Get real PHY status on operating. Valid Only W5500.
CW_SET_PHYPOWMODE | Set PHY power mode as normal and down when PHYSTATUS.OPMD == 1. Valid Only W5500.
CW_GET_PHYPOWMODE | Get PHY Power mode as down or normal, Valid Only W5100, W5200.
CW_GET_PHYLINK | Get PHY Link status, Valid Only W5100, W5200.

Definition at line 213 of file wizchip_conf.h.

enum ctlnetwork_type

Network control type enumration used in ctlnetwork().

Enumerator
CN_SET_NETINFO | Set Network with wiz_NetInfo.
CN_GET_NETINFO | Get Network with wiz_NetInfo.
CN_SET_NETMODE | Set network mode as WOL, PPPoE, Ping Block, and Force ARP mode.
CN_GET_NETMODE | Get network mode as WOL, PPPoE, Ping Block, and Force ARP mode.
CN_SET_TIMEOUT | Set network timeout as retry count and time.
CN_GET_TIMEOUT | Get network timeout as retry count and time.

Definition at line 242 of file wizchip_conf.h.

enum intr_kind

Interrupt kind when CW_SET_INTRRUPT, CW_GET_INTERRUPT, CW_SET_INTRMASK and CW_GET_INTRMASK is used in ctlnetwork(). It can be used with OR operation.

Enumerator
IK_WOL | Wake On Lan by receiving the magic packet. Valid in W500.
IK_PPPOE_TERMINATED | PPPoE Disconnected.
IK_DEST_UNREACH | Destination IP & Port Unreachable, No use in W5200.
IK_IP_CONFLICT | IP conflict occurred.
IK_SOCK_0 | Socket 0 interrupt.
IK_SOCK_1 | Socket 1 interrupt.
IK_SOCK_2 | Socket 2 interrupt.
IK_SOCK_3 | Socket 3 interrupt.
IK_SOCK_4 | Socket 4 interrupt, No use in 5100.
IK_SOCK_5 | Socket 5 interrupt, No use in 5100.
IK_SOCK_6 | Socket 6 interrupt, No use in 5100.
IK_SOCK_7 | Socket 7 interrupt, No use in 5100.
IK_SOCK_ALL | All Socket interrupt.

Definition at line 258 of file wizchip_conf.h.

enum dhcp_mode

It used in setting dhcp_mode of wiz_NetInfo.

Enumerator
NETINFO_STATIC | Static IP configuration by manually.
NETINFO_DHCP | Dynamic IP configruation from a DHCP sever.

Definition at line 328 of file wizchip_conf.h.

enum netmode_type

Network mode

Enumerator
NM_FORCEARP | Force to APP send whenever udp data is sent. Valid only in W5500.
NM_WAKEONLAN | Wake On Lan.
NM_PINGBLOCK | Block ping-request.
NM_PPPOE | PPPoE mode.

Definition at line 352 of file wizchip_conf.h.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: __WIZCHIP Struct Reference

  • Class List
  • Class Index
  • Class Members
Classes | Public Attributes | List of all members
__WIZCHIP Struct Reference
DATA TYPE

The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions. More...

#include <wizchip_conf.h>

Collaboration diagram for __WIZCHIP:
[legend]

Classes

struct | _CRIS
struct | _CS
union | _IF

Public Attributes

uint16_t | if_mode
host interface mode More...
uint8_t | id [6]
WIZCHIP ID such as 5100, 5200, 5500, and so on. More...
struct __WIZCHIP::_CRIS | CRIS
struct __WIZCHIP::_CS | CS
union __WIZCHIP::_IF | IF

Detailed Description

The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions.

Definition at line 159 of file wizchip_conf.h.

Member Data Documentation

uint16_t __WIZCHIP::if_mode

host interface mode

Definition at line 161 of file wizchip_conf.h.

Referenced by reg_wizchip_bus_cbfunc(), reg_wizchip_spi_cbfunc(), and reg_wizchip_spiburst_cbfunc().

uint8_t __WIZCHIP::id[6]

WIZCHIP ID such as 5100, 5200, 5500, and so on.

Definition at line 162 of file wizchip_conf.h.

Referenced by ctlwizchip().

struct __WIZCHIP::_CRIS __WIZCHIP::CRIS

Referenced by reg_wizchip_cris_cbfunc().

struct __WIZCHIP::_CS __WIZCHIP::CS

Referenced by reg_wizchip_cs_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

union __WIZCHIP::_IF __WIZCHIP::IF

Referenced by reg_wizchip_bus_cbfunc(), reg_wizchip_spi_cbfunc(), reg_wizchip_spiburst_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: __WIZCHIP::_CRIS Struct Reference

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _CRIS
Public Attributes | List of all members
__WIZCHIP::_CRIS Struct Reference

#include <wizchip_conf.h>

Public Attributes

void(* | _enter )(void)
crtical section enter More...
void(* | _exit )(void)
critial section exit More...

Detailed Description

The set of critical section callback func.

Definition at line 166 of file wizchip_conf.h.

Member Data Documentation

void(* __WIZCHIP::_CRIS::_enter)(void)

crtical section enter

Definition at line 168 of file wizchip_conf.h.

Referenced by reg_wizchip_cris_cbfunc().

void(* __WIZCHIP::_CRIS::_exit)(void)

critial section exit

Definition at line 169 of file wizchip_conf.h.

Referenced by reg_wizchip_cris_cbfunc().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: __WIZCHIP::_CS Struct Reference

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _CS
Public Attributes | List of all members
__WIZCHIP::_CS Struct Reference

#include <wizchip_conf.h>

Public Attributes

void(* | _select )(void)
_WIZCHIP_ selected More...
void(* | _deselect )(void)
_WIZCHIP_ deselected More...

Detailed Description

The set of select control callback func.

Definition at line 174 of file wizchip_conf.h.

Member Data Documentation

void(* __WIZCHIP::_CS::_select)(void)

_WIZCHIP_ selected

Definition at line 176 of file wizchip_conf.h.

Referenced by reg_wizchip_cs_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

void(* __WIZCHIP::_CS::_deselect)(void)

_WIZCHIP_ deselected

Definition at line 177 of file wizchip_conf.h.

Referenced by reg_wizchip_cs_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: __WIZCHIP::_IF Union Reference

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _IF
Public Attributes | List of all members
__WIZCHIP::_IF Union Reference

#include <wizchip_conf.h>

Public Attributes

struct {
uint8_t(* _read_byte )(uint32_t AddrSel)
void(* _write_byte )(uint32_t AddrSel, uint8_t wb)
} BUS
struct {
uint8_t(* _read_byte )(void)
void(* _write_byte )(uint8_t wb)
void(* _read_burst )(uint8_t *pBuf, uint16_t len)
void(* _write_burst )(uint8_t *pBuf, uint16_t len)
} SPI

Detailed Description

The set of interface IO callback func.

Definition at line 182 of file wizchip_conf.h.

Member Data Documentation

uint8_t(* __WIZCHIP::_IF::_read_byte)(void)

Definition at line 189 of file wizchip_conf.h.

Referenced by reg_wizchip_bus_cbfunc(), reg_wizchip_spi_cbfunc(), WIZCHIP_READ(), and WIZCHIP_READ_BUF().

void(* __WIZCHIP::_IF::_write_byte)(uint8_t wb)

Definition at line 190 of file wizchip_conf.h.

Referenced by reg_wizchip_bus_cbfunc(), reg_wizchip_spi_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

struct { ... } __WIZCHIP::_IF::BUS

For BUS interface IO

Referenced by reg_wizchip_bus_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

void(* __WIZCHIP::_IF::_read_burst)(uint8_t *pBuf, uint16_t len)

Definition at line 199 of file wizchip_conf.h.

Referenced by reg_wizchip_spiburst_cbfunc(), WIZCHIP_READ(), and WIZCHIP_READ_BUF().

void(* __WIZCHIP::_IF::_write_burst)(uint8_t *pBuf, uint16_t len)

Definition at line 200 of file wizchip_conf.h.

Referenced by reg_wizchip_spiburst_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

struct { ... } __WIZCHIP::_IF::SPI

For SPI interface IO

Referenced by reg_wizchip_spi_cbfunc(), reg_wizchip_spiburst_cbfunc(), WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

The documentation for this union was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: wiz_PhyConf_t Struct Reference

  • Class List
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Public Attributes | List of all members
wiz_PhyConf_t Struct Reference
DATA TYPE

#include <wizchip_conf.h>

Public Attributes

uint8_t | by
set by PHY_CONFBY_HW or PHY_CONFBY_SW More...
uint8_t | mode
set by PHY_MODE_MANUAL or PHY_MODE_AUTONEGO More...
uint8_t | speed
set by PHY_SPEED_10 or PHY_SPEED_100 More...
uint8_t | duplex
set by PHY_DUPLEX_HALF PHY_DUPLEX_FULL More...

Detailed Description

It configures PHY configuration when CW_SET PHYCONF or CW_GET_PHYCONF in W5500, and it indicates the real PHY status configured by HW or SW in all WIZCHIP.
Valid only in W5500.

Definition at line 313 of file wizchip_conf.h.

Member Data Documentation

uint8_t wiz_PhyConf_t::by

set by PHY_CONFBY_HW or PHY_CONFBY_SW

Definition at line 315 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

uint8_t wiz_PhyConf_t::mode

set by PHY_MODE_MANUAL or PHY_MODE_AUTONEGO

Definition at line 316 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

uint8_t wiz_PhyConf_t::speed

set by PHY_SPEED_10 or PHY_SPEED_100

Definition at line 317 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), wizphy_getphystat(), and wizphy_setphyconf().

uint8_t wiz_PhyConf_t::duplex

set by PHY_DUPLEX_HALF PHY_DUPLEX_FULL

Definition at line 318 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), wizphy_getphystat(), and wizphy_setphyconf().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: wiz_NetInfo_t Struct Reference

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wiz_NetInfo_t Struct Reference
DATA TYPE

#include <wizchip_conf.h>

Public Attributes

uint8_t | mac [6]
Source Mac Address. More...
uint8_t | ip [4]
Source IP Address. More...
uint8_t | sn [4]
Subnet Mask. More...
uint8_t | gw [4]
Gateway IP Address. More...
uint8_t | dns [4]
DNS server IP Address. More...
dhcp_mode dhcp
1 - Static, 2 - DHCP More...

Detailed Description

Network Information for WIZCHIP

Definition at line 338 of file wizchip_conf.h.

Member Data Documentation

uint8_t wiz_NetInfo_t::mac[6]

Source Mac Address.

Definition at line 340 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

uint8_t wiz_NetInfo_t::ip[4]

Source IP Address.

Definition at line 341 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

uint8_t wiz_NetInfo_t::sn[4]

Subnet Mask.

Definition at line 342 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

uint8_t wiz_NetInfo_t::gw[4]

Gateway IP Address.

Definition at line 343 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

uint8_t wiz_NetInfo_t::dns[4]

DNS server IP Address.

Definition at line 344 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

dhcp_mode wiz_NetInfo_t::dhcp

1 - Static, 2 - DHCP

Definition at line 345 of file wizchip_conf.h.

Referenced by wizchip_getnetinfo(), and wizchip_setnetinfo().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: wiz_NetTimeout_t Struct Reference

  • Class List
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wiz_NetTimeout_t Struct Reference
DATA TYPE

#include <wizchip_conf.h>

Public Attributes

uint8_t | retry_cnt
retry count More...
uint16_t | time_100us
time unit 100us More...

Detailed Description

Used in CN_SET_TIMEOUT or CN_GET_TIMEOUT of ctlwizchip() for timeout configruation.

Definition at line 366 of file wizchip_conf.h.

Member Data Documentation

uint8_t wiz_NetTimeout_t::retry_cnt

retry count

Definition at line 368 of file wizchip_conf.h.

Referenced by wizchip_gettimeout(), and wizchip_settimeout().

uint16_t wiz_NetTimeout_t::time_100us

time unit 100us

Definition at line 369 of file wizchip_conf.h.

Referenced by wizchip_gettimeout(), and wizchip_settimeout().

The documentation for this struct was generated from the following file:
  • Ethernet/wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: W5100

Modules
W5100

WHIZCHIP register defines and I/O functions of W5100. More...

Collaboration diagram for W5100:

Modules

WIZCHIP I/O functions
This supports the basic I/O functions for WIZCHIP register.
WIZCHIP register
WIZCHIP register defines register group of W5100 .

Detailed Description

WHIZCHIP register defines and I/O functions of W5100.

  • WIZCHIP register : Common register and Socket register
  • WIZCHIP I/O functions : Basic I/O function, Common register access functions and Socket register
Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP I/O functions

Modules
WIZCHIP I/O functions
W5100

This supports the basic I/O functions for WIZCHIP register. More...

Collaboration diagram for WIZCHIP I/O functions:

Modules

Basic I/O function
These are basic input/output functions to read values from register or write values to register.
Common register access functions
These are functions to access common registers.
Socket register access functions
These are functions to access socket registers.

Detailed Description

This supports the basic I/O functions for WIZCHIP register.

  • Basic I/O function
    WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()

  • Common register access functions
    1. Mode
      getMR(), setMR()
    2. Interrupt
      getIR(), setIR(), getIMR(), setIMR(),
    3. Network Information
      getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
    4. Retransmission
      getRCR(), setRCR(), getRTR(), setRTR()
    5. PPPoE
      getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC()
  • Socket register access functions
    1. SOCKET control
      getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IR(), setSn_IR()
    2. SOCKET information
      getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT() getSn_MSSR(), setSn_MSSR()
    3. SOCKET communication
      getSn_RXMEM_SIZE(), setSn_RXMEM_SIZE(), getSn_TXMEM_SIZE(), setSn_TXMEM_SIZE()
      getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR()
      getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR()
      getSn_TX_FSR(), getSn_RX_RSR()
    4. IP header field
      getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS()
      getSn_TTL(), setSn_TTL()
Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Basic I/O function

Functions
Basic I/O function
WIZCHIP I/O functions

These are basic input/output functions to read values from register or write values to register. More...

Collaboration diagram for Basic I/O function:

Functions

uint8_t | WIZCHIP_READ (uint16_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint16_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

These are basic input/output functions to read values from register or write values to register.

Function Documentation

uint8_t WIZCHIP_READ ( uint16_t AddrSel)

It reads 1 byte value from a register.

Parameters
AddrSel Register address
Returns
The value of register

Definition at line 74 of file w5100.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_IF::_read_byte, __WIZCHIP::_CS::_select, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, and WIZCHIP_CRITICAL_EXIT.

Referenced by getSn_RX_RSR(), getSn_TX_FSR(), WIZCHIP_READ_BUF(), and WIZCHIP_WRITE_BUF().

void WIZCHIP_WRITE | ( | uint16_t | AddrSel,
 |  | uint8_t | wb
 | ) |  |

It writes 1 byte value to a register.

Parameters
AddrSel | Register address
wb | Write data
Returns
void

Definition at line 46 of file w5100.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, and WIZCHIP_CRITICAL_EXIT.

Referenced by WIZCHIP_READ_BUF(), and WIZCHIP_WRITE_BUF().

void WIZCHIP_READ_BUF | ( | uint16_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It reads sequence data from registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to read data
len | Data length

Definition at line 144 of file w5100.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_IF::_read_byte, __WIZCHIP::_CS::_select, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, MR, MR_AI, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, WIZCHIP_CRITICAL_EXIT, WIZCHIP_READ(), and WIZCHIP_WRITE().

Referenced by wiz_recv_data().

void WIZCHIP_WRITE_BUF | ( | uint16_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It writes sequence data to registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to write data
len | Data length

Definition at line 107 of file w5100.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, MR, MR_AI, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, WIZCHIP_CRITICAL_EXIT, WIZCHIP_READ(), and WIZCHIP_WRITE().

Referenced by wiz_send_data().

void wiz_send_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to internal TX memory.

This function reads the Tx write pointer register and after that, it copies the wizdata(pointer buffer) of the length of len(variable) bytes to internal TX memory and updates the Tx write pointer register. This function is being called by send() and sendto() function also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to write data
len | Data length
See Also
wiz_recv_data()

It copies data to internal TX memory.

This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer register. User should read upper byte first and lower byte later to get proper value. And this function is being used for copy the data form application buffer to Transmite buffer of the chip. It calculate the actual physical address where one has to write the data in transmite buffer. Here also take care of the condition while it exceed the Tx memory uper-bound of socket.

Definition at line 254 of file w5100.c.

void wiz_recv_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after that, it copies the received data from internal RX memory to wizdata(pointer variable) of the length of len(variable) bytes. This function is being called by recv() also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to read data
len | Data length
See Also
wiz_send_data()

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after copy the data from receive buffer update the Rx write pointer register. User should read upper byte first and lower byte later to get proper value. It calculate the actual physical address where one has to read the data from Receive buffer. Here also take care of the condition while it exceed the Rx memory uper-bound of socket.

Definition at line 296 of file w5100.c.

void wiz_recv_ignore | ( | uint8_t | sn,
 |  | uint16_t | len
 | ) |  |

It discard the received data in RX memory.

It discards the data of the length of len(variable) bytes in internal RX memory.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
len | Data length

Definition at line 328 of file w5100.c.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register access functions

Macros
Common register access functions
WIZCHIP I/O functions

These are functions to access common registers. More...

Collaboration diagram for Common register access functions:

Macros

#define | setMR(mr) (*((uint8_t*)MR) = mr)
Set Mode Register. More...
#define | getMR() (*(uint8_t*)MR)
Get MR. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set GAR. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get GAR. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR,subr,4)
Set SUBR. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get SUBR. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set SHAR. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get SHAR. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set SIPR. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get SIPR. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xA0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xA0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | setRMSR(rmsr) WIZCHIP_WRITE(RMSR)
Get RMSR register. More...
#define | getRMSR() WIZCHIP_READ()
Get RMSR register. More...
#define | setTMSR(rmsr) WIZCHIP_WRITE(TMSR)
Get TMSR register. More...
#define | getPATR() (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
Get TMSR register. More...
#define | getPPPALGO() WIZCHIP_READ(PPPALGO)
Get PPPALGO register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...

Detailed Description

These are functions to access common registers.

Macro Definition Documentation

#define setMR ( mr) (*((uint8_t*)MR) = mr)

Set Mode Register.

Parameters
(uint8_t)mr The value to be set.
See Also
getMR()

Definition at line 1097 of file w5100.h.

Referenced by wizchip_setnetmode(), and wizchip_sw_reset().

#define getMR ( ) (*(uint8_t*)MR)

Get MR.

Returns
uint8_t. The value of Mode register.
See Also
setMR()

Definition at line 1109 of file w5100.h.

Referenced by wizchip_getnetmode(), wizchip_setnetmode(), and wizchip_sw_reset().

#define setGAR ( gar) WIZCHIP_WRITE_BUF(GAR,gar,4)

Set GAR.

Parameters
(uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
See Also
getGAR()

Definition at line 1118 of file w5100.h.

Referenced by wizchip_setnetinfo(), and wizchip_sw_reset().

#define getGAR ( gar) WIZCHIP_READ_BUF(GAR,gar,4)

Get GAR.

Parameters
(uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
See Also
setGAR()

Definition at line 1127 of file w5100.h.

Referenced by wizchip_getnetinfo(), and wizchip_sw_reset().

#define setSUBR ( subr) WIZCHIP_WRITE_BUF(SUBR,subr,4)

Set SUBR.

Parameters
(uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
Note
If subr is null pointer, set the backup subnet to SUBR.
If subr is 0.0.0.0, back up SUBR and clear it.
Otherwize, set subr to SUBR
See Also
getSUBR()

Definition at line 1139 of file w5100.h.

Referenced by sendto(), wizchip_setnetinfo(), and wizchip_sw_reset().

#define getSUBR ( subr) WIZCHIP_READ_BUF(SUBR, subr, 4)

Get SUBR.

Parameters
(uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
See Also
setSUBR()

Definition at line 1148 of file w5100.h.

Referenced by sendto(), wizchip_getnetinfo(), and wizchip_sw_reset().

#define setSHAR ( shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)

Set SHAR.

Parameters
(uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
See Also
getSHAR()

Definition at line 1157 of file w5100.h.

Referenced by wizchip_setnetinfo(), and wizchip_sw_reset().

#define getSHAR ( shar) WIZCHIP_READ_BUF(SHAR, shar, 6)

Get SHAR.

Parameters
(uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
See Also
setSHAR()

Definition at line 1166 of file w5100.h.

Referenced by wizchip_getnetinfo(), and wizchip_sw_reset().

#define setSIPR ( sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)

Set SIPR.

Parameters
(uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
See Also
getSIPR()

Definition at line 1175 of file w5100.h.

Referenced by wizchip_setnetinfo(), and wizchip_sw_reset().

#define getSIPR ( sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)

Get SIPR.

Parameters
(uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
See Also
setSIPR()

Definition at line 1184 of file w5100.h.

Referenced by sendto(), socket(), wizchip_getnetinfo(), and wizchip_sw_reset().

#define setIR ( ir) WIZCHIP_WRITE(IR, (ir & 0xA0))

Set IR register.

Parameters
(uint8_t)ir Value to set IR register.
See Also
getIR()

Definition at line 1193 of file w5100.h.

Referenced by wizchip_clrinterrupt().

#define getIR ( ) (WIZCHIP_READ(IR) & 0xA0)

Get IR register.

Returns
uint8_t. Value of IR register.
See Also
setIR()

Definition at line 1201 of file w5100.h.

Referenced by wizchip_getinterrupt().

#define setIMR ( imr) WIZCHIP_WRITE(_IMR_, imr)

Set IMR register.

Parameters
(uint8_t)imr Value to set IMR register.
See Also
getIMR()

Definition at line 1210 of file w5100.h.

Referenced by wizchip_setinterruptmask().

#define getIMR ( ) WIZCHIP_READ(_IMR_)

Get IMR register.

Returns
uint8_t. Value of IMR register.
See Also
setIMR()

Definition at line 1219 of file w5100.h.

Referenced by wizchip_getinterruptmask().

#define setRTR ( rtr)
Value:
{\
WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
}

Set RTR register.

Parameters
(uint16_t)rtr Value to set RTR register.
See Also
getRTR()

Definition at line 1228 of file w5100.h.

Referenced by wizchip_settimeout().

#define getRTR ( ) (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))

Get RTR register.

Returns
uint16_t. Value of RTR register.
See Also
setRTR()

Definition at line 1239 of file w5100.h.

Referenced by wizchip_gettimeout().

#define setRCR ( rcr) WIZCHIP_WRITE(_RCR_, rcr)

Set RCR register.

Parameters
(uint8_t)rcr Value to set RCR register.
See Also
getRCR()

Definition at line 1248 of file w5100.h.

Referenced by wizchip_settimeout().

#define getRCR ( ) WIZCHIP_READ(_RCR_)

Get RCR register.

Returns
uint8_t. Value of RCR register.
See Also
setRCR()

Definition at line 1257 of file w5100.h.

Referenced by wizchip_gettimeout().

#define setRMSR ( rmsr) WIZCHIP_WRITE(RMSR)

Get RMSR register.

See Also
getRMSR()

Definition at line 1265 of file w5100.h.

#define getRMSR ( ) WIZCHIP_READ()

Get RMSR register.

Returns
uint8_t. Value of RMSR register.
See Also
setRMSR()

Definition at line 1274 of file w5100.h.

#define setTMSR ( rmsr) WIZCHIP_WRITE(TMSR)

Get TMSR register.

See Also
getTMSR()

Definition at line 1282 of file w5100.h.

#define getPATR ( ) (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))

Get TMSR register.

Returns
uint8_t. Value of TMSR register.
See Also
setTMSR()

Get PATR register

Returns
uint16_t. Value to set PATR register

Definition at line 1298 of file w5100.h.

#define getPPPALGO ( ) WIZCHIP_READ(PPPALGO)

Get PPPALGO register.

Returns
uint8_t. Value to set PPPALGO register

Definition at line 1306 of file w5100.h.

#define setPTIMER ( ptimer) WIZCHIP_WRITE(PTIMER, ptimer)

Set PTIMER register.

Parameters
(uint8_t)ptimer Value to set PTIMER register.
See Also
getPTIMER()

Definition at line 1316 of file w5100.h.

#define getPTIMER ( ) WIZCHIP_READ(PTIMER)

Get PTIMER register.

Returns
uint8_t. Value of PTIMER register.
See Also
setPTIMER()

Definition at line 1325 of file w5100.h.

#define setPMAGIC ( pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)

Set PMAGIC register.

Parameters
(uint8_t)pmagic Value to set PMAGIC register.
See Also
getPMAGIC()

Definition at line 1334 of file w5100.h.

#define getPMAGIC ( ) WIZCHIP_READ(PMAGIC)

Get PMAGIC register.

Returns
uint8_t. Value of PMAGIC register.
See Also
setPMAGIC()

Definition at line 1343 of file w5100.h.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register access functions

Macros | Functions
Socket register access functions
WIZCHIP I/O functions

These are functions to access socket registers. More...

Collaboration diagram for Socket register access functions:

Macros

#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), ir)
Set Sn_IR register. More...
#define | getSn_IR(sn) WIZCHIP_READ(Sn_IR(sn))
Get Sn_IR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_DHAR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_PROTO(sn, proto) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_PROTO register. More...
#define | getSn_PROTO(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_PROTO register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXMEM_SIZE(sn, rxmemsize) WIZCHIP_WRITE(RMSR, (WIZCHIP_READ(RMSR) & ~(0x03 << (2*sn))) | (rxmemsize << (2*sn)))
Set Sn_RXMEM_SIZE register. More...
#define | getSn_RXMEM_SIZE(sn) ((WIZCHIP_READ(RMSR) & (0x03 << (2*sn))) >> (2*sn))
Get Sn_RXMEM_SIZE register. More...
#define | setSn_TXMEM_SIZE(sn, txmemsize) WIZCHIP_WRITE(TMSR, (WIZCHIP_READ(TMSR) & ~(0x03 << (2*sn))) | (txmemsize << (2*sn)))
Set Sn_TXMEM_SIZE register. More...
#define | getSn_TXMEM_SIZE(sn) ((WIZCHIP_READ(TMSR) & (0x03 << (2*sn))) >> (2*sn))
Get Sn_TXMEM_SIZE register. More...
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | setSn_RX_WR(sn, rxwr)
Set Sn_RX_WR register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | getSn_RxMAX(sn) ((uint16_t)(1 << getSn_RXMEM_SIZE(sn)) << 10)
Get the max RX buffer size of socket sn. More...
#define | getSn_TxMAX(sn) ((uint16_t)(1 << getSn_TXMEM_SIZE(sn)) << 10)
Get the max TX buffer size of socket sn. More...
#define | getSn_RxMASK(sn) (getSn_RxMAX(sn) - 1)
Get the mask of socket sn RX buffer. More...
#define | getSn_TxMASK(sn) (getSn_TxMAX(sn) - 1)
Get the mask of socket sn TX buffer. More...

Functions

uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint32_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint32_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...

Detailed Description

These are functions to access socket registers.

Macro Definition Documentation

#define setSn_MR | ( | sn,
 |  | mr
 | ) | WIZCHIP_WRITE(Sn_MR(sn),mr)

Set Sn_MR register.

Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ expect bit 4.
mr | Value to set Sn_MR
See Also
getSn_MR()

Definition at line 1356 of file w5100.h.

Referenced by socket().

#define getSn_MR ( sn) WIZCHIP_READ(Sn_MR(sn))

Get Sn_MR register.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ expect bit 4.
Returns
Value of Sn_MR.
See Also
setSn_MR()

Definition at line 1366 of file w5100.h.

Referenced by getsockopt(), recvfrom(), and sendto().

#define setSn_CR | ( | sn,
 |  | cr
 | ) | WIZCHIP_WRITE(Sn_CR(sn), cr)

Set Sn_CR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)cr | Value to set Sn_CR
See Also
getSn_CR()

Definition at line 1376 of file w5100.h.

Referenced by close(), connect(), disconnect(), listen(), recv(), recvfrom(), send(), sendto(), setsockopt(), and socket().

#define getSn_CR ( sn) WIZCHIP_READ(Sn_CR(sn))

Get Sn_CR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_CR.
See Also
setSn_CR()

Definition at line 1386 of file w5100.h.

Referenced by close(), connect(), disconnect(), listen(), recv(), recvfrom(), send(), sendto(), setsockopt(), and socket().

#define setSn_IR | ( | sn,
 |  | ir
 | ) | WIZCHIP_WRITE(Sn_IR(sn), ir)

Set Sn_IR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)ir | Value to set Sn_IR
See Also
getSn_IR()

Definition at line 1396 of file w5100.h.

Referenced by close(), connect(), ctlsocket(), send(), sendto(), and setsockopt().

#define getSn_IR ( sn) WIZCHIP_READ(Sn_IR(sn))

Get Sn_IR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_IR.
See Also
setSn_IR()

Definition at line 1406 of file w5100.h.

Referenced by connect(), ctlsocket(), disconnect(), send(), sendto(), and setsockopt().

#define getSn_SR ( sn) WIZCHIP_READ(Sn_SR(sn))

Get Sn_SR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_SR.

Definition at line 1415 of file w5100.h.

Referenced by close(), connect(), disconnect(), getsockopt(), listen(), recv(), recvfrom(), send(), sendto(), and socket().

#define setSn_PORT | ( | sn,
 |  | port
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
}

Set Sn_PORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)port | Value to set Sn_PORT.
See Also
getSn_PORT()

Definition at line 1425 of file w5100.h.

Referenced by socket().

#define getSn_PORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))

Get Sn_PORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_PORT.
See Also
setSn_PORT()

Definition at line 1437 of file w5100.h.

#define setSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)

Set Sn_DHAR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dhar | Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
See Also
getSn_DHAR()

Definition at line 1447 of file w5100.h.

#define getSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)

Get Sn_DHAR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dhar | Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
See Also
setSn_DHAR()

Definition at line 1457 of file w5100.h.

#define setSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)

Set Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dipr | Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
See Also
getSn_DIPR()

Definition at line 1467 of file w5100.h.

Referenced by connect(), sendto(), and setsockopt().

#define getSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)

Get Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dipr | Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
See Also
SetSn_DIPR()

Definition at line 1477 of file w5100.h.

Referenced by getsockopt().

#define setSn_DPORT | ( | sn,
 |  | dport
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
}

Set Sn_DPORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)dport | Value to set Sn_DPORT
See Also
getSn_DPORT()

Definition at line 1487 of file w5100.h.

Referenced by connect(), sendto(), and setsockopt().

#define getSn_DPORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))

Get Sn_DPORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_DPORT.
See Also
setSn_DPORT()

Definition at line 1499 of file w5100.h.

Referenced by getsockopt().

#define setSn_MSSR | ( | sn,
 |  | mss
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
}

Set Sn_MSSR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)mss | Value to set Sn_MSSR
See Also
setSn_MSSR()

Definition at line 1509 of file w5100.h.

Referenced by setsockopt().

#define getSn_MSSR ( sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))

Get Sn_MSSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_MSSR.
See Also
setSn_MSSR()

Definition at line 1521 of file w5100.h.

Referenced by getsockopt().

#define setSn_PROTO | ( | sn,
 |  | proto
 | ) | WIZCHIP_WRITE(Sn_TOS(sn), tos)

Set Sn_PROTO register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)proto | Value to set Sn_PROTO
See Also
getSn_PROTO()

Definition at line 1531 of file w5100.h.

#define getSn_PROTO ( sn) WIZCHIP_READ(Sn_TOS(sn))

Get Sn_PROTO register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_PROTO.
See Also
setSn_PROTO()

Definition at line 1541 of file w5100.h.

#define setSn_TOS | ( | sn,
 |  | tos
 | ) | WIZCHIP_WRITE(Sn_TOS(sn), tos)

Set Sn_TOS register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)tos | Value to set Sn_TOS
See Also
getSn_TOS()

Definition at line 1551 of file w5100.h.

Referenced by setsockopt().

#define getSn_TOS ( sn) WIZCHIP_READ(Sn_TOS(sn))

Get Sn_TOS register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
Returns
uint8_t. Value of Sn_TOS.
See Also
setSn_TOS()

Definition at line 1561 of file w5100.h.

Referenced by getsockopt().

#define setSn_TTL | ( | sn,
 |  | ttl
 | ) | WIZCHIP_WRITE(Sn_TTL(sn), ttl)

Set Sn_TTL register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
(uint8_t)ttl | Value to set Sn_TTL
See Also
getSn_TTL()

Definition at line 1571 of file w5100.h.

Referenced by setsockopt().

#define getSn_TTL ( sn) WIZCHIP_READ(Sn_TTL(sn))

Get Sn_TTL register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
Returns
uint8_t. Value of Sn_TTL.
See Also
setSn_TTL()

Definition at line 1581 of file w5100.h.

Referenced by getsockopt().

#define setSn_RXMEM_SIZE | ( | sn,
 |  | rxmemsize
 | ) | WIZCHIP_WRITE(RMSR, (WIZCHIP_READ(RMSR) & ~(0x03 << (2*sn))) | (rxmemsize << (2*sn)))

Set Sn_RXMEM_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
(uint8_t)rxmemsize | Value to set Sn_RXMEM_SIZE
See Also
getSn_RXMEM_SIZE()

Definition at line 1591 of file w5100.h.

#define getSn_RXMEM_SIZE ( sn) ((WIZCHIP_READ(RMSR) & (0x03 << (2*sn))) >> (2*sn))

Get Sn_RXMEM_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_RXMEM.
See Also
setSn_RXMEM_SIZE()

Definition at line 1602 of file w5100.h.

#define setSn_TXMEM_SIZE | ( | sn,
 |  | txmemsize
 | ) | WIZCHIP_WRITE(TMSR, (WIZCHIP_READ(TMSR) & ~(0x03 << (2*sn))) | (txmemsize << (2*sn)))

Set Sn_TXMEM_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)txmemsize | Value to set Sn_TXMEM_SIZE
See Also
getSn_TXMEM_SIZE()

Definition at line 1613 of file w5100.h.

#define getSn_TXMEM_SIZE ( sn) ((WIZCHIP_READ(TMSR) & (0x03 << (2*sn))) >> (2*sn))

Get Sn_TXMEM_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_TXMEM_SIZE.
See Also
setSn_TXMEM_SIZE()

Definition at line 1624 of file w5100.h.

#define getSn_TX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))

Get Sn_TX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_RD.

Definition at line 1642 of file w5100.h.

Referenced by send().

#define setSn_TX_WR | ( | sn,
 |  | txwr
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
}

Set Sn_TX_WR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)txwr | Value to set Sn_TX_WR
See Also
GetSn_TX_WR()

Definition at line 1652 of file w5100.h.

Referenced by wiz_send_data().

#define getSn_TX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))

Get Sn_TX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_WR.
See Also
setSn_TX_WR()

Definition at line 1664 of file w5100.h.

Referenced by wiz_send_data().

#define setSn_RX_RD | ( | sn,
 |  | rxrd
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
}

Set Sn_RX_RD register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)rxrd | Value to set Sn_RX_RD
See Also
getSn_RX_RD()

Definition at line 1682 of file w5100.h.

Referenced by wiz_recv_data(), and wiz_recv_ignore().

#define getSn_RX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))

Get Sn_RX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_. uint16_t. Value of Sn_RX_RD.
See Also
setSn_RX_RD()

Definition at line 1694 of file w5100.h.

Referenced by wiz_recv_data(), and wiz_recv_ignore().

#define setSn_RX_WR | ( | sn,
 |  | rxwr
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
}

Set Sn_RX_WR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)rxwr | Value to set Sn_RX_WR
See Also
getSn_RX_WR()

Definition at line 1704 of file w5100.h.

#define getSn_RX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))

Get Sn_RX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_RX_WR.

Definition at line 1716 of file w5100.h.

#define setSn_FRAG | ( | sn,
 |  | frag
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
}

Set Sn_FRAG register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)frag | Value to set Sn_FRAG
See Also
getSn_FRAD()

Definition at line 1726 of file w5100.h.

#define getSn_FRAG ( sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))

Get Sn_FRAG register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_FRAG.
See Also
setSn_FRAG()

Definition at line 1738 of file w5100.h.

#define getSn_RxMAX ( sn) ((uint16_t)(1 << getSn_RXMEM_SIZE(sn)) << 10)

Get the max RX buffer size of socket sn.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Max buffer size

Definition at line 1747 of file w5100.h.

Referenced by ctlsocket(), getSn_RxBASE(), recv(), and wiz_recv_data().

#define getSn_TxMAX ( sn) ((uint16_t)(1 << getSn_TXMEM_SIZE(sn)) << 10)

Get the max TX buffer size of socket sn.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Max buffer size

Definition at line 1757 of file w5100.h.

Referenced by ctlsocket(), getSn_TxBASE(), recv(), send(), sendto(), and wiz_send_data().

#define getSn_RxMASK ( sn) (getSn_RxMAX(sn) - 1)

Get the mask of socket sn RX buffer.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Mask value

Definition at line 1766 of file w5100.h.

Referenced by wiz_recv_data().

#define getSn_TxMASK ( sn) (getSn_TxMAX(sn) - 1)

Get the mask of socket sn TX buffer.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Mask value

Definition at line 1775 of file w5100.h.

Referenced by wiz_send_data().

Function Documentation

uint16_t getSn_TX_FSR ( uint8_t sn)

Get Sn_TX_FSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_FSR.

Definition at line 180 of file w5100.c.

uint16_t getSn_RX_RSR ( uint8_t sn)

Get Sn_RX_RSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_RX_RSR.

Definition at line 197 of file w5100.c.

uint32_t getSn_RxBASE ( uint8_t sn)

Get the base address of socket sn RX buffer.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Socket n RX buffer base address.

Definition at line 216 of file w5100.c.

uint32_t getSn_TxBASE ( uint8_t sn)

Get the base address of socket sn TX buffer.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Socket n TX buffer base address.

Definition at line 230 of file w5100.c.

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP register

Modules
WIZCHIP register
W5100

WIZCHIP register defines register group of W5100 . More...

Collaboration diagram for WIZCHIP register:

Modules

Common register
Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
Socket register
Socket register group
Socket register configures and control SOCKETn which is necessary to data communication.

Detailed Description

WIZCHIP register defines register group of W5100 .

  • Common register : Common register group W5100
  • Socket register : SOCKET n register group W5100
Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register

Macros
Common register
WIZCHIP register

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc. More...

Collaboration diagram for Common register:

Macros

#define | MR (_W5100_IO_BASE_ + (0x0000))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5100_IO_BASE_ + (0x0001))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5100_IO_BASE_ + (0x0005))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5100_IO_BASE_ + (0x0009))
Source MAC Register address(R/W) More...
#define | SIPR (_W5100_IO_BASE_ + (0x000F))
Source IP Register address(R/W) More...
#define | IR (_W5100_IO_BASE_ + (0x0015))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5100_IO_BASE_ + (0x0016))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5100_IO_BASE_ + (0x0017))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5100_IO_BASE_ + (0x0019))
Retry count register(R/W) More...
#define | PATR (_W5100_IO_BASE_ + (0x001C))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PTIMER (_W5100_IO_BASE_ + (0x0028))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PMAGIC (_W5100_IO_BASE_ + (0x0029))
PPP LCP Magic number register in PPPoE mode(R) More...

Detailed Description

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.

See Also
MR : Mode register.
GAR, SUBR, SHAR, SIPR
IR, Sn_IR, IMR : Interrupt.
RTR, RCR : Data retransmission.
PTIMER, PMAGIC : PPPoE.

Macro Definition Documentation

#define MR (_W5100_IO_BASE_ + (0x0000))

Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.

Each bit of MR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RST | Reserved | WOL | PB | PPPoE | Reserved | AI | IND
  • MR_RST : Reset
  • MR_PB : Ping block
  • MR_PPPOE : PPPoE mode
  • MR_AI : Address Auto-Increment in Indirect Bus Interface
  • MR_IND : Indirect Bus Interface mode

Definition at line 197 of file w5100.h.

Referenced by WIZCHIP_READ_BUF(), and WIZCHIP_WRITE_BUF().

#define GAR (_W5100_IO_BASE_ + (0x0001))

Gateway IP Register address(R/W)

GAR configures the default gateway address.

Definition at line 204 of file w5100.h.

#define SUBR (_W5100_IO_BASE_ + (0x0005))

Subnet mask Register address(R/W)

SUBR configures the subnet mask address.

Definition at line 211 of file w5100.h.

#define SHAR (_W5100_IO_BASE_ + (0x0009))

Source MAC Register address(R/W)

SHAR configures the source hardware address.

Definition at line 218 of file w5100.h.

#define SIPR (_W5100_IO_BASE_ + (0x000F))

Source IP Register address(R/W)

SIPR configures the source IP address.

Definition at line 225 of file w5100.h.

#define IR (_W5100_IO_BASE_ + (0x0015))

Interrupt Register(R/W)

IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00

Each bit of IR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CONFLICT | UNREACH | PPPoE | Reserved | S3_INT | S2_INT | S1_INT | S0_INT
  • IR_CONFLICT : IP conflict
  • IR_UNREACH : Destination unreachable
  • IR_PPPoE : PPPoE connection close
  • IR_SOCK(3) : SOCKET 3 Interrupt
  • IR_SOCK(2) : SOCKET 2 Interrupt
  • IR_SOCK(1) : SOCKET 1 Interrupt
  • IR_SOCK(0) : SOCKET 0 Interrupt

Definition at line 248 of file w5100.h.

#define _IMR_ (_W5100_IO_BASE_ + (0x0016))

Socket Interrupt Mask Register(R/W)

Each bit of IMR corresponds to each bit of IR. When a bit of IMR is and the corresponding bit of IR is set, Interrupt will be issued.

Definition at line 256 of file w5100.h.

#define _RTR_ (_W5100_IO_BASE_ + (0x0017))

Timeout register address( 1 is 100us )(R/W)

RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0or 000 And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5100 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5100 retransmits the packet or issues timeout.

Definition at line 266 of file w5100.h.

#define _RCR_ (_W5100_IO_BASE_ + (0x0019))

Retry count register(R/W)

RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR[TIMEOUT] = '1').

Definition at line 274 of file w5100.h.

#define PATR (_W5100_IO_BASE_ + (0x001C))

PPP LCP Request Timer register in PPPoE mode(R)

PATR notifies authentication method that has been agreed at the connection with PPPoE Server. W5100 supports two types of Authentication method - PAP and CHAP.

Definition at line 285 of file w5100.h.

#define PTIMER (_W5100_IO_BASE_ + (0x0028))

PPP LCP Request Timer register in PPPoE mode(R)

PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.

Definition at line 293 of file w5100.h.

#define PMAGIC (_W5100_IO_BASE_ + (0x0029))

PPP LCP Magic number register in PPPoE mode(R)

PMAGIC configures the 4bytes magic number to be used in LCP negotiation.

Definition at line 300 of file w5100.h.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register

Macros
Socket register
WIZCHIP register

Socket register group
Socket register configures and control SOCKETn which is necessary to data communication. More...

Collaboration diagram for Socket register:

Macros

#define | Sn_MR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))
socket Mode register(R/W) More...
#define | Sn_CR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))
Socket command register(R/W) More...
#define | Sn_IR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))
Socket interrupt register(R) More...
#define | Sn_SR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))
Socket status register(R) More...
#define | Sn_PORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))
source port register(R/W) More...
#define | Sn_DHAR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))
Peer IP register address(R/W) More...
#define | Sn_DPORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))
Peer port register address(R/W) More...
#define | Sn_MSSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_PROTO(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))
IP Protocol(PROTO) Register(R/W) More...
#define | Sn_TOS(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + 0x0015)
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_TX_FSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))
Received data size register(R) More...
#define | Sn_RX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))
Write point of Receive memory(R) More...

Detailed Description

Socket register group
Socket register configures and control SOCKETn which is necessary to data communication.

See Also
Sn_MR, Sn_CR, Sn_IR : SOCKETn Control
Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
Sn_MSSR, Sn_TOS, Sn_TTL, Sn_FRAG : Internet protocol.
Sn_RXMEM_SIZE, Sn_TXMEM_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication

Macro Definition Documentation

#define Sn_MR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))

socket Mode register(R/W)

Sn_MR configures the option or protocol type of Socket n.

Each bit of Sn_MR defined as the following.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MULTI | MF | ND/MC | Reserved | Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0]
  • Sn_MR_MULTI : Support UDP Multicasting
  • Sn_MR_MF : Support MACRAW
  • Sn_MR_ND : No Delayed Ack(TCP) flag
  • Sn_MR_MC : IGMP version used in UDP mulitcasting
  • Protocol
    Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0] | Meaning
    0 | 0 | 0 | 0 | Closed
    0 | 0 | 0 | 1 | TCP
    0 | 0 | 1 | 0 | UDP
    0 | 1 | 0 | 0 | MACRAW
  • In case of Socket 0
    Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0] | Meaning
    0 | 1 | 0 | 0 | MACRAW
    0 | 1 | 0 | 1 | PPPoE
    • Sn_MR_MACRAW : MAC LAYER RAW SOCK

Sn_MR_UDP : UDP

  • Sn_MR_TCP : TCP
  • Sn_MR_CLOSE : Unused socket
    Note
    MACRAW mode should be only used in Socket 0.

Definition at line 344 of file w5100.h.

#define Sn_CR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))

Socket command register(R/W)

This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.
After W5100 accepts the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed.
To check whether the command is completed or not, please check the Sn_IR or Sn_SR.

  • Sn_CR_OPEN : Initialize or open socket.
  • Sn_CR_LISTEN : Wait connection request in TCP mode(Server mode)
  • Sn_CR_CONNECT : Send connection request in TCP mode(Client mode)
  • Sn_CR_DISCON : Send closing request in TCP mode.
  • Sn_CR_CLOSE : Close socket.
  • Sn_CR_SEND : Update TX buffer pointer and send data.
  • Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process.
  • Sn_CR_SEND_KEEP : Send keep alive message.
  • Sn_CR_RECV : Update RX buffer pointer and receive data.
  • In case of S0_MR(P3:P0) = S0_MR_PPPoE
    Value | Symbol | Description
    0x23 | PCON | PPPoE connection begins by transmitting PPPoE discovery packet
    0x24 | PDISCON | Closes PPPoE connection
    0x25 | PCR | In each phase, it transmits REQ message.
    0x26 | PCN | In each phase, it transmits NAK message.
    0x27 | PCJ | In each phase, it transmits REJECT message.

Definition at line 372 of file w5100.h.

#define Sn_IR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))

Socket interrupt register(R)

Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).
When an interrupt occurs and the corresponding bit IR_SOCK(N) in IMR are set, IR_SOCK(N) in IR becomes '1'.
In order to clear the Sn_IR bit, the host should write the bit to

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRECV | PFAIL | PNEXT | SEND_OK | TIMEOUT | RECV | DISCON | CON
  • Sn_IR_PRECV : PPP Receive Interrupt
  • Sn_IR_PFAIL : PPP Fail Interrupt
  • Sn_IR_PNEXT : PPP Next Phase Interrupt
  • Sn_IR_SENDOK : SEND_OK Interrupt
  • Sn_IR_TIMEOUT : TIMEOUT Interrupt
  • Sn_IR_RECV : RECV Interrupt
  • Sn_IR_DISCON : DISCON Interrupt
  • Sn_IR_CON : CON Interrupt

Definition at line 393 of file w5100.h.

#define Sn_SR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))

Socket status register(R)

Sn_SR indicates the status of Socket n.
The status of Socket n is changed by Sn_CR or some special control packet as SYN, FIN packet in TCP.

Normal status
  • SOCK_CLOSED : Closed
  • SOCK_INIT : Initiate state
  • SOCK_LISTEN : Listen state
  • SOCK_ESTABLISHED : Success to connect
  • SOCK_CLOSE_WAIT : Closing state
  • SOCK_UDP : UDP socket
  • SOCK_MACRAW : MAC raw mode socket
Temporary status during changing the status of Socket n.
  • SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
  • SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
  • SOCK_FIN_WAIT : Connection state
  • SOCK_CLOSING : Closing state
  • SOCK_TIME_WAIT : Closing state
  • SOCK_LAST_ACK : Closing state

Definition at line 416 of file w5100.h.

#define Sn_PORT ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))

source port register(R/W)

Sn_PORT configures the source port number of Socket n. It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered.

Definition at line 424 of file w5100.h.

#define Sn_DHAR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))

Peer MAC register address(R/W)

Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND command.

Definition at line 432 of file w5100.h.

#define Sn_DIPR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))

Peer IP register address(R/W)

Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode. In TCP client mode, it configures an IP address of TCP server before CONNECT command. In TCP server mode, it indicates an IP address of TCP client after successfully establishing connection. In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.

Definition at line 442 of file w5100.h.

#define Sn_DPORT ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))

Peer port register address(R/W)

Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. In TCP clientmode, it configures the listen port number of TCP server before CONNECT command. In TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.

Definition at line 452 of file w5100.h.

#define Sn_MSSR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))

Maximum Segment Size(Sn_MSSR0) register address(R/W)

Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.

Definition at line 459 of file w5100.h.

#define Sn_PROTO ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))

IP Protocol(PROTO) Register(R/W)

Sn_PROTO that sets the protocol number field of the IP header at the IP layer. It is valid only in IPRAW mode, and ignored in other modes.

Definition at line 467 of file w5100.h.

#define Sn_TOS ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + 0x0015)

IP Type of Service(TOS) Register(R/W)

Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. It is set before OPEN command.

Definition at line 475 of file w5100.h.

#define Sn_TTL ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))

IP Time to live(TTL) Register(R/W)

Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. It is set before OPEN command.

Definition at line 483 of file w5100.h.

#define Sn_TX_FSR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))

Transmit free memory size register(R)

Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by Sn_TXMEM_SIZE. Data bigger than Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent. Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, transmit the data after dividing into the checked size and saving in the Socket n TX buffer.

Definition at line 502 of file w5100.h.

Referenced by getSn_TX_FSR().

#define Sn_TX_RD ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))

Transmit memory read pointer register address(R)

Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP. After its initialization, it is auto-increased by SEND command. SEND command transmits the saved data from the current Sn_TX_RD to the Sn_TX_WR in the Socket n TX Buffer. After transmitting the saved data, the SEND command increases the Sn_TX_RD as same as the Sn_TX_WR. If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 514 of file w5100.h.

#define Sn_TX_WR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))

Transmit memory write pointer register address(R/W)

Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP.
It should be read or be updated like as follows.

  1. Read the starting address for saving the transmitting data.
  2. Save the transmitting data from the starting address of Socket n TX buffer.
  3. After saving the transmitting data, update Sn_TX_WR to the increased value as many as transmitting data size. If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.
  4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command

Definition at line 528 of file w5100.h.

#define Sn_RX_RSR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))

Received data size register(R)

Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. Sn_RX_RSR does not exceed the Sn_RXMEM_SIZE and is calculated as the difference between Socket n RX Write Pointer (Sn_RX_WR)and Socket n RX Read Pointer (Sn_RX_RD)

Definition at line 537 of file w5100.h.

Referenced by getSn_RX_RSR().

#define Sn_RX_RD ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))

Read point of Receive memory(R/W)

Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.

  1. Read the starting save address of the received data.
  2. Read data from the starting address of Socket n RX Buffer.
  3. After reading the received data, Update Sn_RX_RD to the increased value as many as the reading size. If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs, update with the lower 16bits value ignored the carry bit.
  4. Order RECV command is for notifying the updated Sn_RX_RD to W5100.

Definition at line 550 of file w5100.h.

#define Sn_RX_WR ( sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))

Write point of Receive memory(R)

Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 559 of file w5100.h.

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


Socket APIs: W5200

Modules
W5200

WHIZCHIP register defines and I/O functions of W5200. More...

Collaboration diagram for W5200:

Modules

WIZCHIP I/O functions
This supports the basic I/O functions for WIZCHIP register.
WIZCHIP register
WIZCHIP register defines register group of W5200 .

Detailed Description

WHIZCHIP register defines and I/O functions of W5200.

  • WIZCHIP register : Common register and Socket register
  • WIZCHIP I/O functions : Basic I/O function, Common register access functions and Socket register
Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP I/O functions

Modules
WIZCHIP I/O functions
W5200

This supports the basic I/O functions for WIZCHIP register. More...

Collaboration diagram for WIZCHIP I/O functions:

Modules

Basic I/O function
These are basic input/output functions to read values from register or write values to register.
Common register access functions
These are functions to access common registers.
Socket register access functions
These are functions to access socket registers.

Detailed Description

This supports the basic I/O functions for WIZCHIP register.

  • Basic I/O function
    WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()

  • Common register access functions
    1. Mode
      getMR(), setMR()
    2. Interrupt
      getIR(), setIR(), getIMR(), setIMR(), getIR2(), setIR2(), getIMR2(), setIMR2(), getINTLEVEL(), setINTLEVEL()
    3. Network Information
      getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
    4. Retransmission
      getRCR(), setRCR(), getRTR(), setRTR()
    5. PPPoE
      getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC()
    6. etc.
      getPHYSTATUS(), getVERSIONR()

  • Socket register access functions
    1. SOCKET control
      getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
    2. SOCKET information
      getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT() getSn_MSSR(), setSn_MSSR()
    3. SOCKET communication
      getSn_RXMEM_SIZE(), setSn_RXMEM_SIZE(), getSn_TXMEM_SIZE(), setSn_TXMEM_SIZE()
      getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR()
      getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR()
      getSn_TX_FSR(), getSn_RX_RSR()
    4. IP header field
      getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS()
      getSn_TTL(), setSn_TTL()
Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: Basic I/O function

Functions
Basic I/O function
WIZCHIP I/O functions

These are basic input/output functions to read values from register or write values to register. More...

Collaboration diagram for Basic I/O function:

Functions

uint8_t | WIZCHIP_READ (uint32_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

These are basic input/output functions to read values from register or write values to register.

Function Documentation

uint8_t WIZCHIP_READ ( uint32_t AddrSel)

It reads 1 byte value from a register.

Parameters
AddrSel Register address
Returns
The value of register

Definition at line 74 of file w5200.c.

void WIZCHIP_WRITE | ( | uint32_t | AddrSel,
 |  | uint8_t | wb
 | ) |  |

It writes 1 byte value to a register.

Parameters
AddrSel | Register address
wb | Write data
Returns
void

Definition at line 46 of file w5200.c.

void WIZCHIP_READ_BUF | ( | uint32_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It reads sequence data from registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to read data
len | Data length

Definition at line 141 of file w5200.c.

void WIZCHIP_WRITE_BUF | ( | uint32_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It writes sequence data to registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to write data
len | Data length

Definition at line 108 of file w5200.c.

void wiz_send_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to internal TX memory.

This function reads the Tx write pointer register and after that, it copies the wizdata(pointer buffer) of the length of len(variable) bytes to internal TX memory and updates the Tx write pointer register. This function is being called by send() and sendto() function also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to write data
len | Data length
See Also
wiz_recv_data()

It copies data to internal TX memory.

This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer register. User should read upper byte first and lower byte later to get proper value. And this function is being used for copy the data form application buffer to Transmite buffer of the chip. It calculate the actual physical address where one has to write the data in transmite buffer. Here also take care of the condition while it exceed the Tx memory uper-bound of socket.

This function reads the Tx write pointer register and after that, it copies the wizdata(pointer buffer) of the length of len(variable) bytes to internal TX memory and updates the Tx write pointer register. This function is being called by send() and sendto() function also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to write data
len | Data length
See Also
wiz_recv_data()

It copies data to internal TX memory.

This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer register. User should read upper byte first and lower byte later to get proper value. And this function is being used for copy the data form application buffer to Transmite buffer of the chip. It calculate the actual physical address where one has to write the data in transmite buffer. Here also take care of the condition while it exceed the Tx memory uper-bound of socket.

Definition at line 254 of file w5100.c.

void wiz_recv_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after that, it copies the received data from internal RX memory to wizdata(pointer variable) of the length of len(variable) bytes. This function is being called by recv() also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to read data
len | Data length
See Also
wiz_send_data()

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after copy the data from receive buffer update the Rx write pointer register. User should read upper byte first and lower byte later to get proper value. It calculate the actual physical address where one has to read the data from Receive buffer. Here also take care of the condition while it exceed the Rx memory uper-bound of socket.

This function read the Rx read pointer register and after that, it copies the received data from internal RX memory to wizdata(pointer variable) of the length of len(variable) bytes. This function is being called by recv() also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to read data
len | Data length
See Also
wiz_send_data()

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after copy the data from receive buffer update the Rx write pointer register. User should read upper byte first and lower byte later to get proper value. It calculate the actual physical address where one has to read the data from Receive buffer. Here also take care of the condition while it exceed the Rx memory uper-bound of socket.

Definition at line 296 of file w5100.c.

void wiz_recv_ignore | ( | uint8_t | sn,
 |  | uint16_t | len
 | ) |  |

It discard the received data in RX memory.

It discards the data of the length of len(variable) bytes in internal RX memory.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
len | Data length

Definition at line 328 of file w5100.c.

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register access functions

Macros
Common register access functions
WIZCHIP I/O functions

These are functions to access common registers. More...

Collaboration diagram for Common register access functions:

Macros

#define | setMR(mr) WIZCHIP_WRITE(MR,mr)
Set Mode Register. More...
#define | getMR() WIZCHIP_READ(MR)
Get MR. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set GAR. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get GAR. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)
Set SUBR. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get SUBR. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set SHAR. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get SHAR. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set SIPR. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get SIPR. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xA0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xA0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | getPATR() (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
Get PATR register. More...
#define | getPPPALGO() WIZCHIP_READ(PPPALGO)
Get PPPALGO register. More...
#define | getVERSIONR() WIZCHIP_READ(VERSIONR)
Get VERSIONR register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...
#define | setINTLEVEL(intlevel)
Set INTLEVEL register. More...
#define | getINTLEVEL() (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
Get INTLEVEL register. More...
#define | setIR2(ir2) WIZCHIP_WRITE(IR2, ir2)
Set IR2 register. More...
#define | getIR2() WIZCHIP_READ(IR2)
Get IR2 register. More...
#define | getPHYSTATUS() WIZCHIP_READ(PHYSTATUS)
Get PHYSTATUS register. More...
#define | setIMR2(imr2) WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))
Set IMR2 register. More...
#define | getIMR2() (WIZCHIP_READ(IMR2) & 0xA0)
Get IMR2 register. More...

Detailed Description

These are functions to access common registers.

Macro Definition Documentation

#define setMR ( mr) WIZCHIP_WRITE(MR,mr)

Set Mode Register.

Parameters
(uint8_t)mr The value to be set.
See Also
getMR()

Definition at line 1223 of file w5200.h.

#define getMR ( ) WIZCHIP_READ(MR)

Get MR.

Returns
uint8_t. The value of Mode register.
See Also
setMR()

Definition at line 1232 of file w5200.h.

#define setGAR ( gar) WIZCHIP_WRITE_BUF(GAR,gar,4)

Set GAR.

Parameters
(uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
See Also
getGAR()

Definition at line 1241 of file w5200.h.

#define getGAR ( gar) WIZCHIP_READ_BUF(GAR,gar,4)

Get GAR.

Parameters
(uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
See Also
setGAR()

Definition at line 1250 of file w5200.h.

#define setSUBR ( subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)

Set SUBR.

Parameters
(uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
Note
If subr is null pointer, set the backup subnet to SUBR.
If subr is 0.0.0.0, back up SUBR and clear it.
Otherwize, set subr to SUBR
See Also
getSUBR()

Definition at line 1262 of file w5200.h.

#define getSUBR ( subr) WIZCHIP_READ_BUF(SUBR, subr, 4)

Get SUBR.

Parameters
(uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
See Also
setSUBR()

Definition at line 1271 of file w5200.h.

#define setSHAR ( shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)

Set SHAR.

Parameters
(uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
See Also
getSHAR()

Definition at line 1280 of file w5200.h.

#define getSHAR ( shar) WIZCHIP_READ_BUF(SHAR, shar, 6)

Get SHAR.

Parameters
(uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
See Also
setSHAR()

Definition at line 1289 of file w5200.h.

#define setSIPR ( sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)

Set SIPR.

Parameters
(uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
See Also
getSIPR()

Definition at line 1298 of file w5200.h.

#define getSIPR ( sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)

Get SIPR.

Parameters
(uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
See Also
setSIPR()

Definition at line 1307 of file w5200.h.

#define setIR ( ir) WIZCHIP_WRITE(IR, (ir & 0xA0))

Set IR register.

Parameters
(uint8_t)ir Value to set IR register.
See Also
getIR()

Definition at line 1316 of file w5200.h.

#define getIR ( ) (WIZCHIP_READ(IR) & 0xA0)

Get IR register.

Returns
uint8_t. Value of IR register.
See Also
setIR()

Definition at line 1324 of file w5200.h.

#define setIMR ( imr) WIZCHIP_WRITE(_IMR_, imr)

Set IMR register.

Parameters
(uint8_t)imr Value to set IMR register.
See Also
getIMR()

Definition at line 1333 of file w5200.h.

#define getIMR ( ) WIZCHIP_READ(_IMR_)

Get IMR register.

Returns
uint8_t. Value of IMR register.
See Also
setIMR()

Definition at line 1342 of file w5200.h.

#define setRTR ( rtr)
Value:
{\
WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
}

Set RTR register.

Parameters
(uint16_t)rtr Value to set RTR register.
See Also
getRTR()

Definition at line 1351 of file w5200.h.

#define getRTR ( ) (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))

Get RTR register.

Returns
uint16_t. Value of RTR register.
See Also
setRTR()

Definition at line 1362 of file w5200.h.

#define setRCR ( rcr) WIZCHIP_WRITE(_RCR_, rcr)

Set RCR register.

Parameters
(uint8_t)rcr Value to set RCR register.
See Also
getRCR()

Definition at line 1371 of file w5200.h.

#define getRCR ( ) WIZCHIP_READ(_RCR_)

Get RCR register.

Returns
uint8_t. Value of RCR register.
See Also
setRCR()

Definition at line 1380 of file w5200.h.

#define getPATR ( ) (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))

Get PATR register.

Returns
uint16_t. Value to set PATR register

Definition at line 1388 of file w5200.h.

#define getPPPALGO ( ) WIZCHIP_READ(PPPALGO)

Get PPPALGO register.

Returns
uint8_t. Value to set PPPALGO register

Definition at line 1396 of file w5200.h.

#define getVERSIONR ( ) WIZCHIP_READ(VERSIONR)

Get VERSIONR register.

Returns
uint8_t. Value to set VERSIONR register

Definition at line 1405 of file w5200.h.

#define setPTIMER ( ptimer) WIZCHIP_WRITE(PTIMER, ptimer)

Set PTIMER register.

Parameters
(uint8_t)ptimer Value to set PTIMER register.
See Also
getPTIMER()

Definition at line 1414 of file w5200.h.

#define getPTIMER ( ) WIZCHIP_READ(PTIMER)

Get PTIMER register.

Returns
uint8_t. Value of PTIMER register.
See Also
setPTIMER()

Definition at line 1423 of file w5200.h.

#define setPMAGIC ( pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)

Set PMAGIC register.

Parameters
(uint8_t)pmagic Value to set PMAGIC register.
See Also
getPMAGIC()

Definition at line 1432 of file w5200.h.

#define getPMAGIC ( ) WIZCHIP_READ(PMAGIC)

Get PMAGIC register.

Returns
uint8_t. Value of PMAGIC register.
See Also
setPMAGIC()

Definition at line 1441 of file w5200.h.

#define setINTLEVEL ( intlevel)
Value:
{\
WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
}

Set INTLEVEL register.

Parameters
(uint16_t)intlevel Value to set INTLEVEL register.
See Also
getINTLEVEL()

Definition at line 1450 of file w5200.h.

Referenced by ctlwizchip().

#define getINTLEVEL ( ) (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))

Get INTLEVEL register.

Returns
uint16_t. Value of INTLEVEL register.
See Also
setINTLEVEL()

Definition at line 1460 of file w5200.h.

Referenced by ctlwizchip().

#define setIR2 ( ir2) WIZCHIP_WRITE(IR2, ir2)

Set IR2 register.

Parameters
(uint8_t)ir2 Value to set IR2 register.
See Also
getIR2()

Definition at line 1469 of file w5200.h.

#define getIR2 ( ) WIZCHIP_READ(IR2)

Get IR2 register.

Returns
uint8_t. Value of IR2 register.
See Also
setIR2()

Definition at line 1479 of file w5200.h.

#define getPHYSTATUS ( ) WIZCHIP_READ(PHYSTATUS)

Get PHYSTATUS register.

Returns
uint8_t. Value to set PHYSTATUS register.

Definition at line 1488 of file w5200.h.

Referenced by wizphy_getphylink(), and wizphy_getphypmode().

#define setIMR2 ( imr2) WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))

Set IMR2 register.

Parameters
(uint8_t)imr2 Value to set IMR2 register.
See Also
getIMR2()

Definition at line 1497 of file w5200.h.

#define getIMR2 ( ) (WIZCHIP_READ(IMR2) & 0xA0)

Get IMR2 register.

Returns
uint8_t. Value of IMR2 register.
See Also
setIMR2()

Definition at line 1507 of file w5200.h.

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register access functions

Macros | Functions
Socket register access functions
WIZCHIP I/O functions

These are functions to access socket registers. More...

Collaboration diagram for Socket register access functions:

Macros

#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), ir)
Set Sn_IR register. More...
#define | getSn_IR(sn) WIZCHIP_READ(Sn_IR(sn))
Get Sn_IR register. More...
#define | setSn_IMR(sn, imr) WIZCHIP_WRITE(Sn_IMR(sn), imr)
Set Sn_IMR register. More...
#define | setSn_IMR(sn,imr) WIZCHIP_WRITE(Sn_IMR(sn), imr)
Set Sn_IMR register. More...
#define | getSn_IMR(sn) WIZCHIP_READ(Sn_IMR(sn))
Get Sn_IMR register. More...
#define | getSn_IMR(sn) WIZCHIP_READ(Sn_IMR(sn))
Get Sn_IMR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_DHAR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_PROTO(sn, proto) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_PROTO register. More...
#define | getSn_PROTO(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_PROTO register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXMEM_SIZE(sn, rxmemsize) WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)
Set Sn_RXMEM_SIZE register. More...
#define | getSn_RXMEM_SIZE(sn) WIZCHIP_READ(Sn_RXMEM_SIZE(sn))
Get Sn_RXMEM_SIZE register. More...
#define | setSn_TXMEM_SIZE(sn, txmemsize) WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)
Set Sn_TXMEM_SIZE register. More...
#define | getSn_TXMEM_SIZE(sn) WIZCHIP_READ(Sn_TXMEM_SIZE(sn))
Get Sn_TXMEM_SIZE register. More...
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | setSn_RX_WR(sn, rxwr)
Set Sn_RX_WR register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | getSn_RxMAX(sn) ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)
Get the max RX buffer size of socket sn. More...
#define | getSn_TxMAX(sn) ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)
Get the max TX buffer size of socket sn. More...
#define | getSn_RxMASK(sn) ((uint16_t)getSn_RxMAX(sn) - 1)
Get the mask of socket sn RX buffer. More...
#define | getSn_TxMASK(sn) ((uint16_t)getSn_TxMAX(sn) - 1)
Get the mask of socket sn TX buffer. More...

Functions

uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint16_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint16_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...

Detailed Description

These are functions to access socket registers.

Macro Definition Documentation

#define setSn_MR | ( | sn,
 |  | mr
 | ) | WIZCHIP_WRITE(Sn_MR(sn),mr)

Set Sn_MR register.

Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ expect bit 4.
mr | Value to set Sn_MR
See Also
getSn_MR()

Definition at line 1520 of file w5200.h.

#define getSn_MR ( sn) WIZCHIP_READ(Sn_MR(sn))

Get Sn_MR register.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ expect bit 4.
Returns
Value of Sn_MR.
See Also
setSn_MR()

Definition at line 1530 of file w5200.h.

#define setSn_CR | ( | sn,
 |  | cr
 | ) | WIZCHIP_WRITE(Sn_CR(sn), cr)

Set Sn_CR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)cr | Value to set Sn_CR
See Also
getSn_CR()

Definition at line 1540 of file w5200.h.

#define getSn_CR ( sn) WIZCHIP_READ(Sn_CR(sn))

Get Sn_CR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_CR.
See Also
setSn_CR()

Definition at line 1550 of file w5200.h.

#define setSn_IR | ( | sn,
 |  | ir
 | ) | WIZCHIP_WRITE(Sn_IR(sn), ir)

Set Sn_IR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)ir | Value to set Sn_IR
See Also
getSn_IR()

Definition at line 1560 of file w5200.h.

#define getSn_IR ( sn) WIZCHIP_READ(Sn_IR(sn))

Get Sn_IR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_IR.
See Also
setSn_IR()

Definition at line 1570 of file w5200.h.

#define setSn_IMR | ( | sn,
 |  | imr
 | ) | WIZCHIP_WRITE(Sn_IMR(sn), imr)

Set Sn_IMR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)imr | Value to set Sn_IMR
See Also
getSn_IMR()
Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)imr | Value to set Sn_IMR
See Also
getSn_IMR()

Definition at line 1914 of file w5200.h.

Referenced by ctlsocket().

#define setSn_IMR | ( | sn,
 |  | imr
 | ) | WIZCHIP_WRITE(Sn_IMR(sn), imr)

Set Sn_IMR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)imr | Value to set Sn_IMR
See Also
getSn_IMR()
Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)imr | Value to set Sn_IMR
See Also
getSn_IMR()

Definition at line 1914 of file w5200.h.

#define getSn_IMR ( sn) WIZCHIP_READ(Sn_IMR(sn))

Get Sn_IMR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_IMR.
See Also
setSn_IMR()

Definition at line 1924 of file w5200.h.

Referenced by ctlsocket().

#define getSn_IMR ( sn) WIZCHIP_READ(Sn_IMR(sn))

Get Sn_IMR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_IMR.
See Also
setSn_IMR()

Definition at line 1924 of file w5200.h.

#define getSn_SR ( sn) WIZCHIP_READ(Sn_SR(sn))

Get Sn_SR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_SR.

Definition at line 1599 of file w5200.h.

#define setSn_PORT | ( | sn,
 |  | port
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
}

Set Sn_PORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)port | Value to set Sn_PORT.
See Also
getSn_PORT()

Definition at line 1609 of file w5200.h.

#define getSn_PORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))

Get Sn_PORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_PORT.
See Also
setSn_PORT()

Definition at line 1621 of file w5200.h.

#define setSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)

Set Sn_DHAR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dhar | Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
See Also
getSn_DHAR()

Definition at line 1631 of file w5200.h.

#define getSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)

Get Sn_DHAR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dhar | Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
See Also
setSn_DHAR()

Definition at line 1641 of file w5200.h.

#define setSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)

Set Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dipr | Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
See Also
getSn_DIPR()

Definition at line 1651 of file w5200.h.

#define getSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)

Get Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t*)dipr | Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
See Also
SetSn_DIPR()

Definition at line 1661 of file w5200.h.

#define setSn_DPORT | ( | sn,
 |  | dport
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
}

Set Sn_DPORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)dport | Value to set Sn_DPORT
See Also
getSn_DPORT()

Definition at line 1671 of file w5200.h.

#define getSn_DPORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))

Get Sn_DPORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_DPORT.
See Also
setSn_DPORT()

Definition at line 1683 of file w5200.h.

#define setSn_MSSR | ( | sn,
 |  | mss
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
}

Set Sn_MSSR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)mss | Value to set Sn_MSSR
See Also
setSn_MSSR()

Definition at line 1693 of file w5200.h.

#define getSn_MSSR ( sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))

Get Sn_MSSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_MSSR.
See Also
setSn_MSSR()

Definition at line 1705 of file w5200.h.

#define setSn_PROTO | ( | sn,
 |  | proto
 | ) | WIZCHIP_WRITE(Sn_TOS(sn), tos)

Set Sn_PROTO register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)proto | Value to set Sn_PROTO
See Also
getSn_PROTO()

Definition at line 1715 of file w5200.h.

#define getSn_PROTO ( sn) WIZCHIP_READ(Sn_TOS(sn))

Get Sn_PROTO register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_PROTO.
See Also
setSn_PROTO()

Definition at line 1725 of file w5200.h.

#define setSn_TOS | ( | sn,
 |  | tos
 | ) | WIZCHIP_WRITE(Sn_TOS(sn), tos)

Set Sn_TOS register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)tos | Value to set Sn_TOS
See Also
getSn_TOS()

Definition at line 1735 of file w5200.h.

#define getSn_TOS ( sn) WIZCHIP_READ(Sn_TOS(sn))

Get Sn_TOS register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
Returns
uint8_t. Value of Sn_TOS.
See Also
setSn_TOS()

Definition at line 1745 of file w5200.h.

#define setSn_TTL | ( | sn,
 |  | ttl
 | ) | WIZCHIP_WRITE(Sn_TTL(sn), ttl)

Set Sn_TTL register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
(uint8_t)ttl | Value to set Sn_TTL
See Also
getSn_TTL()

Definition at line 1755 of file w5200.h.

#define getSn_TTL ( sn) WIZCHIP_READ(Sn_TTL(sn))

Get Sn_TTL register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
Returns
uint8_t. Value of Sn_TTL.
See Also
setSn_TTL()

Definition at line 1765 of file w5200.h.

#define setSn_RXMEM_SIZE | ( | sn,
 |  | rxmemsize
 | ) | WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)

Set Sn_RXMEM_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_ .
(uint8_t)rxmemsize | Value to set Sn_RXMEM_SIZE
See Also
getSn_RXMEM_SIZE()

Definition at line 1775 of file w5200.h.

#define getSn_RXMEM_SIZE ( sn) WIZCHIP_READ(Sn_RXMEM_SIZE(sn))

Get Sn_RXMEM_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_RXMEM.
See Also
setSn_RXMEM_SIZE()

Definition at line 1787 of file w5200.h.

#define setSn_TXMEM_SIZE | ( | sn,
 |  | txmemsize
 | ) | WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)

Set Sn_TXMEM_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint8_t)txmemsize | Value to set Sn_TXMEM_SIZE
See Also
getSn_TXMEM_SIZE()

Definition at line 1799 of file w5200.h.

#define getSn_TXMEM_SIZE ( sn) WIZCHIP_READ(Sn_TXMEM_SIZE(sn))

Get Sn_TXMEM_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint8_t. Value of Sn_TXMEM_SIZE.
See Also
setSn_TXMEM_SIZE()

Definition at line 1811 of file w5200.h.

#define getSn_TX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))

Get Sn_TX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_RD.

Definition at line 1830 of file w5200.h.

#define setSn_TX_WR | ( | sn,
 |  | txwr
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
}

Set Sn_TX_WR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)txwr | Value to set Sn_TX_WR
See Also
GetSn_TX_WR()

Definition at line 1840 of file w5200.h.

#define getSn_TX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))

Get Sn_TX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_WR.
See Also
setSn_TX_WR()

Definition at line 1852 of file w5200.h.

#define setSn_RX_RD | ( | sn,
 |  | rxrd
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
}

Set Sn_RX_RD register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)rxrd | Value to set Sn_RX_RD
See Also
getSn_RX_RD()

Definition at line 1870 of file w5200.h.

#define getSn_RX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))

Get Sn_RX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_. uint16_t. Value of Sn_RX_RD.
See Also
setSn_RX_RD()

Definition at line 1882 of file w5200.h.

#define setSn_RX_WR | ( | sn,
 |  | rxwr
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
}

Set Sn_RX_WR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)rxwr | Value to set Sn_RX_WR
See Also
getSn_RX_WR()

Definition at line 1892 of file w5200.h.

#define getSn_RX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))

Get Sn_RX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_RX_WR.

Definition at line 1904 of file w5200.h.

#define setSn_FRAG | ( | sn,
 |  | frag
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
}

Set Sn_FRAG register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
(uint16_t)frag | Value to set Sn_FRAG
See Also
getSn_FRAD()

Definition at line 1934 of file w5200.h.

#define getSn_FRAG ( sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))

Get Sn_FRAG register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_FRAG.
See Also
setSn_FRAG()

Definition at line 1946 of file w5200.h.

#define getSn_RxMAX ( sn) ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)

Get the max RX buffer size of socket sn.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Max buffer size

Definition at line 1955 of file w5200.h.

#define getSn_TxMAX ( sn) ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)

Get the max TX buffer size of socket sn.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Max buffer size

Definition at line 1964 of file w5200.h.

#define getSn_RxMASK ( sn) ((uint16_t)getSn_RxMAX(sn) - 1)

Get the mask of socket sn RX buffer.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Mask value

Definition at line 1973 of file w5200.h.

#define getSn_TxMASK ( sn) ((uint16_t)getSn_TxMAX(sn) - 1)

Get the mask of socket sn TX buffer.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Mask value

Definition at line 1982 of file w5200.h.

Function Documentation

uint16_t getSn_TX_FSR ( uint8_t sn)

Get Sn_TX_FSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_FSR.

Definition at line 180 of file w5100.c.

uint16_t getSn_RX_RSR ( uint8_t sn)

Get Sn_RX_RSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_RX_RSR.

Definition at line 197 of file w5100.c.

uint16_t getSn_RxBASE ( uint8_t sn)

Get the base address of socket sn RX buffer.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Socket n RX buffer base address.

Definition at line 216 of file w5100.c.

References _W5100_IO_BASE_, _WIZCHIP_IO_RXBUF_, and getSn_RxMAX.

Referenced by wiz_recv_data().

uint16_t getSn_TxBASE ( uint8_t sn)

Get the base address of socket sn TX buffer.

Parameters
sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Socket n TX buffer base address.

Definition at line 230 of file w5100.c.

References _W5100_IO_BASE_, _WIZCHIP_IO_TXBUF_, and getSn_TxMAX.

Referenced by wiz_send_data().

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP register

Modules
WIZCHIP register
W5200

WIZCHIP register defines register group of W5200 . More...

Collaboration diagram for WIZCHIP register:

Modules

Common register
Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
Socket register
Socket register group
Socket register configures and control SOCKETn which is necessary to data communication.

Detailed Description

WIZCHIP register defines register group of W5200 .

  • Common register : Common register group w5200
  • Socket register : SOCKET n register group w5200
Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register

Macros
Common register
WIZCHIP register

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc. More...

Collaboration diagram for Common register:

Macros

#define | MR (_W5200_IO_BASE_ + (0x0000))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5200_IO_BASE_ + (0x0001))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5200_IO_BASE_ + (0x0005))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5200_IO_BASE_ + (0x0009))
Source MAC Register address(R/W) More...
#define | SIPR (_W5200_IO_BASE_ + (0x000F))
Source IP Register address(R/W) More...
#define | IR (_W5200_IO_BASE_ + (0x0015))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5200_IO_BASE_ + (0x0016))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5200_IO_BASE_ + (0x0017))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5200_IO_BASE_ + (0x0019))
Retry count register(R/W) More...
#define | PATR (_W5200_IO_BASE_ + (0x001C))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PPPALGO (_W5200_IO_BASE_ + (0x001E))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | VERSIONR (_W5200_IO_BASE_ + (0x001F))
chip version register address(R) More...
#define | PTIMER (_W5200_IO_BASE_ + (0x0028))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PMAGIC (_W5200_IO_BASE_ + (0x0029))
PPP LCP Magic number register in PPPoE mode(R) More...
#define | INTLEVEL (_W5200_IO_BASE_ + (0x0030))
Set Interrupt low level timer register address(R/W) More...
#define | IR2 (_W5200_IO_BASE_ + (0x0034))
Socket Interrupt Register(R/W) More...
#define | PHYSTATUS (_W5200_IO_BASE_ + (0x0035))
PHYSTATUS(R/W) More...
#define | IMR2 (_W5200_IO_BASE_ + (0x0036))
Interrupt mask register(R/W) More...

Detailed Description

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.

See Also
MR : Mode register.
GAR, SUBR, SHAR, SIPR
INTLEVEL, IR, IMR, IR2, IMR2 : Interrupt.
RTR, RCR : Data retransmission.
PTIMER, PMAGIC : PPPoE.
PHYSTATUS, VERSIONR : etc.

Macro Definition Documentation

#define MR (_W5200_IO_BASE_ + (0x0000))

Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.

Each bit of MR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RST | Reserved | WOL | PB | PPPoE | Reserved | AI | IND
  • MR_RST : Reset
  • MR_WOL : Wake on LAN
  • MR_PB : Ping block
  • MR_PPPOE : PPPoE mode
  • MR_AI : Address Auto-Increment in Indirect Bus Interface
  • MR_IND : Indirect Bus Interface mode

Definition at line 200 of file w5200.h.

#define GAR (_W5200_IO_BASE_ + (0x0001))

Gateway IP Register address(R/W)

GAR configures the default gateway address.

Definition at line 207 of file w5200.h.

#define SUBR (_W5200_IO_BASE_ + (0x0005))

Subnet mask Register address(R/W)

SUBR configures the subnet mask address.

Definition at line 214 of file w5200.h.

#define SHAR (_W5200_IO_BASE_ + (0x0009))

Source MAC Register address(R/W)

SHAR configures the source hardware address.

Definition at line 221 of file w5200.h.

#define SIPR (_W5200_IO_BASE_ + (0x000F))

Source IP Register address(R/W)

SIPR configures the source IP address.

Definition at line 228 of file w5200.h.

#define IR (_W5200_IO_BASE_ + (0x0015))

Interrupt Register(R/W)

IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00

Each bit of IR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CONFLICT | Reserved | PPPoE | Reserved | Reserved | Reserved | Reserved | Reserved
  • IR_CONFLICT : IP conflict
  • IR_PPPoE : PPPoE connection close

Definition at line 246 of file w5200.h.

#define _IMR_ (_W5200_IO_BASE_ + (0x0016))

Socket Interrupt Mask Register(R/W)

Each bit of IMR corresponds to each bit of IR2. When a bit of IMR is and the corresponding bit of IR2 is Interrupt will be issued. In other words, if a bit of SIMR is an interrupt will be not issued even if the corresponding bit of IR is

Definition at line 255 of file w5200.h.

#define _RTR_ (_W5200_IO_BASE_ + (0x0017))

Timeout register address( 1 is 100us )(R/W)

RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0or 000 And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5200 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5200 retransmits the packet or issues timeout.

Definition at line 265 of file w5200.h.

#define _RCR_ (_W5200_IO_BASE_ + (0x0019))

Retry count register(R/W)

RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR[TIMEOUT] = '1').

Definition at line 273 of file w5200.h.

#define PATR (_W5200_IO_BASE_ + (0x001C))

PPP LCP Request Timer register in PPPoE mode(R)

PATR notifies authentication method that has been agreed at the connection with PPPoE Server. W5200 supports two types of Authentication method - PAP and CHAP.

Definition at line 284 of file w5200.h.

#define PPPALGO (_W5200_IO_BASE_ + (0x001E))

PPP LCP Request Timer register in PPPoE mode(R)

PPPALGO notifies authentication algorithm in PPPoE mode. For detailed information, please refer to PPPoE application note.

Definition at line 292 of file w5200.h.

#define VERSIONR (_W5200_IO_BASE_ + (0x001F))

chip version register address(R)

VERSIONR always indicates the W5200 version as 0x03.

Definition at line 299 of file w5200.h.

#define PTIMER (_W5200_IO_BASE_ + (0x0028))

PPP LCP Request Timer register in PPPoE mode(R)

PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.

Definition at line 315 of file w5200.h.

#define PMAGIC (_W5200_IO_BASE_ + (0x0029))

PPP LCP Magic number register in PPPoE mode(R)

PMAGIC configures the 4bytes magic number to be used in LCP negotiation.

Definition at line 322 of file w5200.h.

#define INTLEVEL (_W5200_IO_BASE_ + (0x0030))

Set Interrupt low level timer register address(R/W)

INTLEVEL configures the Interrupt Assert Time.

Definition at line 336 of file w5200.h.

#define IR2 (_W5200_IO_BASE_ + (0x0034))

Socket Interrupt Register(R/W)

IR2 indicates the interrupt status of Socket.
Each bit of IR2 be still until Sn_IR is cleared by the host.
If Sn_IR is not equal to x00 the n-th bit of IR2 is and INTn PIN is asserted until IR2 is x00

Definition at line 347 of file w5200.h.

#define PHYSTATUS (_W5200_IO_BASE_ + (0x0035))

PHYSTATUS(R/W)

PHYSTATUS is the Register to indicate W5200 status of PHY.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Reserved | Reserved | LINK | POWERSAVE | POWERDOWN | Reserved | Reserved | Reserved
  • PHYSTATUS_LINK : Link Status Register[Read Only]
  • PHYSTATUS_POWERSAVE : Power save mode of PHY[R/W]
  • PHYSTATUS_POWERDOWN : Power down mode of PHY[R/W]

Definition at line 361 of file w5200.h.

#define IMR2 (_W5200_IO_BASE_ + (0x0036))

Interrupt mask register(R/W)

IMR2 is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR2 is and the corresponding bit of IR is an interrupt will be issued. In other words, if a bit of IMR2 is an interrupt will not be issued even if the corresponding bit of IR is

Each bit of IMR2 defined as the following.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IM_IR7 | Reserved | IM_IR5 | Reserved | Reserved | Reserved | Reserved | Reserved
  • IM_IR7 : IP Conflict Interrupt Mask
  • IM_IR5 : PPPoE Close Interrupt Mask

Definition at line 377 of file w5200.h.

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register

Macros
Socket register
WIZCHIP register

Socket register group
Socket register configures and control SOCKETn which is necessary to data communication. More...

Collaboration diagram for Socket register:

Macros

#define | Sn_MR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))
socket Mode register(R/W) More...
#define | Sn_CR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))
Socket command register(R/W) More...
#define | Sn_IR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))
Socket interrupt register(R) More...
#define | Sn_SR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))
Socket status register(R) More...
#define | Sn_PORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))
source port register(R/W) More...
#define | Sn_DHAR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))
Peer IP register address(R/W) More...
#define | Sn_DPORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))
Peer port register address(R/W) More...
#define | Sn_MSSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_PROTO(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))
IP Protocol(PROTO) Register(R/W) More...
#define | Sn_TOS(sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015)
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_RXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E))
Receive memory size register(R/W) More...
#define | Sn_TXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F))
Transmit memory size register(R/W) More...
#define | Sn_TX_FSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))
Received data size register(R) More...
#define | Sn_RX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))
Write point of Receive memory(R) More...
#define | Sn_IMR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C))
socket interrupt mask register(R) More...
#define | Sn_FRAG(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D))
Fragment field value in IP header register(R/W) More...

Detailed Description

Socket register group
Socket register configures and control SOCKETn which is necessary to data communication.

See Also
Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
Sn_MSSR, Sn_TOS, Sn_TTL, Sn_FRAG : Internet protocol.
Sn_RXMEM_SIZE, Sn_TXMEM_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication

Macro Definition Documentation

#define Sn_MR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))

socket Mode register(R/W)

Sn_MR configures the option or protocol type of Socket n.

Each bit of Sn_MR defined as the following.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MULTI | MF | ND/MC | Reserved | Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0]
  • Sn_MR_MULTI : Support UDP Multicasting
  • Sn_MR_MF : Support MACRAW
  • Sn_MR_ND : No Delayed Ack(TCP) flag
  • Sn_MR_MC : IGMP version used in UDP mulitcasting
  • Protocol
    Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0] | Meaning
    0 | 0 | 0 | 0 | Closed
    0 | 0 | 0 | 1 | TCP
    0 | 0 | 1 | 0 | UDP
    0 | 1 | 0 | 0 | MACRAW
  • In case of Socket 0
    Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0] | Meaning
    0 | 1 | 0 | 0 | MACRAW
    0 | 1 | 0 | 1 | PPPoE
    • Sn_MR_MACRAW : MAC LAYER RAW SOCK
    • Sn_MR_UDP : UDP
    • Sn_MR_TCP : TCP
    • Sn_MR_CLOSE : Unused socket
      Note
      MACRAW mode should be only used in Socket 0.

Definition at line 417 of file w5200.h.

#define Sn_CR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))

Socket command register(R/W)

This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.
After W5200 accepts the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed.
To check whether the command is completed or not, please check the Sn_IR or Sn_SR.

  • Sn_CR_OPEN : Initialize or open socket.
  • Sn_CR_LISTEN : Wait connection request in TCP mode(Server mode)
  • Sn_CR_CONNECT : Send connection request in TCP mode(Client mode)
  • Sn_CR_DISCON : Send closing request in TCP mode.
  • Sn_CR_CLOSE : Close socket.
  • Sn_CR_SEND : Update TX buffer pointer and send data.
  • Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process.
  • Sn_CR_SEND_KEEP : Send keep alive message.
  • Sn_CR_RECV : Update RX buffer pointer and receive data.
  • In case of S0_MR(P3:P0) = S0_MR_PPPoE
    Value | Symbol | Description
    0x23 | PCON | PPPoE connection begins by transmitting PPPoE discovery packet
    0x24 | PDISCON | Closes PPPoE connection
    0x25 | PCR | In each phase, it transmits REQ message.
    0x26 | PCN | In each phase, it transmits NAK message.
    0x27 | PCJ | In each phase, it transmits REJECT message.

Definition at line 445 of file w5200.h.

#define Sn_IR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))

Socket interrupt register(R)

Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).
When an interrupt occurs and the corresponding bit of Sn_IMR is the corresponding bit of Sn_IR becomes
In order to clear the Sn_IR bit, the host should write the bit to

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRECV | PFAIL | PNEXT | SEND_OK | TIMEOUT | RECV | DISCON | CON
  • Sn_IR_PRECV : PPP Receive Interrupt
  • Sn_IR_PFAIL : PPP Fail Interrupt
  • Sn_IR_PNEXT : PPP Next Phase Interrupt
  • Sn_IR_SENDOK : SEND_OK Interrupt
  • Sn_IR_TIMEOUT : TIMEOUT Interrupt
  • Sn_IR_RECV : RECV Interrupt
  • Sn_IR_DISCON : DISCON Interrupt
  • Sn_IR_CON : CON Interrupt

Definition at line 466 of file w5200.h.

#define Sn_SR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))

Socket status register(R)

Sn_SR indicates the status of Socket n.
The status of Socket n is changed by Sn_CR or some special control packet as SYN, FIN packet in TCP.

Normal status
  • SOCK_CLOSED : Closed
  • SOCK_INIT : Initiate state
  • SOCK_LISTEN : Listen state
  • SOCK_ESTABLISHED : Success to connect
  • SOCK_CLOSE_WAIT : Closing state
  • SOCK_UDP : UDP socket
  • SOCK_MACRAW : MAC raw mode socket
Temporary status during changing the status of Socket n.
  • SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
  • SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
  • SOCK_FIN_WAIT : Connection state
  • SOCK_CLOSING : Closing state
  • SOCK_TIME_WAIT : Closing state
  • SOCK_LAST_ACK : Closing state

Definition at line 489 of file w5200.h.

#define Sn_PORT ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))

source port register(R/W)

Sn_PORT configures the source port number of Socket n. It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered.

Definition at line 497 of file w5200.h.

#define Sn_DHAR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))

Peer MAC register address(R/W)

Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND command.

Definition at line 505 of file w5200.h.

#define Sn_DIPR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))

Peer IP register address(R/W)

Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode. In TCP client mode, it configures an IP address of TCP server before CONNECT command. In TCP server mode, it indicates an IP address of TCP client after successfully establishing connection. In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.

Definition at line 515 of file w5200.h.

#define Sn_DPORT ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))

Peer port register address(R/W)

Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. In TCP clientmode, it configures the listen port number of TCP server before CONNECT command. In TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.

Definition at line 525 of file w5200.h.

#define Sn_MSSR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))

Maximum Segment Size(Sn_MSSR0) register address(R/W)

Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.

Definition at line 532 of file w5200.h.

#define Sn_PROTO ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))

IP Protocol(PROTO) Register(R/W)

Sn_PROTO that sets the protocol number field of the IP header at the IP layer. It is valid only in IPRAW mode, and ignored in other modes.

Definition at line 540 of file w5200.h.

#define Sn_TOS ( sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015)

IP Type of Service(TOS) Register(R/W)

Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. It is set before OPEN command.

Definition at line 548 of file w5200.h.

#define Sn_TTL ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))

IP Time to live(TTL) Register(R/W)

Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. It is set before OPEN command.

Definition at line 556 of file w5200.h.

#define Sn_RXMEM_SIZE ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E))

Receive memory size register(R/W)

Sn_RXMEM_SIZE configures the RX buffer block size of Socket n. Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. If a different size is configured, the data cannot be normally received from a peer. Although Socket n RX Buffer Block size is initially configured to 2Kbytes, user can re-configure its size using Sn_RXMEM_SIZE. The total sum of Sn_RXMEM_SIZE can not be exceed 16Kbytes. When exceeded, the data reception error is occurred.

Definition at line 576 of file w5200.h.

#define Sn_TXMEM_SIZE ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F))

Transmit memory size register(R/W)

Sn_TXMEM_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. If a different size is configured, the data can't be normally transmitted to a peer. Although Socket n TX Buffer Block size is initially configured to 2Kbytes, user can be re-configure its size using Sn_TXMEM_SIZE. The total sum of Sn_TXMEM_SIZE can not be exceed 16Kbytes. When exceeded, the data transmission error is occurred.

Definition at line 587 of file w5200.h.

#define Sn_TX_FSR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))

Transmit free memory size register(R)

Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by Sn_TXMEM_SIZE. Data bigger than Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent. Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, transmit the data after dividing into the checked size and saving in the Socket n TX buffer.

Definition at line 598 of file w5200.h.

#define Sn_TX_RD ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))

Transmit memory read pointer register address(R)

Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP. After its initialization, it is auto-increased by SEND command. SEND command transmits the saved data from the current Sn_TX_RD to the Sn_TX_WR in the Socket n TX Buffer. After transmitting the saved data, the SEND command increases the Sn_TX_RD as same as the Sn_TX_WR. If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 610 of file w5200.h.

#define Sn_TX_WR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))

Transmit memory write pointer register address(R/W)

Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001), it is re-initialized while connecting with TCP.
It should be read or be updated like as follows.

  1. Read the starting address for saving the transmitting data.
  2. Save the transmitting data from the starting address of Socket n TX buffer.
  3. After saving the transmitting data, update Sn_TX_WR to the increased value as many as transmitting data size. If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.
  4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command

Definition at line 624 of file w5200.h.

#define Sn_RX_RSR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))

Received data size register(R)

Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. Sn_RX_RSR does not exceed the Sn_RXMEM_SIZE and is calculated as the difference between Socket n RX Write Pointer (Sn_RX_WR)and Socket n RX Read Pointer (Sn_RX_RD)

Definition at line 633 of file w5200.h.

#define Sn_RX_RD ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))

Read point of Receive memory(R/W)

Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.

  1. Read the starting save address of the received data.
  2. Read data from the starting address of Socket n RX Buffer.
  3. After reading the received data, Update Sn_RX_RD to the increased value as many as the reading size. If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs, update with the lower 16bits value ignored the carry bit.
  4. Order RECV command is for notifying the updated Sn_RX_RD to W5200.

Definition at line 646 of file w5200.h.

#define Sn_RX_WR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))

Write point of Receive memory(R)

Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 655 of file w5200.h.

#define Sn_IMR ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C))

socket interrupt mask register(R)

Sn_IMR masks the interrupt of Socket n. Each bit corresponds to each bit of Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of Sn_IMR is the corresponding bit of Sn_IR becomes When both the corresponding bit of Sn_IMR and Sn_IR are and the n-th bit of IR is Host is interrupted by asserted INTn PIN to low.

Definition at line 665 of file w5200.h.

#define Sn_FRAG ( sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D))

Fragment field value in IP header register(R/W)

Sn_FRAG configures the FRAG(Fragment field in IP header).

Definition at line 672 of file w5200.h.

Generated on Thu Apr 9 2015 14:44:04 for Socket APIs by doxygen 1.8.4


Socket APIs: W5500

Modules
W5500

WHIZCHIP register defines and I/O functions of W5500. More...

Collaboration diagram for W5500:

Modules

WIZCHIP I/O functions
This supports the basic I/O functions for WIZCHIP register.
WIZCHIP register
WHIZCHIP register defines register group of W5500.

Detailed Description

WHIZCHIP register defines and I/O functions of W5500.

  • WIZCHIP register : Common register and Socket register
  • WIZCHIP I/O functions : Basic I/O function, Common register access functions and Socket register access functions
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP I/O functions

Modules
WIZCHIP I/O functions
W5500

This supports the basic I/O functions for WIZCHIP register. More...

Collaboration diagram for WIZCHIP I/O functions:

Modules

Basic I/O function
These are basic input/output functions to read values from register or write values to register.
Common register access functions
These are functions to access common registers.
Socket register access functions
These are functions to access socket registers.

Detailed Description

This supports the basic I/O functions for WIZCHIP register.

  • Basic I/O function
    WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()

  • Common register access functions
    1. Mode
      getMR(), setMR()
    2. Interrupt
      getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL()
    3. Network Information
      getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
    4. Retransmission
      getRCR(), setRCR(), getRTR(), setRTR()
    5. PPPoE
      getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU()
    6. ICMP packet
      getUIPR(), getUPORTR()
    7. etc.
      getPHYCFGR(), setPHYCFGR(), getVERSIONR()

  • Socket register access functions
    1. SOCKET control
      getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
    2. SOCKET information
      getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT() getSn_MSSR(), setSn_MSSR()
    3. SOCKET communication
      getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE()
      getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR()
      getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR()
      getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR()
    4. IP header field
      getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS()
      getSn_TTL(), setSn_TTL()
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Basic I/O function

Functions
Basic I/O function
WIZCHIP I/O functions

These are basic input/output functions to read values from register or write values to register. More...

Collaboration diagram for Basic I/O function:

Functions

uint8_t | WIZCHIP_READ (uint32_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

These are basic input/output functions to read values from register or write values to register.

Function Documentation

uint8_t WIZCHIP_READ ( uint32_t AddrSel)

It reads 1 byte value from a register.

Parameters
AddrSel Register address
Returns
The value of register

Definition at line 74 of file w5200.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_IF::_read_burst, __WIZCHIP::_IF::_read_byte, __WIZCHIP::_CS::_select, _W5200_SPI_READ_, _W5500_SPI_READ_, _W5500_SPI_VDM_OP_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, and WIZCHIP_CRITICAL_EXIT.

void WIZCHIP_WRITE | ( | uint32_t | AddrSel,
 |  | uint8_t | wb
 | ) |  |

It writes 1 byte value to a register.

Parameters
AddrSel | Register address
wb | Write data
Returns
void

Definition at line 46 of file w5200.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, _W5200_SPI_WRITE_, _W5500_SPI_VDM_OP_, _W5500_SPI_WRITE_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, and WIZCHIP_CRITICAL_EXIT.

void WIZCHIP_READ_BUF | ( | uint32_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It reads sequence data from registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to read data
len | Data length

Definition at line 141 of file w5200.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_IF::_read_burst, __WIZCHIP::_IF::_read_byte, __WIZCHIP::_CS::_select, _W5200_SPI_READ_, _W5500_SPI_READ_, _W5500_SPI_VDM_OP_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, MR, MR_AI, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, WIZCHIP_CRITICAL_EXIT, WIZCHIP_READ(), and WIZCHIP_WRITE().

void WIZCHIP_WRITE_BUF | ( | uint32_t | AddrSel,
 |  | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

It writes sequence data to registers.

Parameters
AddrSel | Register address
pBuf | Pointer buffer to write data
len | Data length

Definition at line 108 of file w5200.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, _W5200_SPI_WRITE_, _W5500_SPI_VDM_OP_, _W5500_SPI_WRITE_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::CS, __WIZCHIP::IF, MR, MR_AI, __WIZCHIP::_IF::SPI, WIZCHIP, WIZCHIP_CRITICAL_ENTER, WIZCHIP_CRITICAL_EXIT, WIZCHIP_READ(), and WIZCHIP_WRITE().

void wiz_send_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to internal TX memory.

This function reads the Tx write pointer register and after that, it copies the wizdata(pointer buffer) of the length of len(variable) bytes to internal TX memory and updates the Tx write pointer register. This function is being called by send() and sendto() function also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
wizdata | Pointer buffer to write data
len | Data length
See Also
wiz_recv_data()

It copies data to internal TX memory.

This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer register. User should read upper byte first and lower byte later to get proper value. And this function is being used for copy the data form application buffer to Transmite buffer of the chip. It calculate the actual physical address where one has to write the data in transmite buffer. Here also take care of the condition while it exceed the Tx memory uper-bound of socket.

This function reads the Tx write pointer register and after that, it copies the wizdata(pointer buffer) of the length of len(variable) bytes to internal TX memory and updates the Tx write pointer register. This function is being called by send() and sendto() function also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to write data
len | Data length
See Also
wiz_recv_data()

It copies data to internal TX memory.

This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer register. User should read upper byte first and lower byte later to get proper value. And this function is being used for copy the data form application buffer to Transmite buffer of the chip. It calculate the actual physical address where one has to write the data in transmite buffer. Here also take care of the condition while it exceed the Tx memory uper-bound of socket.

Definition at line 254 of file w5100.c.

References getSn_TX_WR, getSn_TxBASE(), getSn_TxMASK, getSn_TxMAX, setSn_TX_WR, WIZCHIP_TXBUF_BLOCK, and WIZCHIP_WRITE_BUF().

Referenced by send(), and sendto().

void wiz_recv_data | ( | uint8_t | sn,
 |  | uint8_t * | wizdata,
 |  | uint16_t | len
 | ) |  |

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after that, it copies the received data from internal RX memory to wizdata(pointer variable) of the length of len(variable) bytes. This function is being called by recv() also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
wizdata | Pointer buffer to read data
len | Data length
See Also
wiz_send_data()

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after copy the data from receive buffer update the Rx write pointer register. User should read upper byte first and lower byte later to get proper value. It calculate the actual physical address where one has to read the data from Receive buffer. Here also take care of the condition while it exceed the Rx memory uper-bound of socket.

This function read the Rx read pointer register and after that, it copies the received data from internal RX memory to wizdata(pointer variable) of the length of len(variable) bytes. This function is being called by recv() also.

Note
User should read upper byte first and lower byte later to get proper value.
Parameters
sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
wizdata | Pointer buffer to read data
len | Data length
See Also
wiz_send_data()

It copies data to your buffer from internal RX memory.

This function read the Rx read pointer register and after copy the data from receive buffer update the Rx write pointer register. User should read upper byte first and lower byte later to get proper value. It calculate the actual physical address where one has to read the data from Receive buffer. Here also take care of the condition while it exceed the Rx memory uper-bound of socket.

Definition at line 296 of file w5100.c.

References getSn_RX_RD, getSn_RxBASE(), getSn_RxMASK, getSn_RxMAX, setSn_RX_RD, WIZCHIP_READ_BUF(), and WIZCHIP_RXBUF_BLOCK.

Referenced by recv(), and recvfrom().

void wiz_recv_ignore | ( | uint8_t | sn,
 |  | uint16_t | len
 | ) |  |

It discard the received data in RX memory.

It discards the data of the length of len(variable) bytes in internal RX memory.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
len | Data length

It discards the data of the length of len(variable) bytes in internal RX memory.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
len | Data length

Definition at line 328 of file w5100.c.

References getSn_RX_RD, and setSn_RX_RD.

Referenced by recvfrom().

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register access functions

Macros
Common register access functions
WIZCHIP I/O functions

These are functions to access common registers. More...

Collaboration diagram for Common register access functions:

Macros

#define | setMR(mr) WIZCHIP_WRITE(MR,mr)
Set Mode Register. More...
#define | getMR() WIZCHIP_READ(MR)
Get Mode Register. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set gateway IP address. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get gateway IP address. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)
Set subnet mask address. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get subnet mask address. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set local MAC address. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get local MAC address. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set local IP address. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get local IP address. More...
#define | setINTLEVEL(intlevel)
Set INTLEVEL register. More...
#define | getINTLEVEL() (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
Get INTLEVEL register. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xF0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xF0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setSIR(sir) WIZCHIP_WRITE(SIR, sir)
Set SIR register. More...
#define | getSIR() WIZCHIP_READ(SIR)
Get SIR register. More...
#define | setSIMR(simr) WIZCHIP_WRITE(SIMR, simr)
Set SIMR register. More...
#define | getSIMR() WIZCHIP_READ(SIMR)
Get SIMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...
#define | setPHAR(phar) WIZCHIP_WRITE_BUF(PHAR, phar, 6)
Set PHAR address. More...
#define | getPHAR(phar) WIZCHIP_READ_BUF(PHAR, phar, 6)
Get local IP address. More...
#define | setPSID(psid)
Set PSID register. More...
#define | getPSID() (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
Get PSID register. More...
#define | setPMRU(pmru)
Set PMRU register. More...
#define | getPMRU() (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
Get PMRU register. More...
#define | getUIPR(uipr) WIZCHIP_READ_BUF(UIPR,uipr,4)
Get unreachable IP address. More...
#define | getUPORTR() (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
Get UPORTR register. More...
#define | setPHYCFGR(phycfgr) WIZCHIP_WRITE(PHYCFGR, phycfgr)
Set PHYCFGR register. More...
#define | getPHYCFGR() WIZCHIP_READ(PHYCFGR)
Get PHYCFGR register. More...
#define | getVERSIONR() WIZCHIP_READ(VERSIONR)
Get VERSIONR register. More...

Detailed Description

These are functions to access common registers.

Macro Definition Documentation

#define setMR ( mr) WIZCHIP_WRITE(MR,mr)

Set Mode Register.

Parameters
(uint8_t)mr The value to be set.
See Also
getMR()

Definition at line 1243 of file w5500.h.

#define getMR ( ) WIZCHIP_READ(MR)

Get Mode Register.

Returns
uint8_t. The value of Mode register.
See Also
setMR()

Definition at line 1253 of file w5500.h.

#define setGAR ( gar) WIZCHIP_WRITE_BUF(GAR,gar,4)

Set gateway IP address.

Parameters
(uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.
See Also
getGAR()

Definition at line 1262 of file w5500.h.

#define getGAR ( gar) WIZCHIP_READ_BUF(GAR,gar,4)

Get gateway IP address.

Parameters
(uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.
See Also
setGAR()

Definition at line 1271 of file w5500.h.

#define setSUBR ( subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)

Set subnet mask address.

Parameters
(uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.
See Also
getSUBR()

Definition at line 1280 of file w5500.h.

#define getSUBR ( subr) WIZCHIP_READ_BUF(SUBR, subr, 4)

Get subnet mask address.

Parameters
(uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.
See Also
setSUBR()

Definition at line 1290 of file w5500.h.

#define setSHAR ( shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)

Set local MAC address.

Parameters
(uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.
See Also
getSHAR()

Definition at line 1299 of file w5500.h.

#define getSHAR ( shar) WIZCHIP_READ_BUF(SHAR, shar, 6)

Get local MAC address.

Parameters
(uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.
See Also
setSHAR()

Definition at line 1308 of file w5500.h.

#define setSIPR ( sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)

Set local IP address.

Parameters
(uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.
See Also
getSIPR()

Definition at line 1317 of file w5500.h.

#define getSIPR ( sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)

Get local IP address.

Parameters
(uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.
See Also
setSIPR()

Definition at line 1326 of file w5500.h.

#define setINTLEVEL ( intlevel)
Value:
{\
WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
}

Set INTLEVEL register.

Parameters
(uint16_t)intlevel Value to set INTLEVEL register.
See Also
getINTLEVEL()

Definition at line 1335 of file w5500.h.

#define getINTLEVEL ( ) (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))

Get INTLEVEL register.

Returns
uint16_t. Value of INTLEVEL register.
See Also
setINTLEVEL()

Definition at line 1352 of file w5500.h.

#define setIR ( ir) WIZCHIP_WRITE(IR, (ir & 0xF0))

Set IR register.

Parameters
(uint8_t)ir Value to set IR register.
See Also
getIR()

Definition at line 1361 of file w5500.h.

#define getIR ( ) (WIZCHIP_READ(IR) & 0xF0)

Get IR register.

Returns
uint8_t. Value of IR register.
See Also
setIR()

Definition at line 1370 of file w5500.h.

#define setIMR ( imr) WIZCHIP_WRITE(_IMR_, imr)

Set IMR register.

Parameters
(uint8_t)imr Value to set IMR register.
See Also
getIMR()

Definition at line 1378 of file w5500.h.

#define getIMR ( ) WIZCHIP_READ(_IMR_)

Get IMR register.

Returns
uint8_t. Value of IMR register.
See Also
setIMR()

Definition at line 1387 of file w5500.h.

#define setSIR ( sir) WIZCHIP_WRITE(SIR, sir)

Set SIR register.

Parameters
(uint8_t)sir Value to set SIR register.
See Also
getSIR()

Definition at line 1396 of file w5500.h.

#define getSIR ( ) WIZCHIP_READ(SIR)

Get SIR register.

Returns
uint8_t. Value of SIR register.
See Also
setSIR()

Definition at line 1405 of file w5500.h.

#define setSIMR ( simr) WIZCHIP_WRITE(SIMR, simr)

Set SIMR register.

Parameters
(uint8_t)simr Value to set SIMR register.
See Also
getSIMR()

Definition at line 1413 of file w5500.h.

#define getSIMR ( ) WIZCHIP_READ(SIMR)

Get SIMR register.

Returns
uint8_t. Value of SIMR register.
See Also
setSIMR()

Definition at line 1422 of file w5500.h.

#define setRTR ( rtr)
Value:
{\
WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
}

Set RTR register.

Parameters
(uint16_t)rtr Value to set RTR register.
See Also
getRTR()

Definition at line 1431 of file w5500.h.

#define getRTR ( ) (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))

Get RTR register.

Returns
uint16_t. Value of RTR register.
See Also
setRTR()

Definition at line 1447 of file w5500.h.

#define setRCR ( rcr) WIZCHIP_WRITE(_RCR_, rcr)

Set RCR register.

Parameters
(uint8_t)rcr Value to set RCR register.
See Also
getRCR()

Definition at line 1457 of file w5500.h.

#define getRCR ( ) WIZCHIP_READ(_RCR_)

Get RCR register.

Returns
uint8_t. Value of RCR register.
See Also
setRCR()

Definition at line 1466 of file w5500.h.

#define setPTIMER ( ptimer) WIZCHIP_WRITE(PTIMER, ptimer)

Set PTIMER register.

Parameters
(uint8_t)ptimer Value to set PTIMER register.
See Also
getPTIMER()

Definition at line 1477 of file w5500.h.

#define getPTIMER ( ) WIZCHIP_READ(PTIMER)

Get PTIMER register.

Returns
uint8_t. Value of PTIMER register.
See Also
setPTIMER()

Definition at line 1486 of file w5500.h.

#define setPMAGIC ( pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)

Set PMAGIC register.

Parameters
(uint8_t)pmagic Value to set PMAGIC register.
See Also
getPMAGIC()

Definition at line 1495 of file w5500.h.

#define getPMAGIC ( ) WIZCHIP_READ(PMAGIC)

Get PMAGIC register.

Returns
uint8_t. Value of PMAGIC register.
See Also
setPMAGIC()

Definition at line 1504 of file w5500.h.

#define setPHAR ( phar) WIZCHIP_WRITE_BUF(PHAR, phar, 6)

Set PHAR address.

Parameters
(uint8_t*)phar Pointer variable to set PPP destination MAC register address. It should be allocated 6 bytes.
See Also
getPHAR()

Definition at line 1513 of file w5500.h.

#define getPHAR ( phar) WIZCHIP_READ_BUF(PHAR, phar, 6)

Get local IP address.

Parameters
(uint8_t*)phar Pointer variable to PPP destination MAC register address. It should be allocated 6 bytes.
See Also
setPHAR()

Definition at line 1522 of file w5500.h.

#define setPSID ( psid)
Value:
{\
WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
}

Set PSID register.

Parameters
(uint16_t)psid Value to set PSID register.
See Also
getPSID()

Definition at line 1531 of file w5500.h.

#define getPSID ( ) (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))

Get PSID register.

Returns
uint16_t. Value of PSID register.
See Also
setPSID()

Definition at line 1548 of file w5500.h.

#define setPMRU ( pmru)
Value:
{ \
WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
}

Set PMRU register.

Parameters
(uint16_t)pmru Value to set PMRU register.
See Also
getPMRU()

Definition at line 1557 of file w5500.h.

#define getPMRU ( ) (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))

Get PMRU register.

Returns
uint16_t. Value of PMRU register.
See Also
setPMRU()

Definition at line 1573 of file w5500.h.

#define getUIPR ( uipr) WIZCHIP_READ_BUF(UIPR,uipr,4)

Get unreachable IP address.

Parameters
(uint8_t*)uipr Pointer variable to get unreachable IP address. It should be allocated 4 bytes.

Definition at line 1586 of file w5500.h.

#define getUPORTR ( ) (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))

Get UPORTR register.

Returns
uint16_t. Value of UPORTR register.

Definition at line 1599 of file w5500.h.

#define setPHYCFGR ( phycfgr) WIZCHIP_WRITE(PHYCFGR, phycfgr)

Set PHYCFGR register.

Parameters
(uint8_t)phycfgr Value to set PHYCFGR register.
See Also
getPHYCFGR()

Definition at line 1608 of file w5500.h.

Referenced by wizphy_reset(), wizphy_setphyconf(), and wizphy_setphypmode().

#define getPHYCFGR ( ) WIZCHIP_READ(PHYCFGR)

Get PHYCFGR register.

Returns
uint8_t. Value of PHYCFGR register.
See Also
setPHYCFGR()

Definition at line 1617 of file w5500.h.

Referenced by wizphy_getphyconf(), wizphy_getphylink(), wizphy_getphypmode(), wizphy_getphystat(), wizphy_reset(), and wizphy_setphypmode().

#define getVERSIONR ( ) WIZCHIP_READ(VERSIONR)

Get VERSIONR register.

Returns
uint8_t. Value of VERSIONR register.

Definition at line 1625 of file w5500.h.

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register access functions

Macros | Functions
Socket register access functions
WIZCHIP I/O functions

These are functions to access socket registers. More...

Collaboration diagram for Socket register access functions:

Macros

#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
Set Sn_IR register. More...
#define | getSn_IR(sn) (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
Get Sn_IR register. More...
#define | setSn_IMR(sn, imr) WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
Set Sn_IMR register. More...
#define | getSn_IMR(sn) (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
Get Sn_IMR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_MR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXBUF_SIZE(sn, rxbufsize) WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
Set Sn_RXBUF_SIZE register. More...
#define | getSn_RXBUF_SIZE(sn) WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
Get Sn_RXBUF_SIZE register. More...
#define | setSn_TXBUF_SIZE(sn, txbufsize) WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
Set Sn_TXBUF_SIZE register. More...
#define | getSn_TXBUF_SIZE(sn) WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
Get Sn_TXBUF_SIZE register. More...
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | setSn_KPALVTR(sn, kpalvt) WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
Set Sn_KPALVTR register. More...
#define | getSn_KPALVTR(sn) WIZCHIP_READ(Sn_KPALVTR(sn))
Get Sn_KPALVTR register. More...

Functions

uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...

Detailed Description

These are functions to access socket registers.

Macro Definition Documentation

#define setSn_MR | ( | sn,
 |  | mr
 | ) | WIZCHIP_WRITE(Sn_MR(sn),mr)

Set Sn_MR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)mr | Value to set Sn_MR
See Also
getSn_MR()

Definition at line 1640 of file w5500.h.

#define getSn_MR ( sn) WIZCHIP_READ(Sn_MR(sn))

Get Sn_MR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_MR.
See Also
setSn_MR()

Definition at line 1650 of file w5500.h.

#define setSn_CR | ( | sn,
 |  | cr
 | ) | WIZCHIP_WRITE(Sn_CR(sn), cr)

Set Sn_CR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)cr | Value to set Sn_CR
See Also
getSn_CR()

Definition at line 1660 of file w5500.h.

#define getSn_CR ( sn) WIZCHIP_READ(Sn_CR(sn))

Get Sn_CR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_CR.
See Also
setSn_CR()

Definition at line 1670 of file w5500.h.

#define setSn_IR | ( | sn,
 |  | ir
 | ) | WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))

Set Sn_IR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)ir | Value to set Sn_IR
See Also
getSn_IR()

Definition at line 1680 of file w5500.h.

#define getSn_IR ( sn) (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)

Get Sn_IR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_IR.
See Also
setSn_IR()

Definition at line 1690 of file w5500.h.

#define setSn_IMR | ( | sn,
 |  | imr
 | ) | WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))

Set Sn_IMR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)imr | Value to set Sn_IMR
See Also
getSn_IMR()

Definition at line 1700 of file w5500.h.

#define getSn_IMR ( sn) (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)

Get Sn_IMR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_IMR.
See Also
setSn_IMR()

Definition at line 1710 of file w5500.h.

#define getSn_SR ( sn) WIZCHIP_READ(Sn_SR(sn))

Get Sn_SR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_SR.

Definition at line 1719 of file w5500.h.

#define setSn_PORT | ( | sn,
 |  | port
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
}

Set Sn_PORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)port | Value to set Sn_PORT.
See Also
getSn_PORT()

Definition at line 1729 of file w5500.h.

#define getSn_PORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))

Get Sn_PORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_PORT.
See Also
setSn_PORT()

Definition at line 1746 of file w5500.h.

#define setSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)

Set Sn_DHAR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t*)dhar | Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.
See Also
getSn_DHAR()

Definition at line 1756 of file w5500.h.

#define getSn_DHAR | ( | sn,
 |  | dhar
 | ) | WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)

Get Sn_MR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t*)dhar | Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.
See Also
setSn_DHAR()

Definition at line 1766 of file w5500.h.

#define setSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)

Set Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t*)dipr | Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.
See Also
getSn_DIPR()

Definition at line 1776 of file w5500.h.

#define getSn_DIPR | ( | sn,
 |  | dipr
 | ) | WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)

Get Sn_DIPR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t*)dipr | Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.
See Also
SetSn_DIPR()

Definition at line 1786 of file w5500.h.

#define setSn_DPORT | ( | sn,
 |  | dport
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
}

Set Sn_DPORT register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)dport | Value to set Sn_DPORT
See Also
getSn_DPORT()

Definition at line 1796 of file w5500.h.

#define getSn_DPORT ( sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))

Get Sn_DPORT register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_DPORT.
See Also
setSn_DPORT()

Definition at line 1813 of file w5500.h.

#define setSn_MSSR | ( | sn,
 |  | mss
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
}

Set Sn_MSSR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)mss | Value to set Sn_MSSR
See Also
setSn_MSSR()

Definition at line 1823 of file w5500.h.

#define getSn_MSSR ( sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))

Get Sn_MSSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_MSSR.
See Also
setSn_MSSR()

Definition at line 1840 of file w5500.h.

#define setSn_TOS | ( | sn,
 |  | tos
 | ) | WIZCHIP_WRITE(Sn_TOS(sn), tos)

Set Sn_TOS register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)tos | Value to set Sn_TOS
See Also
getSn_TOS()

Definition at line 1850 of file w5500.h.

#define getSn_TOS ( sn) WIZCHIP_READ(Sn_TOS(sn))

Get Sn_TOS register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_TOS.
See Also
setSn_TOS()

Definition at line 1860 of file w5500.h.

#define setSn_TTL | ( | sn,
 |  | ttl
 | ) | WIZCHIP_WRITE(Sn_TTL(sn), ttl)

Set Sn_TTL register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)ttl | Value to set Sn_TTL
See Also
getSn_TTL()

Definition at line 1870 of file w5500.h.

#define getSn_TTL ( sn) WIZCHIP_READ(Sn_TTL(sn))

Get Sn_TTL register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_TTL.
See Also
setSn_TTL()

Definition at line 1881 of file w5500.h.

#define setSn_RXBUF_SIZE | ( | sn,
 |  | rxbufsize
 | ) | WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)

Set Sn_RXBUF_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)rxbufsize | Value to set Sn_RXBUF_SIZE
See Also
getSn_RXBUF_SIZE()

Definition at line 1892 of file w5500.h.

#define getSn_RXBUF_SIZE ( sn) WIZCHIP_READ(Sn_RXBUF_SIZE(sn))

Get Sn_RXBUF_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_RXBUF_SIZE.
See Also
setSn_RXBUF_SIZE()

Definition at line 1903 of file w5500.h.

#define setSn_TXBUF_SIZE | ( | sn,
 |  | txbufsize
 | ) | WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)

Set Sn_TXBUF_SIZE register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)txbufsize | Value to set Sn_TXBUF_SIZE
See Also
getSn_TXBUF_SIZE()

Definition at line 1913 of file w5500.h.

#define getSn_TXBUF_SIZE ( sn) WIZCHIP_READ(Sn_TXBUF_SIZE(sn))

Get Sn_TXBUF_SIZE register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_TXBUF_SIZE.
See Also
setSn_TXBUF_SIZE()

Definition at line 1923 of file w5500.h.

#define getSn_TX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))

Get Sn_TX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_TX_RD.

Definition at line 1945 of file w5500.h.

#define setSn_TX_WR | ( | sn,
 |  | txwr
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
}

Set Sn_TX_WR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)txwr | Value to set Sn_TX_WR
See Also
GetSn_TX_WR()

Definition at line 1955 of file w5500.h.

#define getSn_TX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))

Get Sn_TX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_TX_WR.
See Also
setSn_TX_WR()

Definition at line 1972 of file w5500.h.

#define setSn_RX_RD | ( | sn,
 |  | rxrd
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
}

Set Sn_RX_RD register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)rxrd | Value to set Sn_RX_RD
See Also
getSn_RX_RD()

Definition at line 1992 of file w5500.h.

#define getSn_RX_RD ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))

Get Sn_RX_RD register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7. uint16_t. Value of Sn_RX_RD.
See Also
setSn_RX_RD()

Definition at line 2009 of file w5500.h.

#define getSn_RX_WR ( sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))

Get Sn_RX_WR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_RX_WR.

Definition at line 2023 of file w5500.h.

#define setSn_FRAG | ( | sn,
 |  | frag
 | ) |
Value:
{ \
WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
}

Set Sn_FRAG register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint16_t)frag | Value to set Sn_FRAG
See Also
getSn_FRAD()

Definition at line 2033 of file w5500.h.

#define getSn_FRAG ( sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))

Get Sn_FRAG register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_FRAG.
See Also
setSn_FRAG()

Definition at line 2050 of file w5500.h.

#define setSn_KPALVTR | ( | sn,
 |  | kpalvt
 | ) | WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)

Set Sn_KPALVTR register.

Parameters
(uint8_t)sn | Socket number. It should be 0 ~ 7.
(uint8_t)kpalvt | Value to set Sn_KPALVTR
See Also
getSn_KPALVTR()

Definition at line 2060 of file w5500.h.

Referenced by setsockopt().

#define getSn_KPALVTR ( sn) WIZCHIP_READ(Sn_KPALVTR(sn))

Get Sn_KPALVTR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint8_t. Value of Sn_KPALVTR.
See Also
setSn_KPALVTR()

Definition at line 2070 of file w5500.h.

Referenced by getsockopt(), and setsockopt().

Function Documentation

uint16_t getSn_TX_FSR ( uint8_t sn)

Get Sn_TX_FSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_TX_FSR.
Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_TX_FSR.

Definition at line 180 of file w5100.c.

References Sn_TX_FSR, WIZCHIP_OFFSET_INC, and WIZCHIP_READ().

Referenced by getsockopt(), recv(), send(), and sendto().

uint16_t getSn_RX_RSR ( uint8_t sn)

Get Sn_RX_RSR register.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Sn_RX_RSR.
Parameters
(uint8_t)sn Socket number. It should be 0 ~ _WIZCHIP_SOCK_NUM_.
Returns
uint16_t. Value of Sn_RX_RSR.

Definition at line 197 of file w5100.c.

References Sn_RX_RSR, WIZCHIP_OFFSET_INC, and WIZCHIP_READ().

Referenced by getsockopt(), recv(), and recvfrom().

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: WIZCHIP register

Modules
WIZCHIP register
W5500

WHIZCHIP register defines register group of W5500. More...

Collaboration diagram for WIZCHIP register:

Modules

Common register
Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
Socket register
Socket register group.
Socket register configures and control SOCKETn which is necessary to data communication.

Detailed Description

WHIZCHIP register defines register group of W5500.

  • Common register : Common register group
  • Socket register : SOCKET n register group
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Common register

Macros
Common register
WIZCHIP register

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc. More...

Collaboration diagram for Common register:

Macros

#define | MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Source MAC Register address(R/W) More...
#define | SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
Source IP Register address(R/W) More...
#define | INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Set Interrupt low level timer register address(R/W) More...
#define | IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Interrupt mask register(R/W) More...
#define | SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Socket Interrupt Register(R/W) More...
#define | SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
Retry count register(R/W) More...
#define | PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP LCP Request Timer register in PPPoE mode(R/W) More...
#define | PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP LCP Magic number register in PPPoE mode(R/W) More...
#define | PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Destination MAC Register address(R/W) More...
#define | PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Session Identification Register(R/W) More...
#define | PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Maximum Segment Size(MSS) register(R/W) More...
#define | UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Unreachable IP register address in UDP mode(R) More...
#define | UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
Unreachable Port register address in UDP mode(R) More...
#define | PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
PHY Status Register(R/W) More...
#define | VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
chip version register address(R) More...

Detailed Description

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.

See Also
MR : Mode register.
GAR, SUBR, SHAR, SIPR
INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
RTR, RCR : Data retransmission.
PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
UIPR, UPORTR : ICMP message.
PHYCFGR, VERSIONR : etc.

Macro Definition Documentation

#define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.

Each bit of MR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RST | Reserved | WOL | PB | PPPoE | Reserved | FARP | Reserved
  • MR_RST : Reset
  • MR_WOL : Wake on LAN
  • MR_PB : Ping block
  • MR_PPPOE : PPPoE mode
  • MR_FARP : Force ARP mode

Definition at line 210 of file w5500.h.

#define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Gateway IP Register address(R/W)

GAR configures the default gateway address.

Definition at line 217 of file w5500.h.

#define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Subnet mask Register address(R/W)

SUBR configures the subnet mask address.

Definition at line 224 of file w5500.h.

#define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source MAC Register address(R/W)

SHAR configures the source hardware address.

Definition at line 231 of file w5500.h.

#define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source IP Register address(R/W)

SIPR configures the source IP address.

Definition at line 238 of file w5500.h.

#define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Set Interrupt low level timer register address(R/W)

INTLEVEL configures the Interrupt Assert Time.

Definition at line 245 of file w5500.h.

#define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt Register(R/W)

IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00

Each bit of IR defined as follows.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CONFLICT | UNREACH | PPPoE | MP | Reserved | Reserved | Reserved | Reserved
  • IR_CONFLICT : IP conflict
  • IR_UNREACH : Destination unreachable
  • IR_PPPoE : PPPoE connection close
  • IR_MP : Magic packet

Definition at line 262 of file w5500.h.

#define _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt mask register(R/W)

IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR is and the corresponding bit of IR is an interrupt will be issued. In other words, if a bit of IMR is an interrupt will not be issued even if the corresponding bit of IR is

Each bit of IMR defined as the following.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IM_IR7 | IM_IR6 | IM_IR5 | IM_IR4 | Reserved | Reserved | Reserved | Reserved
  • IM_IR7 : IP Conflict Interrupt Mask
  • IM_IR6 : Destination unreachable Interrupt Mask
  • IM_IR5 : PPPoE Close Interrupt Mask
  • IM_IR4 : Magic Packet Interrupt Mask

Definition at line 282 of file w5500.h.

#define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Register(R/W)

SIR indicates the interrupt status of Socket.
Each bit of SIR be still until Sn_IR is cleared by the host.
If Sn_IR is not equal to x00 the n-th bit of SIR is and INTn PIN is asserted until SIR is x00

Definition at line 290 of file w5500.h.

#define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Mask Register(R/W)

Each bit of SIMR corresponds to each bit of SIR. When a bit of SIMR is and the corresponding bit of SIR is Interrupt will be issued. In other words, if a bit of SIMR is an interrupt will be not issued even if the corresponding bit of SIR is

Definition at line 299 of file w5500.h.

#define _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Timeout register address( 1 is 100us )(R/W)

RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0or 000 And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5500 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5500 retransmits the packet or issues timeout.

Definition at line 311 of file w5500.h.

#define _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))

Retry count register(R/W)

RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR[TIMEOUT] = .

Definition at line 321 of file w5500.h.

#define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Request Timer register in PPPoE mode(R/W)

PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.

Definition at line 328 of file w5500.h.

#define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Magic number register in PPPoE mode(R/W)

PMAGIC configures the 4bytes magic number to be used in LCP negotiation.

Definition at line 335 of file w5500.h.

#define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Destination MAC Register address(R/W)

PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.

Definition at line 342 of file w5500.h.

#define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Session Identification Register(R/W)

PSID configures the PPPoE sever session ID acquired during PPPoE connection process.

Definition at line 349 of file w5500.h.

#define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Maximum Segment Size(MSS) register(R/W)

PMRU configures the maximum receive unit of PPPoE.

Definition at line 356 of file w5500.h.

#define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable IP register address in UDP mode(R)

W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes and UIPR & UPORTR indicates the destination IP address & port number respectively.

Definition at line 365 of file w5500.h.

#define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable Port register address in UDP mode(R)

W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes and UIPR & UPORTR indicates the destination IP address & port number respectively.

Definition at line 374 of file w5500.h.

#define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PHY Status Register(R/W)

PHYCFGR configures PHY operation mode and resets PHY. In addition, PHYCFGR indicates the status of PHY such as duplex, Speed, Link.

Definition at line 381 of file w5500.h.

#define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))

chip version register address(R)

VERSIONR always indicates the W5500 version as 0x04.

Definition at line 399 of file w5500.h.

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket register

Macros
Socket register
WIZCHIP register

Socket register group.
Socket register configures and control SOCKETn which is necessary to data communication. More...

Collaboration diagram for Socket register:

Macros

#define | Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
socket Mode register(R/W) More...
#define | Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket command register(R/W) More...
#define | Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket interrupt register(R) More...
#define | Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket status register(R) More...
#define | Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
source port register(R/W) More...
#define | Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer IP register address(R/W) More...
#define | Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer port register address(R/W) More...
#define | Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Receive memory size register(R/W) More...
#define | Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory size register(R/W) More...
#define | Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Received data size register(R) More...
#define | Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Write point of Receive memory(R) More...
#define | Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
socket interrupt mask register(R) More...
#define | Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Fragment field value in IP header register(R/W) More...
#define | Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Keep Alive Timer register(R/W) More...

Detailed Description

Socket register group.
Socket register configures and control SOCKETn which is necessary to data communication.

See Also
Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol.
Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication

Macro Definition Documentation

#define Sn_MR ( N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

socket Mode register(R/W)

Sn_MR configures the option or protocol type of Socket n.

Each bit of Sn_MR defined as the following.

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MULTI/MFEN | BCASTB | ND/MC/MMB | UCASTB/MIP6B | Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0]
  • Sn_MR_MULTI : Support UDP Multicasting
  • Sn_MR_BCASTB : Broadcast block in UDP Multicasting
  • Sn_MR_ND : No Delayed Ack(TCP) flag
  • Sn_MR_MC : IGMP version used in UDP mulitcasting
  • Sn_MR_MMB : Multicast Blocking in Sn_MR_MACRAW mode
  • Sn_MR_UCASTB : Unicast Block in UDP Multicating
  • Sn_MR_MIP6B : IPv6 packet Blocking in Sn_MR_MACRAW mode
  • Protocol
    Protocol[3] | Protocol[2] | Protocol[1] | Protocol[0] | Meaning
    0 | 0 | 0 | 0 | Closed
    0 | 0 | 0 | 1 | TCP
    0 | 0 | 1 | 0 | UDP
    0 | 1 | 0 | 0 | MACRAW
    • Sn_MR_MACRAW : MAC LAYER RAW SOCK
    • Sn_MR_UDP : UDP
    • Sn_MR_TCP : TCP
    • Sn_MR_CLOSE : Unused socket
      Note
      MACRAW mode should be only used in Socket 0.

Definition at line 433 of file w5500.h.

#define Sn_CR ( N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Socket command register(R/W)

This is used to set the command for Socket n such as OPEN, CLOSE, CONNECT, LISTEN, SEND, and RECEIVE.
After W5500 accepts the command, the Sn_CR register is automatically cleared to 0x00. Even though Sn_CR is cleared to 0x00, the command is still being processed.
To check whether the command is completed or not, please check the Sn_IR or Sn_SR.

  • Sn_CR_OPEN : Initialize or open socket.
  • Sn_CR_LISTEN : Wait connection request in TCP mode(Server mode)
  • Sn_CR_CONNECT : Send connection request in TCP mode(Client mode)
  • Sn_CR_DISCON : Send closing request in TCP mode.
  • Sn_CR_CLOSE : Close socket.
  • Sn_CR_SEND : Update TX buffer pointer and send data.
  • Sn_CR_SEND_MAC : Send data with MAC address, so without ARP process.
  • Sn_CR_SEND_KEEP : Send keep alive message.
  • Sn_CR_RECV : Update RX buffer pointer and receive data.

Definition at line 452 of file w5500.h.

#define Sn_IR ( N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Socket interrupt register(R)

Sn_IR indicates the status of Socket Interrupt such as establishment, termination, receiving data, timeout).
When an interrupt occurs and the corresponding bit of Sn_IMR is the corresponding bit of Sn_IR becomes
In order to clear the Sn_IR bit, the host should write the bit to

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Reserved | Reserved | Reserved | SEND_OK | TIMEOUT | RECV | DISCON | CON
  • Sn_IR_SENDOK : SEND_OK Interrupt
  • Sn_IR_TIMEOUT : TIMEOUT Interrupt
  • Sn_IR_RECV : RECV Interrupt
  • Sn_IR_DISCON : DISCON Interrupt
  • Sn_IR_CON : CON Interrupt

Definition at line 470 of file w5500.h.

#define Sn_SR ( N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Socket status register(R)

Sn_SR indicates the status of Socket n.
The status of Socket n is changed by Sn_CR or some special control packet as SYN, FIN packet in TCP.

Normal status
  • SOCK_CLOSED : Closed
  • SOCK_INIT : Initiate state
  • SOCK_LISTEN : Listen state
  • SOCK_ESTABLISHED : Success to connect
  • SOCK_CLOSE_WAIT : Closing state
  • SOCK_UDP : UDP socket
  • SOCK_MACRAW : MAC raw mode socket
Temporary status during changing the status of Socket n.
  • SOCK_SYNSENT : This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
  • SOCK_SYNRECV : It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
  • SOCK_FIN_WAIT : Connection state
  • SOCK_CLOSING : Closing state
  • SOCK_TIME_WAIT : Closing state
  • SOCK_LAST_ACK : Closing state

Definition at line 493 of file w5500.h.

#define Sn_PORT ( N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

source port register(R/W)

Sn_PORT configures the source port number of Socket n. It is valid when Socket n is used in TCP/UPD mode. It should be set before OPEN command is ordered.

Definition at line 501 of file w5500.h.

#define Sn_DHAR ( N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Peer MAC register address(R/W)

Sn_DHAR configures the destination hardware address of Socket n when using SEND_MAC command in UDP mode or it indicates that it is acquired in ARP-process by CONNECT/SEND command.

Definition at line 509 of file w5500.h.

#define Sn_DIPR ( N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Peer IP register address(R/W)

Sn_DIPR configures or indicates the destination IP address of Socket n. It is valid when Socket n is used in TCP/UDP mode. In TCP client mode, it configures an IP address of �TCP serverbefore CONNECT command. In TCP server mode, it indicates an IP address of �TCP clientafter successfully establishing connection. In UDP mode, it configures an IP address of peer to be received the UDP packet by SEND or SEND_MAC command.

Definition at line 519 of file w5500.h.

#define Sn_DPORT ( N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Peer port register address(R/W)

Sn_DPORT configures or indicates the destination port number of Socket n. It is valid when Socket n is used in TCP/UDP mode. In �TCP clientmode, it configures the listen port number of �TCP serverbefore CONNECT command. In �TCP Servermode, it indicates the port number of TCP client after successfully establishing connection. In UDP mode, it configures the port number of peer to be transmitted the UDP packet by SEND/SEND_MAC command.

Definition at line 529 of file w5500.h.

#define Sn_MSSR ( N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Maximum Segment Size(Sn_MSSR0) register address(R/W)

Sn_MSSR configures or indicates the MTU(Maximum Transfer Unit) of Socket n.

Definition at line 536 of file w5500.h.

#define Sn_TOS ( N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

IP Type of Service(TOS) Register(R/W)

Sn_TOS configures the TOS(Type Of Service field in IP Header) of Socket n. It is set before OPEN command.

Definition at line 546 of file w5500.h.

#define Sn_TTL ( N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

IP Time to live(TTL) Register(R/W)

Sn_TTL configures the TTL(Time To Live field in IP header) of Socket n. It is set before OPEN command.

Definition at line 553 of file w5500.h.

#define Sn_RXBUF_SIZE ( N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Receive memory size register(R/W)

Sn_RXBUF_SIZE configures the RX buffer block size of Socket n. Socket n RX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. If a different size is configured, the data cannot be normally received from a peer. Although Socket n RX Buffer Block size is initially configured to 2Kbytes, user can re-configure its size using Sn_RXBUF_SIZE. The total sum of Sn_RXBUF_SIZE can not be exceed 16Kbytes. When exceeded, the data reception error is occurred.

Definition at line 572 of file w5500.h.

#define Sn_TXBUF_SIZE ( N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Transmit memory size register(R/W)

Sn_TXBUF_SIZE configures the TX buffer block size of Socket n. Socket n TX Buffer Block size can be configured with 1,2,4,8, and 16 Kbytes. If a different size is configured, the data can�t be normally transmitted to a peer. Although Socket n TX Buffer Block size is initially configured to 2Kbytes, user can be re-configure its size using Sn_TXBUF_SIZE. The total sum of Sn_TXBUF_SIZE can not be exceed 16Kbytes. When exceeded, the data transmission error is occurred.

Definition at line 583 of file w5500.h.

#define Sn_TX_FSR ( N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Transmit free memory size register(R)

Sn_TX_FSR indicates the free size of Socket n TX Buffer Block. It is initialized to the configured size by Sn_TXBUF_SIZE. Data bigger than Sn_TX_FSR should not be saved in the Socket n TX Buffer because the bigger data overwrites the previous saved data not yet sent. Therefore, check before saving the data to the Socket n TX Buffer, and if data is equal or smaller than its checked size, transmit the data with SEND/SEND_MAC command after saving the data in Socket n TX buffer. But, if data is bigger than its checked size, transmit the data after dividing into the checked size and saving in the Socket n TX buffer.

Definition at line 594 of file w5500.h.

#define Sn_TX_RD ( N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Transmit memory read pointer register address(R)

Sn_TX_RD is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP. After its initialization, it is auto-increased by SEND command. SEND command transmits the saved data from the current Sn_TX_RD to the Sn_TX_WR in the Socket n TX Buffer. After transmitting the saved data, the SEND command increases the Sn_TX_RD as same as the Sn_TX_WR. If its increment value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 606 of file w5500.h.

#define Sn_TX_WR ( N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Transmit memory write pointer register address(R/W)

Sn_TX_WR is initialized by OPEN command. However, if Sn_MR(P[3:0]) is TCP mode(001, it is re-initialized while connecting with TCP.
It should be read or be updated like as follows.

  1. Read the starting address for saving the transmitting data.
  2. Save the transmitting data from the starting address of Socket n TX buffer.
  3. After saving the transmitting data, update Sn_TX_WR to the increased value as many as transmitting data size. If the increment value exceeds the maximum value 0xFFFF(greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.
  4. Transmit the saved data in Socket n TX Buffer by using SEND/SEND command

Definition at line 620 of file w5500.h.

#define Sn_RX_RSR ( N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Received data size register(R)

Sn_RX_RSR indicates the data size received and saved in Socket n RX Buffer. Sn_RX_RSR does not exceed the Sn_RXBUF_SIZE and is calculated as the difference between �Socket n RX Write Pointer (Sn_RX_WR)and �Socket n RX Read Pointer (Sn_RX_RD)

Definition at line 629 of file w5500.h.

#define Sn_RX_RD ( N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Read point of Receive memory(R/W)

Sn_RX_RD is initialized by OPEN command. Make sure to be read or updated as follows.

  1. Read the starting save address of the received data.
  2. Read data from the starting address of Socket n RX Buffer.
  3. After reading the received data, Update Sn_RX_RD to the increased value as many as the reading size. If the increment value exceeds the maximum value 0xFFFF, that is, is greater than 0x10000 and the carry bit occurs, update with the lower 16bits value ignored the carry bit.
  4. Order RECV command is for notifying the updated Sn_RX_RD to W5500.

Definition at line 642 of file w5500.h.

#define Sn_RX_WR ( N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Write point of Receive memory(R)

Sn_RX_WR is initialized by OPEN command and it is auto-increased by the data reception. If the increased value exceeds the maximum value 0xFFFF, (greater than 0x10000 and the carry bit occurs), then the carry bit is ignored and will automatically update with the lower 16bits value.

Definition at line 651 of file w5500.h.

#define Sn_IMR ( N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

socket interrupt mask register(R)

Sn_IMR masks the interrupt of Socket n. Each bit corresponds to each bit of Sn_IR. When a Socket n Interrupt is occurred and the corresponding bit of Sn_IMR is the corresponding bit of Sn_IR becomes When both the corresponding bit of Sn_IMR and Sn_IR are and the n-th bit of IR is Host is interrupted by asserted INTn PIN to low.

Definition at line 661 of file w5500.h.

#define Sn_FRAG ( N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Fragment field value in IP header register(R/W)

Sn_FRAG configures the FRAG(Fragment field in IP header).

Definition at line 668 of file w5500.h.

#define Sn_KPALVTR ( N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))

Keep Alive Timer register(R/W)

Sn_KPALVTR configures the transmitting timer of �KEEP ALIVE(KA)packet of SOCKETn. It is valid only in TCP mode, and ignored in other modes. The time unit is 5s. KA packet is transmittable after Sn_SR is changed to SOCK_ESTABLISHED and after the data is transmitted or received to/from a peer at least once. In case of 'Sn_KPALVTR > 0', W5500 automatically transmits KA packet after time-period for checking the TCP connection (Auto-keepalive-process). In case of 'Sn_KPALVTR = 0', Auto-keep-alive-process will not operate, and KA packet can be transmitted by SEND_KEEP command by the host (Manual-keep-alive-process). Manual-keep-alive-process is ignored in case of 'Sn_KPALVTR > 0'.

Definition at line 681 of file w5500.h.

Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Class List

  • Class List
  • Class Index
  • Class Members
Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
[detail level 12]
o C __WIZCHIP | The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions
| o C _CRIS |
| o C _CS |
| \ C _IF |
o C wiz_NetInfo_t |
o C wiz_NetTimeout_t |
\ C wiz_PhyConf_t |
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Class Index

  • Class List
  • Class Index
  • Class Members
Class Index
W | _
W
wiz_NetTimeout_t __WIZCHIP::_CRIS
wiz_PhyConf_t __WIZCHIP::_CS
wiz_NetInfo_t
_
__WIZCHIP::_IF
__WIZCHIP
W | _
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Class Members

  • Class List
  • Class Index
  • Class Members
  • All
  • Variables
Here is a list of all class members with links to the classes they belong to:
  • _deselect : __WIZCHIP::_CS
  • _enter : __WIZCHIP::_CRIS
  • _exit : __WIZCHIP::_CRIS
  • _read_burst : __WIZCHIP::_IF
  • _read_byte : __WIZCHIP::_IF
  • _select : __WIZCHIP::_CS
  • _write_burst : __WIZCHIP::_IF
  • _write_byte : __WIZCHIP::_IF
  • BUS : __WIZCHIP::_IF
  • by : wiz_PhyConf_t
  • CRIS : __WIZCHIP
  • CS : __WIZCHIP
  • dhcp : wiz_NetInfo_t
  • dns : wiz_NetInfo_t
  • duplex : wiz_PhyConf_t
  • gw : wiz_NetInfo_t
  • id : __WIZCHIP
  • IF : __WIZCHIP
  • if_mode : __WIZCHIP
  • ip : wiz_NetInfo_t
  • mac : wiz_NetInfo_t
  • mode : wiz_PhyConf_t
  • retry_cnt : wiz_NetTimeout_t
  • sn : wiz_NetInfo_t
  • speed : wiz_PhyConf_t
  • SPI : __WIZCHIP::_IF
  • time_100us : wiz_NetTimeout_t
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Class Members - Variables

  • Class List
  • Class Index
  • Class Members
  • All
  • Variables
  • _deselect : __WIZCHIP::_CS
  • _enter : __WIZCHIP::_CRIS
  • _exit : __WIZCHIP::_CRIS
  • _read_burst : __WIZCHIP::_IF
  • _read_byte : __WIZCHIP::_IF
  • _select : __WIZCHIP::_CS
  • _write_burst : __WIZCHIP::_IF
  • _write_byte : __WIZCHIP::_IF
  • BUS : __WIZCHIP::_IF
  • by : wiz_PhyConf_t
  • CRIS : __WIZCHIP
  • CS : __WIZCHIP
  • dhcp : wiz_NetInfo_t
  • dns : wiz_NetInfo_t
  • duplex : wiz_PhyConf_t
  • gw : wiz_NetInfo_t
  • id : __WIZCHIP
  • IF : __WIZCHIP
  • if_mode : __WIZCHIP
  • ip : wiz_NetInfo_t
  • mac : wiz_NetInfo_t
  • mode : wiz_PhyConf_t
  • retry_cnt : wiz_NetTimeout_t
  • sn : wiz_NetInfo_t
  • speed : wiz_PhyConf_t
  • SPI : __WIZCHIP::_IF
  • time_100us : wiz_NetTimeout_t
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: File List

  • File List
  • File Members
File List
Here is a list of all files with brief descriptions:
[detail level 123]
\ - Ethernet |
o - W5100 |
| o * w5100.c |
| \ * w5100.h | W5100 HAL Header File
o - W5200 |
| o * w5200.c | W5200 HAL Interface
| \ * w5200.h | W5200 HAL Header File
o - W5500 |
| o * w5500.c | W5500 HAL Interface
| \ * w5500.h | W5500 HAL Header File
o * socket.c | SOCKET APIs Implements file
o * socket.h | SOCKET APIs Header file
o * wizchip_conf.c | WIZCHIP Config Header File
\ * wizchip_conf.h | WIZCHIP Config Header File
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet Directory Reference

  • Ethernet
Ethernet Directory Reference

Directories

directory | W5100
directory | W5200
directory | W5500

Files

file | socket.c [code]
SOCKET APIs Implements file.
file | socket.h [code]
SOCKET APIs Header file.
file | wizchip_conf.c [code]
WIZCHIP Config Header File.
file | wizchip_conf.h [code]
WIZCHIP Config Header File.
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5100 Directory Reference

  • Ethernet
  • W5100
W5100 Directory Reference

Files

file | w5100.c [code]
file | w5100.h [code]
W5100 HAL Header File.
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5100/w5100.c File Reference

  • Ethernet
  • W5100
Functions
w5100.c File Reference
#include "w5100.h"
Include dependency graph for w5100.c:

Go to the source code of this file.

Functions

void | WIZCHIP_WRITE (uint16_t AddrSel, uint8_t wb)
This function writes the data into W5200 registers. More...
uint8_t | WIZCHIP_READ (uint16_t AddrSel)
This function reads the value from W5200 registers. More...
void | WIZCHIP_WRITE_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
This function writes into W5200 memory(Buffer) More...
void | WIZCHIP_READ_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
This function reads into W5200 memory(Buffer) More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint32_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint32_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
This function is being called by send() and sendto() function also. for copy the data form application buffer to Transmite buffer of the chip. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
This function is being called by recv() also. This function is being used for copy the data form Receive buffer of the chip to application buffer. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...
Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5100/w5100.h File Reference

  • Ethernet
  • W5100
Macros | Functions
w5100.h File Reference

W5100 HAL Header File. More...

#include <stdint.h>
#include "Ethernet/wizchip_conf.h"
Include dependency graph for w5100.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | _WIZCHIP_SN_BASE_ (0x0400)
#define | _WIZCHIP_SN_SIZE_ (0x0100)
#define | _WIZCHIP_IO_TXBUF_ (0x4000) /* Internal Tx buffer address of the iinchip */
#define | _WIZCHIP_IO_RXBUF_ (0x6000) /* Internal Rx buffer address of the iinchip */
#define | WIZCHIP_CREG_BLOCK 0x00
Common register block. More...
#define | WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
Socket N register block. More...
#define | WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
Increase offset address. More...
#define | _W5100_IO_BASE_ _WIZCHIP_IO_BASE_
#define | IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE(ADDR, VAL) WIZCHIP_WRITE(ADDR,VAL)
The defined for legacy chip driver. More...
#define | IINCHIP_READ_BUF(ADDR, BUF, LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE_BUF(ADDR, BUF, LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | MR (_W5100_IO_BASE_ + (0x0000))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5100_IO_BASE_ + (0x0001))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5100_IO_BASE_ + (0x0005))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5100_IO_BASE_ + (0x0009))
Source MAC Register address(R/W) More...
#define | SIPR (_W5100_IO_BASE_ + (0x000F))
Source IP Register address(R/W) More...
#define | IR (_W5100_IO_BASE_ + (0x0015))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5100_IO_BASE_ + (0x0016))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5100_IO_BASE_ + (0x0017))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5100_IO_BASE_ + (0x0019))
Retry count register(R/W) More...
#define | RMSR (_W5100_IO_BASE_ + (0x001A))
#define | TMSR (_W5100_IO_BASE_ + (0x001B))
#define | PATR (_W5100_IO_BASE_ + (0x001C))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PTIMER (_W5100_IO_BASE_ + (0x0028))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PMAGIC (_W5100_IO_BASE_ + (0x0029))
PPP LCP Magic number register in PPPoE mode(R) More...
#define | UIPR0 (_W5100_IO_BASE_ + (0x002A))
#define | UPORT0 (_W5100_IO_BASE + (0x002E))
#define | Sn_MR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))
socket Mode register(R/W) More...
#define | Sn_CR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))
Socket command register(R/W) More...
#define | Sn_IR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))
Socket interrupt register(R) More...
#define | Sn_SR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))
Socket status register(R) More...
#define | Sn_PORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))
source port register(R/W) More...
#define | Sn_DHAR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))
Peer IP register address(R/W) More...
#define | Sn_DPORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))
Peer port register address(R/W) More...
#define | Sn_MSSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_PROTO(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))
IP Protocol(PROTO) Register(R/W) More...
#define | Sn_TOS(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + 0x0015)
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_TX_FSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))
Received data size register(R) More...
#define | Sn_RX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))
Write point of Receive memory(R) More...
#define | MR_RST 0x80
Reset. More...
#define | MR_PB 0x10
Ping block. More...
#define | MR_PPPOE 0x08
Enable PPPoE. More...
#define | MR_AI 0x02
Address Auto-Increment in Indirect Bus Interface. More...
#define | MR_IND 0x01
Indirect Bus Interface mode. More...
#define | IR_CONFLICT 0x80
Check IP conflict. More...
#define | IR_UNREACH 0x40
Get the destination unreachable message in UDP sending. More...
#define | IR_PPPoE 0x20
Get the PPPoE close message. More...
#define | IR_SOCK(sn) (0x01 << sn)
check socket interrupt More...
#define | Sn_MR_CLOSE 0x00
Unused socket. More...
#define | Sn_MR_TCP 0x01
TCP. More...
#define | Sn_MR_UDP 0x02
UDP. More...
#define | Sn_MR_IPRAW 0x03
IP LAYER RAW SOCK. More...
#define | Sn_MR_MACRAW 0x04
MAC LAYER RAW SOCK. More...
#define | Sn_MR_PPPoE 0x05
PPPoE. More...
#define | Sn_MR_ND 0x20
No Delayed Ack(TCP), Multicast flag. More...
#define | Sn_MR_MC Sn_MR_ND
Support UDP Multicasting. More...
#define | Sn_MR_MF 0x40
MAC filter enable in Sn_MR_MACRAW mode. More...
#define | Sn_MR_MFEN Sn_MR_MF
#define | Sn_MR_MULTI 0x80
Support UDP Multicasting. More...
#define | Sn_CR_OPEN 0x01
Initialize or open socket. More...
#define | Sn_CR_LISTEN 0x02
Wait connection request in TCP mode(Server mode) More...
#define | Sn_CR_CONNECT 0x04
Send connection request in TCP mode(Client mode) More...
#define | Sn_CR_DISCON 0x08
Send closing request in TCP mode. More...
#define | Sn_CR_CLOSE 0x10
Close socket. More...
#define | Sn_CR_SEND 0x20
Update TX buffer pointer and send data. More...
#define | Sn_CR_SEND_MAC 0x21
Send data with MAC address, so without ARP process. More...
#define | Sn_CR_SEND_KEEP 0x22
Send keep alive message. More...
#define | Sn_CR_RECV 0x40
Update RX buffer pointer and receive data. More...
#define | Sn_CR_PCON 0x23
PPPoE connection. More...
#define | Sn_CR_PDISCON 0x24
Closes PPPoE connection. More...
#define | Sn_CR_PCR 0x25
REQ message transmission. More...
#define | Sn_CR_PCN 0x26
NAK massage transmission. More...
#define | Sn_CR_PCJ 0x27
REJECT message transmission. More...
#define | Sn_IR_PRECV 0x80
PPP Receive Interrupt. More...
#define | Sn_IR_PFAIL 0x40
PPP Fail Interrupt. More...
#define | Sn_IR_PNEXT 0x20
PPP Next Phase Interrupt. More...
#define | Sn_IR_SENDOK 0x10
SEND_OK Interrupt. More...
#define | Sn_IR_TIMEOUT 0x08
TIMEOUT Interrupt. More...
#define | Sn_IR_RECV 0x04
RECV Interrupt. More...
#define | Sn_IR_DISCON 0x02
DISCON Interrupt. More...
#define | Sn_IR_CON 0x01
CON Interrupt. More...
#define | SOCK_CLOSED 0x00
Closed. More...
#define | SOCK_INIT 0x13
Initiate state. More...
#define | SOCK_LISTEN 0x14
Listen state. More...
#define | SOCK_SYNSENT 0x15
Connection state. More...
#define | SOCK_SYNRECV 0x16
Connection state. More...
#define | SOCK_ESTABLISHED 0x17
Success to connect. More...
#define | SOCK_FIN_WAIT 0x18
Closing state. More...
#define | SOCK_CLOSING 0x1A
Closing state. More...
#define | SOCK_TIME_WAIT 0x1B
Closing state. More...
#define | SOCK_CLOSE_WAIT 0x1C
Closing state. More...
#define | SOCK_LAST_ACK 0x1D
Closing state. More...
#define | SOCK_UDP 0x22
UDP socket. More...
#define | SOCK_IPRAW 0x32
IP raw mode socket. More...
#define | SOCK_MACRAW 0x42
MAC raw mode socket. More...
#define | SOCK_PPPOE 0x5F
PPPoE mode socket. More...
#define | IPPROTO_IP 0
Dummy for IP. More...
#define | IPPROTO_ICMP 1
Control message protocol. More...
#define | IPPROTO_IGMP 2
Internet group management protocol. More...
#define | IPPROTO_GGP 3
GW^2 (deprecated) More...
#define | IPPROTO_TCP 6
TCP. More...
#define | IPPROTO_PUP 12
PUP. More...
#define | IPPROTO_UDP 17
UDP. More...
#define | IPPROTO_IDP 22
XNS idp. More...
#define | IPPROTO_ND 77
UNOFFICIAL net disk protocol. More...
#define | IPPROTO_RAW 255
Raw IP packet. More...
#define | WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
Enter a critical section. More...
#define | WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
Exit a critical section. More...
#define | setMR(mr) (*((uint8_t*)MR) = mr)
Set Mode Register. More...
#define | getMR() (*(uint8_t*)MR)
Get MR. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set GAR. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get GAR. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR,subr,4)
Set SUBR. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get SUBR. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set SHAR. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get SHAR. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set SIPR. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get SIPR. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xA0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xA0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | setRMSR(rmsr) WIZCHIP_WRITE(RMSR)
Get RMSR register. More...
#define | getRMSR() WIZCHIP_READ()
Get RMSR register. More...
#define | setTMSR(rmsr) WIZCHIP_WRITE(TMSR)
Get TMSR register. More...
#define | getPATR() (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
Get TMSR register. More...
#define | getPPPALGO() WIZCHIP_READ(PPPALGO)
Get PPPALGO register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...
#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), ir)
Set Sn_IR register. More...
#define | getSn_IR(sn) WIZCHIP_READ(Sn_IR(sn))
Get Sn_IR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_DHAR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_PROTO(sn, proto) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_PROTO register. More...
#define | getSn_PROTO(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_PROTO register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXMEM_SIZE(sn, rxmemsize) WIZCHIP_WRITE(RMSR, (WIZCHIP_READ(RMSR) & ~(0x03 << (2*sn))) | (rxmemsize << (2*sn)))
Set Sn_RXMEM_SIZE register. More...
#define | setSn_RXBUF_SIZE(sn, rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
#define | getSn_RXMEM_SIZE(sn) ((WIZCHIP_READ(RMSR) & (0x03 << (2*sn))) >> (2*sn))
Get Sn_RXMEM_SIZE register. More...
#define | getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
#define | setSn_TXMEM_SIZE(sn, txmemsize) WIZCHIP_WRITE(TMSR, (WIZCHIP_READ(TMSR) & ~(0x03 << (2*sn))) | (txmemsize << (2*sn)))
Set Sn_TXMEM_SIZE register. More...
#define | setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
#define | getSn_TXMEM_SIZE(sn) ((WIZCHIP_READ(TMSR) & (0x03 << (2*sn))) >> (2*sn))
Get Sn_TXMEM_SIZE register. More...
#define | getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | setSn_RX_WR(sn, rxwr)
Set Sn_RX_WR register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | getSn_RxMAX(sn) ((uint16_t)(1 << getSn_RXMEM_SIZE(sn)) << 10)
Get the max RX buffer size of socket sn. More...
#define | getSn_TxMAX(sn) ((uint16_t)(1 << getSn_TXMEM_SIZE(sn)) << 10)
Get the max TX buffer size of socket sn. More...
#define | getSn_RxMASK(sn) (getSn_RxMAX(sn) - 1)
Get the mask of socket sn RX buffer. More...
#define | getSn_TxMASK(sn) (getSn_TxMAX(sn) - 1)
Get the mask of socket sn TX buffer. More...

Functions

uint8_t | WIZCHIP_READ (uint16_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint16_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint16_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint32_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint32_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

W5100 HAL Header File.

Version
1.0.0
Date
2013/10/21
Revision history
<2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5100.h.

Macro Definition Documentation

#define _WIZCHIP_SN_BASE_ (0x0400)

Definition at line 46 of file w5100.h.

#define _WIZCHIP_SN_SIZE_ (0x0100)

Definition at line 47 of file w5100.h.

#define _WIZCHIP_IO_TXBUF_ (0x4000) /* Internal Tx buffer address of the iinchip */

Definition at line 48 of file w5100.h.

Referenced by getSn_TxBASE().

#define _WIZCHIP_IO_RXBUF_ (0x6000) /* Internal Rx buffer address of the iinchip */

Definition at line 49 of file w5100.h.

Referenced by getSn_RxBASE().

#define WIZCHIP_CREG_BLOCK 0x00

Common register block.

Definition at line 52 of file w5100.h.

#define WIZCHIP_SREG_BLOCK ( N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)

Socket N register block.

Definition at line 53 of file w5100.h.

#define WIZCHIP_OFFSET_INC | ( | ADDR,
 |  | N
 | ) | (ADDR + N)

Increase offset address.

Definition at line 55 of file w5100.h.

Referenced by getSn_RX_RSR(), and getSn_TX_FSR().

#define _W5100_IO_BASE_ _WIZCHIP_IO_BASE_

Definition at line 58 of file w5100.h.

Referenced by getSn_RxBASE(), and getSn_TxBASE().

#define IINCHIP_READ ( ADDR) WIZCHIP_READ(ADDR)

The defined for legacy chip driver.

Definition at line 72 of file w5100.h.

#define IINCHIP_WRITE | ( | ADDR,
 |  | VAL
 | ) | WIZCHIP_WRITE(ADDR,VAL)

The defined for legacy chip driver.

Definition at line 73 of file w5100.h.

#define IINCHIP_READ_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_READ_BUF(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 74 of file w5100.h.

#define IINCHIP_WRITE_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_WRITE(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 75 of file w5100.h.

#define RMSR (_W5100_IO_BASE_ + (0x001A))

Definition at line 275 of file w5100.h.

#define TMSR (_W5100_IO_BASE_ + (0x001B))

Definition at line 276 of file w5100.h.

#define UIPR0 (_W5100_IO_BASE_ + (0x002A))

Definition at line 302 of file w5100.h.

#define UPORT0 (_W5100_IO_BASE + (0x002E))

Definition at line 303 of file w5100.h.

#define MR_RST 0x80

Reset.

If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.reset

Definition at line 569 of file w5100.h.

Referenced by wizchip_sw_reset().

#define MR_PB 0x10

Ping block.

0 : Disable Ping block
1 : Enable Ping block
If the bit is it blocks the response to a ping request.ping block

Definition at line 578 of file w5100.h.

#define MR_PPPOE 0x08

Enable PPPoE.

0 : DisablePPPoE mode
1 : EnablePPPoE mode
If you use ADSL, this bit should be '1'.enable pppoe

Definition at line 586 of file w5100.h.

#define MR_AI 0x02

Address Auto-Increment in Indirect Bus Interface.

0 : Disable auto-increment
1 : Enable auto-incremente
At the Indirect Bus Interface mode, if this bit is set as ��1��, the address will be automatically increased by 1 whenever read and write are performed.auto-increment in indirect mode

Definition at line 595 of file w5100.h.

Referenced by WIZCHIP_READ_BUF(), and WIZCHIP_WRITE_BUF().

#define MR_IND 0x01

Indirect Bus Interface mode.

0 : Disable Indirect bus Interface mode
1 : Enable Indirect bus Interface mode
If this bit is set as ��1��, Indirect Bus Interface mode is set.enable indirect mode

Definition at line 603 of file w5100.h.

#define IR_CONFLICT 0x80

Check IP conflict.

Bit is set as when own source IP address is same with the sender IP address in the received ARP request.check ip confict

Definition at line 610 of file w5100.h.

#define IR_UNREACH 0x40

Get the destination unreachable message in UDP sending.

When receiving the ICMP (Destination port unreachable) packet, this bit is set as When this bit is Destination Information such as IP address and Port number may be checked with the corresponding UIPR & UPORTR.check destination unreachable

Definition at line 617 of file w5100.h.

#define IR_PPPoE 0x20

Get the PPPoE close message.

When PPPoE is disconnected during PPPoE mode, this bit is set.get the PPPoE close message

Definition at line 623 of file w5100.h.

#define IR_SOCK ( sn) (0x01 << sn)

check socket interrupt

Definition at line 625 of file w5100.h.

#define Sn_MR_CLOSE 0x00

Unused socket.

This configures the protocol mode of Socket n.unused socket

Definition at line 634 of file w5100.h.

#define Sn_MR_TCP 0x01

TCP.

This configures the protocol mode of Socket n.TCP

Definition at line 640 of file w5100.h.

Referenced by connect(), disconnect(), getsockopt(), listen(), recv(), send(), setsockopt(), and socket().

#define Sn_MR_UDP 0x02

UDP.

This configures the protocol mode of Socket n.UDP

Definition at line 646 of file w5100.h.

Referenced by recvfrom(), sendto(), and socket().

#define Sn_MR_IPRAW 0x03

IP LAYER RAW SOCK.

Definition at line 647 of file w5100.h.

Referenced by recvfrom(), and socket().

#define Sn_MR_MACRAW 0x04

MAC LAYER RAW SOCK.

This configures the protocol mode of Socket n.

Note
MACRAW mode should be only used in Socket 0.MAC LAYER RAW SOCK

Definition at line 654 of file w5100.h.

Referenced by recvfrom(), sendto(), and socket().

#define Sn_MR_PPPoE 0x05

PPPoE.

This configures the protocol mode of Socket n.

Note
PPPoE mode should be only used in Socket 0.PPPoE

Definition at line 661 of file w5100.h.

Referenced by recvfrom(), and socket().

#define Sn_MR_ND 0x20

No Delayed Ack(TCP), Multicast flag.

0 : Disable No Delayed ACK option
1 : Enable No Delayed ACK option
This bit is applied only during TCP mode (P[3:0] = 001).
When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.
When this bit is It sends the ACK packet after waiting for the timeout time configured by RTR.No Delayed Ack(TCP) flag

Definition at line 671 of file w5100.h.

#define Sn_MR_MC Sn_MR_ND

Support UDP Multicasting.

0 : using IGMP version 2
1 : using IGMP version 1
This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = '1') It configures the version for IGMP messages (Join/Leave/Report).Select IGMP version 1(0) or 2(1)

Definition at line 680 of file w5100.h.

#define Sn_MR_MF 0x40

MAC filter enable in Sn_MR_MACRAW mode.

0 : disable MAC Filtering
1 : enable MAC Filtering
This bit is applied only during MACRAW mode(P[3:0] = 100.
When set as W5100 can only receive broadcasting packet or packet sent to itself. When this bit is W5100 can receive all packets on Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended that this bit is set as for reducing host overhead to process the all received packets.Use MAC filter

Definition at line 692 of file w5100.h.

#define Sn_MR_MFEN Sn_MR_MF

Definition at line 693 of file w5100.h.

#define Sn_MR_MULTI 0x80

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010).
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.support multicating

Definition at line 705 of file w5100.h.

#define Sn_CR_OPEN 0x01

Initialize or open socket.

Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). The table below shows the value of Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0]) | Sn_SR
Sn_MR_CLOSE (000) | –
Sn_MR_TCP (001) | SOCK_INIT (0x13)
Sn_MR_UDP (010) | SOCK_UDP (0x22)
S0_MR_IPRAW (011) | SOCK_IPRAW (0x32)
S0_MR_MACRAW (100) | SOCK_MACRAW (0x42)
S0_MR_PPPoE (101) | SOCK_PPPoE (0x5F)

initialize or open socket

Definition at line 722 of file w5100.h.

Referenced by socket().

#define Sn_CR_LISTEN 0x02

Wait connection request in TCP mode(Server mode)

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP).// In this mode, Socket n operates as a 'TCP server' and waits for connection-request (SYN packet) from any 'TCP client'.// The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.// When a 'TCP client' connection request is successfully established, the Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes But when a 'TCP client' connection request is failed, Sn_IR(3) becomes and the status of Sn_SR changes to SOCK_CLOSED.wait connection request in tcp mode(Server mode)

Definition at line 733 of file w5100.h.

Referenced by listen().

#define Sn_CR_CONNECT 0x04

Send connection request in TCP mode(Client mode)

To connect, a connect-request (SYN packet) is sent to TCP serverconfigured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes

The connect-request fails in the following three cases.

  1. When a ARPTO occurs (Sn_IR[3] = '1') because destination hardware address is not acquired through the ARP-process.
  2. When a SYN/ACK packet is not received and TCPTO (Sn_IR(3) ='1')
  3. When a RST packet is received instead of a SYN/ACK packet. In these cases, Sn_SR is changed to SOCK_CLOSED.
    Note
    This is valid only in TCP mode and operates when Socket n acts as TCP clientsend connection request in tcp mode(Client mode)

Definition at line 745 of file w5100.h.

Referenced by connect().

#define Sn_CR_DISCON 0x08

Send closing request in TCP mode.

Regardless of TCP serveror TCP client the DISCON command processes the disconnect-process (Active closeor Passive close.

Active close
it transmits disconnect-request(FIN packet) to the connected peer
Passive close
When FIN packet is received from peer, a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), Sn_SR is changed to SOCK_CLOSED.
Otherwise, TCPTO occurs (Sn_IR(3)='1') and then Sn_SR is changed to SOCK_CLOSED.

Note
Valid only in TCP mode.send closing reqeuset in tcp mode

Definition at line 758 of file w5100.h.

Referenced by disconnect().

#define Sn_CR_CLOSE 0x10

Close socket.

Sn_SR is changed to SOCK_CLOSED.

Definition at line 764 of file w5100.h.

Referenced by close().

#define Sn_CR_SEND 0x20

Update TX buffer pointer and send data.

SEND transmits all the data in the Socket n TX buffer.
For more details, please refer to Socket n TX Free Size Register (Sn_TX_FSR), Socket n, TX Write Pointer Register(Sn_TX_WR), and Socket n TX Read Pointer Register(Sn_TX_RD).

Definition at line 772 of file w5100.h.

Referenced by send(), and sendto().

#define Sn_CR_SEND_MAC 0x21

Send data with MAC address, so without ARP process.

The basic operation is same as SEND.
Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).
But SEND_MAC transmits data without the automatic ARP-process.
In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process.

Note
Valid only in UDP mode.

Definition at line 782 of file w5100.h.

#define Sn_CR_SEND_KEEP 0x22

Send keep alive message.

It checks the connection status by sending 1byte keep-alive packet.
If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.

Note
Valid only in TCP mode.

Definition at line 790 of file w5100.h.

Referenced by setsockopt().

#define Sn_CR_RECV 0x40

Update RX buffer pointer and receive data.

RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD).
For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD).

Definition at line 798 of file w5100.h.

Referenced by recv(), and recvfrom().

#define Sn_CR_PCON 0x23

PPPoE connection.

PPPoE connection begins by transmitting PPPoE discovery packet

Definition at line 804 of file w5100.h.

#define Sn_CR_PDISCON 0x24

Closes PPPoE connection.

Closes PPPoE connection

Definition at line 810 of file w5100.h.

#define Sn_CR_PCR 0x25

REQ message transmission.

In each phase, it transmits REQ message.

Definition at line 816 of file w5100.h.

#define Sn_CR_PCN 0x26

NAK massage transmission.

In each phase, it transmits NAK message.

Definition at line 822 of file w5100.h.

#define Sn_CR_PCJ 0x27

REJECT message transmission.

In each phase, it transmits REJECT message.

Definition at line 828 of file w5100.h.

#define Sn_IR_PRECV 0x80

PPP Receive Interrupt.

PPP Receive Interrupts when the option which is not supported is received.

Definition at line 835 of file w5100.h.

#define Sn_IR_PFAIL 0x40

PPP Fail Interrupt.

PPP Fail Interrupts when PAP Authentication is failed.

Definition at line 841 of file w5100.h.

#define Sn_IR_PNEXT 0x20

PPP Next Phase Interrupt.

PPP Next Phase Interrupts when the phase is changed during ADSL connection process.

Definition at line 847 of file w5100.h.

#define Sn_IR_SENDOK 0x10

SEND_OK Interrupt.

This is issued when SEND command is completed.complete sending

Definition at line 853 of file w5100.h.

Referenced by send(), and sendto().

#define Sn_IR_TIMEOUT 0x08

TIMEOUT Interrupt.

This is issued when ARPTO or TCPTO occurs.assert timeout

Definition at line 859 of file w5100.h.

Referenced by connect(), disconnect(), send(), sendto(), and setsockopt().

#define Sn_IR_RECV 0x04

RECV Interrupt.

This is issued whenever data is received from a peer.

Definition at line 865 of file w5100.h.

#define Sn_IR_DISCON 0x02

DISCON Interrupt.

This is issued when FIN or FIN/ACK packet is received from a peer.

Definition at line 871 of file w5100.h.

#define Sn_IR_CON 0x01

CON Interrupt.

This is issued one time when the connection with peer is successful and then Sn_SR is changed to SOCK_ESTABLISHED.

Definition at line 877 of file w5100.h.

#define SOCK_CLOSED 0x00

Closed.

This indicates that Socket n is released.
When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status.closed

Definition at line 885 of file w5100.h.

Referenced by close(), connect(), disconnect(), listen(), recvfrom(), sendto(), and socket().

#define SOCK_INIT 0x13

Initiate state.

This indicates Socket n is opened with TCP mode.
It is changed to SOCK_INIT when Sn_MR(P[3:0]) = 001)and OPEN command is ordered.
After SOCK_INIT, user can use LISTEN /CONNECT command.init state

Definition at line 893 of file w5100.h.

#define SOCK_LISTEN 0x14

Listen state.

This indicates Socket n is operating as TCP servermode and waiting for connection-request (SYN packet) from a peer (TCP client).
It will change to SOCK_ESTABLISHED when the connection-request is successfully accepted.
Otherwise it will change to SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = '1').

Definition at line 901 of file w5100.h.

Referenced by listen().

#define SOCK_SYNSENT 0x15

Connection state.

This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.
If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.
Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = '1') is occurred.

Definition at line 910 of file w5100.h.

#define SOCK_SYNRECV 0x16

Connection state.

It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED.
If not, it changes to SOCK_CLOSED after timeout occurs (Sn_IR[TIMEOUT] = '1').

Definition at line 918 of file w5100.h.

#define SOCK_ESTABLISHED 0x17

Success to connect.

This indicates the status of the connection of Socket n.
It changes to SOCK_ESTABLISHED when the TCP SERVERprocessed the SYN packet from the TCP CLIENTduring SOCK_LISTEN, or when the CONNECT command is successful.
During SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.

Definition at line 927 of file w5100.h.

Referenced by connect(), recv(), and send().

#define SOCK_FIN_WAIT 0x18

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 935 of file w5100.h.

#define SOCK_CLOSING 0x1A

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 943 of file w5100.h.

#define SOCK_TIME_WAIT 0x1B

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 951 of file w5100.h.

#define SOCK_CLOSE_WAIT 0x1C

Closing state.

This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.
This is half-closing status, and data can be transferred.
For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.

Definition at line 959 of file w5100.h.

Referenced by recv(), and send().

#define SOCK_LAST_ACK 0x1D

Closing state.

This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.
It changes to SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (Sn_IR[TIMEOUT] = '1').

Definition at line 966 of file w5100.h.

#define SOCK_UDP 0x22

UDP socket.

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010).
It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.
Unlike TCP mode, data can be transfered without the connection-process.udp socket

Definition at line 974 of file w5100.h.

Referenced by sendto().

#define SOCK_IPRAW 0x32

IP raw mode socket.

TThe socket is opened in IPRAW mode. The SOCKET status is change to SOCK_IPRAW when Sn_MR (P3:P0) is Sn_MR_IPRAW and OPEN command is used.
IP Packet can be transferred without a connection similar to the UDP mode.ip raw mode socket

Definition at line 982 of file w5100.h.

#define SOCK_MACRAW 0x42

MAC raw mode socket.

This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.
It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100)and OPEN command is ordered.
Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.mac raw mode socket

Definition at line 990 of file w5100.h.

Referenced by sendto().

#define SOCK_PPPOE 0x5F

PPPoE mode socket.

It is the status that SOCKET0 is open as PPPoE mode. It is changed to SOCK_PPPoE in case of S0_CR=OPEN and S0_MR (P3:P0)=S0_MR_PPPoE.
It is temporarily used at the PPPoE connection.pppoe socket

Definition at line 999 of file w5100.h.

#define IPPROTO_IP 0

Dummy for IP.

Definition at line 1002 of file w5100.h.

#define IPPROTO_ICMP 1

Control message protocol.

Definition at line 1003 of file w5100.h.

#define IPPROTO_IGMP 2

Internet group management protocol.

Definition at line 1004 of file w5100.h.

#define IPPROTO_GGP 3

GW^2 (deprecated)

Definition at line 1005 of file w5100.h.

#define IPPROTO_TCP 6

TCP.

Definition at line 1006 of file w5100.h.

#define IPPROTO_PUP 12

PUP.

Definition at line 1007 of file w5100.h.

#define IPPROTO_UDP 17

UDP.

Definition at line 1008 of file w5100.h.

#define IPPROTO_IDP 22

XNS idp.

Definition at line 1009 of file w5100.h.

#define IPPROTO_ND 77

UNOFFICIAL net disk protocol.

Definition at line 1010 of file w5100.h.

#define IPPROTO_RAW 255

Raw IP packet.

Definition at line 1011 of file w5100.h.

#define WIZCHIP_CRITICAL_ENTER ( ) WIZCHIP.CRIS._enter()

Enter a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_EXIT()

Definition at line 1024 of file w5100.h.

Referenced by WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

#define WIZCHIP_CRITICAL_EXIT ( ) WIZCHIP.CRIS._exit()

Exit a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_ENTER()

Definition at line 1041 of file w5100.h.

Referenced by WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

#define setSn_RXBUF_SIZE | ( | sn,
 |  | rxmemsize
 | ) | setSn_RXMEM_SIZE(sn,rxmemsize)

Definition at line 1593 of file w5100.h.

Referenced by wizchip_init().

#define getSn_RXBUF_SIZE ( sn) getSn_RXMEM_SIZE(sn)

Definition at line 1604 of file w5100.h.

#define setSn_TXBUF_SIZE | ( | sn,
 |  | txmemsize
 | ) | setSn_TXMEM_SIZE(sn,txmemsize)

Definition at line 1615 of file w5100.h.

Referenced by wizchip_init().

#define getSn_TXBUF_SIZE ( sn) getSn_TXMEM_SIZE(sn)

Definition at line 1626 of file w5100.h.

Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5200 Directory Reference

  • Ethernet
  • W5200
W5200 Directory Reference

Files

file | w5200.c [code]
W5200 HAL Interface.
file | w5200.h [code]
W5200 HAL Header File.
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5200/w5200.c File Reference

  • Ethernet
  • W5200
Functions
w5200.c File Reference

W5200 HAL Interface. More...

#include "w5200.h"
Include dependency graph for w5200.c:

Go to the source code of this file.

Functions

void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
This function writes the data into W5200 registers. More...
uint8_t | WIZCHIP_READ (uint32_t AddrSel)
This function reads the value from W5200 registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
This function writes into W5200 memory(Buffer) More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
This function reads into W5200 memory(Buffer) More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint16_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint16_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
This function is being called by send() and sendto() function also. for copy the data form application buffer to Transmite buffer of the chip. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
This function is being called by recv() also. This function is being used for copy the data form Receive buffer of the chip to application buffer. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

W5200 HAL Interface.

Version
1.0.0
Date
2013/10/21
Revision history
<2013/10/21> 1st Release
Author
MidnightCow

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5200.c.

Generated on Thu Apr 9 2015 14:44:02 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5200/w5200.h File Reference

  • Ethernet
  • W5200
Macros | Functions
w5200.h File Reference

W5200 HAL Header File. More...

#include <stdint.h>
#include "Ethernet/wizchip_conf.h"
Include dependency graph for w5200.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | _WIZCHIP_SN_BASE_ (0x4000)
#define | _WIZCHIP_SN_SIZE_ (0x0100)
#define | _WIZCHIP_IO_TXBUF_ (0x8000) /* Internal Tx buffer address of the iinchip */
#define | _WIZCHIP_IO_RXBUF_ (0xC000) /* Internal Rx buffer address of the iinchip */
#define | _W5200_SPI_READ_ (0x00 << 7)
SPI interface Read operation in Control Phase. More...
#define | _W5200_SPI_WRITE_ (0x01 << 7)
SPI interface Write operation in Control Phase. More...
#define | WIZCHIP_CREG_BLOCK 0x00
Common register block. More...
#define | WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
Socket N register block. More...
#define | WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
Increase offset address. More...
#define | IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE(ADDR, VAL) WIZCHIP_WRITE(ADDR,VAL)
The defined for legacy chip driver. More...
#define | IINCHIP_READ_BUF(ADDR, BUF, LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE_BUF(ADDR, BUF, LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | MR (_W5200_IO_BASE_ + (0x0000))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5200_IO_BASE_ + (0x0001))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5200_IO_BASE_ + (0x0005))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5200_IO_BASE_ + (0x0009))
Source MAC Register address(R/W) More...
#define | SIPR (_W5200_IO_BASE_ + (0x000F))
Source IP Register address(R/W) More...
#define | IR (_W5200_IO_BASE_ + (0x0015))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5200_IO_BASE_ + (0x0016))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5200_IO_BASE_ + (0x0017))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5200_IO_BASE_ + (0x0019))
Retry count register(R/W) More...
#define | PATR (_W5200_IO_BASE_ + (0x001C))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PPPALGO (_W5200_IO_BASE_ + (0x001E))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | VERSIONR (_W5200_IO_BASE_ + (0x001F))
chip version register address(R) More...
#define | PTIMER (_W5200_IO_BASE_ + (0x0028))
PPP LCP Request Timer register in PPPoE mode(R) More...
#define | PMAGIC (_W5200_IO_BASE_ + (0x0029))
PPP LCP Magic number register in PPPoE mode(R) More...
#define | INTLEVEL (_W5200_IO_BASE_ + (0x0030))
Set Interrupt low level timer register address(R/W) More...
#define | IR2 (_W5200_IO_BASE_ + (0x0034))
Socket Interrupt Register(R/W) More...
#define | PHYSTATUS (_W5200_IO_BASE_ + (0x0035))
PHYSTATUS(R/W) More...
#define | IMR2 (_W5200_IO_BASE_ + (0x0036))
Interrupt mask register(R/W) More...
#define | Sn_MR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000))
socket Mode register(R/W) More...
#define | Sn_CR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001))
Socket command register(R/W) More...
#define | Sn_IR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002))
Socket interrupt register(R) More...
#define | Sn_SR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003))
Socket status register(R) More...
#define | Sn_PORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004))
source port register(R/W) More...
#define | Sn_DHAR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C))
Peer IP register address(R/W) More...
#define | Sn_DPORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010))
Peer port register address(R/W) More...
#define | Sn_MSSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_PROTO(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014))
IP Protocol(PROTO) Register(R/W) More...
#define | Sn_TOS(sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015)
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_RXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E))
Receive memory size register(R/W) More...
#define | Sn_TXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F))
Transmit memory size register(R/W) More...
#define | Sn_TX_FSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026))
Received data size register(R) More...
#define | Sn_RX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A))
Write point of Receive memory(R) More...
#define | Sn_IMR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C))
socket interrupt mask register(R) More...
#define | Sn_FRAG(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D))
Fragment field value in IP header register(R/W) More...
#define | MR_RST 0x80
Reset. More...
#define | MR_WOL 0x20
Wake on LAN. More...
#define | MR_PB 0x10
Ping block. More...
#define | MR_PPPOE 0x08
Enable PPPoE. More...
#define | MR_AI 0x02
Address Auto-Increment in Indirect Bus Interface. More...
#define | MR_IND 0x01
Indirect Bus Interface mode. More...
#define | IR_CONFLICT 0x80
Check IP conflict. More...
#define | IR_PPPoE 0x20
Get the PPPoE close message. More...
#define | PHYSTATUS_LINK 0x20
Link Status [Read Only]. More...
#define | PHYSTATUS_POWERSAVE 0x10
Power save mode of PHY. More...
#define | PHYSTATUS_POWERDOWN 0x08
Power down mode of PHY. More...
#define | Sn_MR_CLOSE 0x00
Unused socket. More...
#define | Sn_MR_TCP 0x01
TCP. More...
#define | Sn_MR_UDP 0x02
UDP. More...
#define | Sn_MR_IPRAW 0x03
IP LAYER RAW SOCK. More...
#define | Sn_MR_MACRAW 0x04
MAC LAYER RAW SOCK. More...
#define | Sn_MR_PPPOE 0x05
PPPoE. More...
#define | Sn_MR_ND 0x20
No Delayed Ack(TCP), Multicast flag. More...
#define | Sn_MR_MC Sn_MR_ND
Support UDP Multicasting. More...
#define | Sn_MR_MF 0x40
Multicast Blocking in Sn_MR_MACRAW mode. More...
#define | Sn_MR_MFEN Sn_MR_MF
#define | Sn_MR_MULTI 0x80
Support UDP Multicasting. More...
#define | Sn_CR_OPEN 0x01
Initialize or open socket. More...
#define | Sn_CR_LISTEN 0x02
Wait connection request in TCP mode(Server mode) More...
#define | Sn_CR_CONNECT 0x04
Send connection request in TCP mode(Client mode) More...
#define | Sn_CR_DISCON 0x08
Send closing request in TCP mode. More...
#define | Sn_CR_CLOSE 0x10
Close socket. More...
#define | Sn_CR_SEND 0x20
Update TX buffer pointer and send data. More...
#define | Sn_CR_SEND_MAC 0x21
Send data with MAC address, so without ARP process. More...
#define | Sn_CR_SEND_KEEP 0x22
Send keep alive message. More...
#define | Sn_CR_RECV 0x40
Update RX buffer pointer and receive data. More...
#define | Sn_CR_PCON 0x23
PPPoE connection. More...
#define | Sn_CR_PDISCON 0x24
Closes PPPoE connection. More...
#define | Sn_CR_PCR 0x25
REQ message transmission. More...
#define | Sn_CR_PCN 0x26
NAK massage transmission. More...
#define | Sn_CR_PCJ 0x27
REJECT message transmission. More...
#define | Sn_IR_PRECV 0x80
PPP Receive Interrupt. More...
#define | Sn_IR_PFAIL 0x40
PPP Fail Interrupt. More...
#define | Sn_IR_PNEXT 0x20
PPP Next Phase Interrupt. More...
#define | Sn_IR_SENDOK 0x10
SEND_OK Interrupt. More...
#define | Sn_IR_TIMEOUT 0x08
TIMEOUT Interrupt. More...
#define | Sn_IR_RECV 0x04
RECV Interrupt. More...
#define | Sn_IR_DISCON 0x02
DISCON Interrupt. More...
#define | Sn_IR_CON 0x01
CON Interrupt. More...
#define | SOCK_CLOSED 0x00
Closed. More...
#define | SOCK_INIT 0x13
Initiate state. More...
#define | SOCK_LISTEN 0x14
Listen state. More...
#define | SOCK_SYNSENT 0x15
Connection state. More...
#define | SOCK_SYNRECV 0x16
Connection state. More...
#define | SOCK_ESTABLISHED 0x17
Success to connect. More...
#define | SOCK_FIN_WAIT 0x18
Closing state. More...
#define | SOCK_CLOSING 0x1A
Closing state. More...
#define | SOCK_TIME_WAIT 0x1B
Closing state. More...
#define | SOCK_CLOSE_WAIT 0x1C
Closing state. More...
#define | SOCK_LAST_ACK 0x1D
Closing state. More...
#define | SOCK_UDP 0x22
UDP socket. More...
#define | SOCK_IPRAW 0x32
IP raw mode socket. More...
#define | SOCK_MACRAW 0x42
MAC raw mode socket. More...
#define | SOCK_PPPOE 0x5F
PPPoE mode socket. More...
#define | IPPROTO_IP 0
Dummy for IP. More...
#define | IPPROTO_ICMP 1
Control message protocol. More...
#define | IPPROTO_IGMP 2
Internet group management protocol. More...
#define | IPPROTO_GGP 3
GW^2 (deprecated) More...
#define | IPPROTO_TCP 6
TCP. More...
#define | IPPROTO_PUP 12
PUP. More...
#define | IPPROTO_UDP 17
UDP. More...
#define | IPPROTO_IDP 22
XNS idp. More...
#define | IPPROTO_ND 77
UNOFFICIAL net disk protocol. More...
#define | IPPROTO_RAW 255
Raw IP packet. More...
#define | WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
Enter a critical section. More...
#define | WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
Exit a critical section. More...
#define | setMR(mr) WIZCHIP_WRITE(MR,mr)
Set Mode Register. More...
#define | getMR() WIZCHIP_READ(MR)
Get MR. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set GAR. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get GAR. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)
Set SUBR. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get SUBR. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set SHAR. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get SHAR. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set SIPR. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get SIPR. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xA0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xA0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | getPATR() (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
Get PATR register. More...
#define | getPPPALGO() WIZCHIP_READ(PPPALGO)
Get PPPALGO register. More...
#define | getVERSIONR() WIZCHIP_READ(VERSIONR)
Get VERSIONR register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...
#define | setINTLEVEL(intlevel)
Set INTLEVEL register. More...
#define | getINTLEVEL() (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
Get INTLEVEL register. More...
#define | setIR2(ir2) WIZCHIP_WRITE(IR2, ir2)
Set IR2 register. More...
#define | setSIR(ir2) setIR2(ir2)
#define | getIR2() WIZCHIP_READ(IR2)
Get IR2 register. More...
#define | getSIR() getIR2()
#define | getPHYSTATUS() WIZCHIP_READ(PHYSTATUS)
Get PHYSTATUS register. More...
#define | setIMR2(imr2) WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))
Set IMR2 register. More...
#define | setSIMR(imr2) setIMR2(imr2)
#define | getIMR2() (WIZCHIP_READ(IMR2) & 0xA0)
Get IMR2 register. More...
#define | getSIMR() getIMR2()
#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), ir)
Set Sn_IR register. More...
#define | getSn_IR(sn) WIZCHIP_READ(Sn_IR(sn))
Get Sn_IR register. More...
#define | setSn_IMR(sn, imr) WIZCHIP_WRITE(Sn_IMR(sn), imr)
Set Sn_IMR register. More...
#define | getSn_IMR(sn) WIZCHIP_READ(Sn_IMR(sn))
Get Sn_IMR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_DHAR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_PROTO(sn, proto) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_PROTO register. More...
#define | getSn_PROTO(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_PROTO register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXMEM_SIZE(sn, rxmemsize) WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)
Set Sn_RXMEM_SIZE register. More...
#define | setSn_RXBUF_SIZE(sn, rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
#define | getSn_RXMEM_SIZE(sn) WIZCHIP_READ(Sn_RXMEM_SIZE(sn))
Get Sn_RXMEM_SIZE register. More...
#define | getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
#define | setSn_TXMEM_SIZE(sn, txmemsize) WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)
Set Sn_TXMEM_SIZE register. More...
#define | setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
#define | getSn_TXMEM_SIZE(sn) WIZCHIP_READ(Sn_TXMEM_SIZE(sn))
Get Sn_TXMEM_SIZE register. More...
#define | getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | setSn_RX_WR(sn, rxwr)
Set Sn_RX_WR register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_IMR(sn,imr) WIZCHIP_WRITE(Sn_IMR(sn), imr)
Set Sn_IMR register. More...
#define | getSn_IMR(sn) WIZCHIP_READ(Sn_IMR(sn))
Get Sn_IMR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | getSn_RxMAX(sn) ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)
Get the max RX buffer size of socket sn. More...
#define | getSn_TxMAX(sn) ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)
Get the max TX buffer size of socket sn. More...
#define | getSn_RxMASK(sn) ((uint16_t)getSn_RxMAX(sn) - 1)
Get the mask of socket sn RX buffer. More...
#define | getSn_TxMASK(sn) ((uint16_t)getSn_TxMAX(sn) - 1)
Get the mask of socket sn TX buffer. More...

Functions

uint8_t | WIZCHIP_READ (uint32_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
uint16_t | getSn_RxBASE (uint8_t sn)
Get the base address of socket sn RX buffer. More...
uint16_t | getSn_TxBASE (uint8_t sn)
Get the base address of socket sn TX buffer. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

W5200 HAL Header File.

Version
1.0.0
Date
2015/03/23
Revision history
<2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5200.h.

Macro Definition Documentation

#define _WIZCHIP_SN_BASE_ (0x4000)

Definition at line 46 of file w5200.h.

#define _WIZCHIP_SN_SIZE_ (0x0100)

Definition at line 47 of file w5200.h.

#define _WIZCHIP_IO_TXBUF_ (0x8000) /* Internal Tx buffer address of the iinchip */

Definition at line 48 of file w5200.h.

#define _WIZCHIP_IO_RXBUF_ (0xC000) /* Internal Rx buffer address of the iinchip */

Definition at line 49 of file w5200.h.

#define _W5200_SPI_READ_ (0x00 << 7)

SPI interface Read operation in Control Phase.

Definition at line 51 of file w5200.h.

Referenced by WIZCHIP_READ(), and WIZCHIP_READ_BUF().

#define _W5200_SPI_WRITE_ (0x01 << 7)

SPI interface Write operation in Control Phase.

Definition at line 52 of file w5200.h.

Referenced by WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

#define WIZCHIP_CREG_BLOCK 0x00

Common register block.

Definition at line 54 of file w5200.h.

#define WIZCHIP_SREG_BLOCK ( N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)

Socket N register block.

Definition at line 55 of file w5200.h.

#define WIZCHIP_OFFSET_INC | ( | ADDR,
 |  | N
 | ) | (ADDR + N)

Increase offset address.

Definition at line 57 of file w5200.h.

#define IINCHIP_READ ( ADDR) WIZCHIP_READ(ADDR)

The defined for legacy chip driver.

Definition at line 71 of file w5200.h.

#define IINCHIP_WRITE | ( | ADDR,
 |  | VAL
 | ) | WIZCHIP_WRITE(ADDR,VAL)

The defined for legacy chip driver.

Definition at line 72 of file w5200.h.

#define IINCHIP_READ_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_READ_BUF(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 73 of file w5200.h.

#define IINCHIP_WRITE_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_WRITE(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 74 of file w5200.h.

#define MR_RST 0x80

Reset.

If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.reset

Definition at line 682 of file w5200.h.

#define MR_WOL 0x20

Wake on LAN.

0 : Disable WOL mode
1 : Enable WOL mode
If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (Sn_MR) for opening Socket.)

Note
The magic packet over UDP supported by W5200 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.Wake on Lan

Definition at line 693 of file w5200.h.

#define MR_PB 0x10

Ping block.

0 : Disable Ping block
1 : Enable Ping block
If the bit is it blocks the response to a ping request.ping block

Definition at line 701 of file w5200.h.

#define MR_PPPOE 0x08

Enable PPPoE.

0 : DisablePPPoE mode
1 : EnablePPPoE mode
If you use ADSL, this bit should be '1'.enable pppoe

Definition at line 709 of file w5200.h.

#define MR_AI 0x02

Address Auto-Increment in Indirect Bus Interface.

0 : Disable auto-increment
1 : Enable auto-incremente
At the Indirect Bus Interface mode, if this bit is set as ��1��, the address will be automatically increased by 1 whenever read and write are performed.auto-increment in indirect mode

Definition at line 718 of file w5200.h.

#define MR_IND 0x01

Indirect Bus Interface mode.

0 : Disable Indirect bus Interface mode
1 : Enable Indirect bus Interface mode
If this bit is set as ��1��, Indirect Bus Interface mode is set.enable indirect mode

Definition at line 726 of file w5200.h.

#define IR_CONFLICT 0x80

Check IP conflict.

Bit is set as when own source IP address is same with the sender IP address in the received ARP request.check ip confict

Definition at line 733 of file w5200.h.

#define IR_PPPoE 0x20

Get the PPPoE close message.

When PPPoE is disconnected during PPPoE mode, this bit is set.get the PPPoE close message

Definition at line 739 of file w5200.h.

#define PHYSTATUS_LINK 0x20

Link Status [Read Only].

0: Link down
1: Link up

Definition at line 745 of file w5200.h.

Referenced by wizphy_getphylink().

#define PHYSTATUS_POWERSAVE 0x10

Power save mode of PHY.

0: Disable Power save mode
1: Enable Power save mode

Definition at line 751 of file w5200.h.

#define PHYSTATUS_POWERDOWN 0x08

Power down mode of PHY.

0: Disable Power down mode
1: Enable Power down mode

Definition at line 757 of file w5200.h.

Referenced by wizphy_getphypmode().

#define Sn_MR_CLOSE 0x00

Unused socket.

This configures the protocol mode of Socket n.unused socket

Definition at line 765 of file w5200.h.

#define Sn_MR_TCP 0x01

TCP.

This configures the protocol mode of Socket n.TCP

Definition at line 771 of file w5200.h.

#define Sn_MR_UDP 0x02

UDP.

This configures the protocol mode of Socket n.UDP

Definition at line 777 of file w5200.h.

#define Sn_MR_IPRAW 0x03

IP LAYER RAW SOCK.

Definition at line 778 of file w5200.h.

#define Sn_MR_MACRAW 0x04

MAC LAYER RAW SOCK.

This configures the protocol mode of Socket n.

Note
MACRAW mode should be only used in Socket 0.MAC LAYER RAW SOCK

Definition at line 785 of file w5200.h.

#define Sn_MR_PPPOE 0x05

PPPoE.

This configures the protocol mode of Socket n.

Note
PPPoE mode should be only used in Socket 0.PPPoE

Definition at line 792 of file w5200.h.

#define Sn_MR_ND 0x20

No Delayed Ack(TCP), Multicast flag.

0 : Disable No Delayed ACK option
1 : Enable No Delayed ACK option
This bit is applied only during TCP mode (P[3:0] = 001).
When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.
When this bit is It sends the ACK packet after waiting for the timeout time configured by RTR.No Delayed Ack(TCP) flag

Definition at line 802 of file w5200.h.

#define Sn_MR_MC Sn_MR_ND

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010).
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.Select IGMP version 1(0) or 2(1)

Definition at line 813 of file w5200.h.

#define Sn_MR_MF 0x40

Multicast Blocking in Sn_MR_MACRAW mode.

0 : using IGMP version 2
1 : using IGMP version 1
This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = '1') It configures the version for IGMP messages (Join/Leave/Report).Use MAC filter

Definition at line 822 of file w5200.h.

#define Sn_MR_MFEN Sn_MR_MF

Definition at line 823 of file w5200.h.

#define Sn_MR_MULTI 0x80

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010).
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.support multicating

Definition at line 834 of file w5200.h.

#define Sn_CR_OPEN 0x01

Initialize or open socket.

Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). The table below shows the value of Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0]) | Sn_SR
Sn_MR_CLOSE (000) | –
Sn_MR_TCP (001) | SOCK_INIT (0x13)
Sn_MR_UDP (010) | SOCK_UDP (0x22)
S0_MR_IPRAW (011) | SOCK_IPRAW (0x32)
S0_MR_MACRAW (100) | SOCK_MACRAW (0x42)
S0_MR_PPPoE (101) | SOCK_PPPoE (0x5F)

initialize or open socket

Definition at line 851 of file w5200.h.

#define Sn_CR_LISTEN 0x02

Wait connection request in TCP mode(Server mode)

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP).// In this mode, Socket n operates as a 'TCP server' and waits for connection-request (SYN packet) from any 'TCP client'.// The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN.// When a 'TCP client' connection request is successfully established, the Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes But when a 'TCP client' connection request is failed, Sn_IR(3) becomes and the status of Sn_SR changes to SOCK_CLOSED.wait connection request in tcp mode(Server mode)

Definition at line 862 of file w5200.h.

#define Sn_CR_CONNECT 0x04

Send connection request in TCP mode(Client mode)

To connect, a connect-request (SYN packet) is sent to TCP serverconfigured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes

The connect-request fails in the following three cases.

  1. When a ARPTO occurs (Sn_IR[3] = '1') because destination hardware address is not acquired through the ARP-process.
  2. When a SYN/ACK packet is not received and TCPTO (Sn_IR(3) ='1')
  3. When a RST packet is received instead of a SYN/ACK packet. In these cases, Sn_SR is changed to SOCK_CLOSED.
    Note
    This is valid only in TCP mode and operates when Socket n acts as TCP clientsend connection request in tcp mode(Client mode)

Definition at line 874 of file w5200.h.

#define Sn_CR_DISCON 0x08

Send closing request in TCP mode.

Regardless of TCP serveror TCP client the DISCON command processes the disconnect-process (Active closeor Passive close.

Active close
it transmits disconnect-request(FIN packet) to the connected peer
Passive close
When FIN packet is received from peer, a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), Sn_SR is changed to SOCK_CLOSED.
Otherwise, TCPTO occurs (Sn_IR(3)='1') and then Sn_SR is changed to SOCK_CLOSED.

Note
Valid only in TCP mode.send closing reqeuset in tcp mode

Definition at line 887 of file w5200.h.

#define Sn_CR_CLOSE 0x10

Close socket.

Sn_SR is changed to SOCK_CLOSED.

Definition at line 893 of file w5200.h.

#define Sn_CR_SEND 0x20

Update TX buffer pointer and send data.

SEND transmits all the data in the Socket n TX buffer.
For more details, please refer to Socket n TX Free Size Register (Sn_TX_FSR), Socket n, TX Write Pointer Register(Sn_TX_WR), and Socket n TX Read Pointer Register(Sn_TX_RD).

Definition at line 901 of file w5200.h.

#define Sn_CR_SEND_MAC 0x21

Send data with MAC address, so without ARP process.

The basic operation is same as SEND.
Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).
But SEND_MAC transmits data without the automatic ARP-process.
In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process.

Note
Valid only in UDP mode.

Definition at line 911 of file w5200.h.

#define Sn_CR_SEND_KEEP 0x22

Send keep alive message.

It checks the connection status by sending 1byte keep-alive packet.
If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.

Note
Valid only in TCP mode.

Definition at line 919 of file w5200.h.

#define Sn_CR_RECV 0x40

Update RX buffer pointer and receive data.

RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD).
For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD).

Definition at line 927 of file w5200.h.

#define Sn_CR_PCON 0x23

PPPoE connection.

PPPoE connection begins by transmitting PPPoE discovery packet

Definition at line 933 of file w5200.h.

#define Sn_CR_PDISCON 0x24

Closes PPPoE connection.

Closes PPPoE connection

Definition at line 939 of file w5200.h.

#define Sn_CR_PCR 0x25

REQ message transmission.

In each phase, it transmits REQ message.

Definition at line 945 of file w5200.h.

#define Sn_CR_PCN 0x26

NAK massage transmission.

In each phase, it transmits NAK message.

Definition at line 951 of file w5200.h.

#define Sn_CR_PCJ 0x27

REJECT message transmission.

In each phase, it transmits REJECT message.

Definition at line 957 of file w5200.h.

#define Sn_IR_PRECV 0x80

PPP Receive Interrupt.

PPP Receive Interrupts when the option which is not supported is received.

Definition at line 964 of file w5200.h.

#define Sn_IR_PFAIL 0x40

PPP Fail Interrupt.

PPP Fail Interrupts when PAP Authentication is failed.

Definition at line 970 of file w5200.h.

#define Sn_IR_PNEXT 0x20

PPP Next Phase Interrupt.

PPP Next Phase Interrupts when the phase is changed during ADSL connection process.

Definition at line 976 of file w5200.h.

#define Sn_IR_SENDOK 0x10

SEND_OK Interrupt.

This is issued when SEND command is completed.complete sending

Definition at line 982 of file w5200.h.

#define Sn_IR_TIMEOUT 0x08

TIMEOUT Interrupt.

This is issued when ARPTO or TCPTO occurs.assert timeout

Definition at line 988 of file w5200.h.

#define Sn_IR_RECV 0x04

RECV Interrupt.

This is issued whenever data is received from a peer.

Definition at line 994 of file w5200.h.

#define Sn_IR_DISCON 0x02

DISCON Interrupt.

This is issued when FIN or FIN/ACK packet is received from a peer.

Definition at line 1000 of file w5200.h.

#define Sn_IR_CON 0x01

CON Interrupt.

This is issued one time when the connection with peer is successful and then Sn_SR is changed to SOCK_ESTABLISHED.

Definition at line 1006 of file w5200.h.

#define SOCK_CLOSED 0x00

Closed.

This indicates that Socket n is released.
When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status.closed

Definition at line 1014 of file w5200.h.

#define SOCK_INIT 0x13

Initiate state.

This indicates Socket n is opened with TCP mode.
It is changed to SOCK_INIT when Sn_MR(P[3:0]) = 001)and OPEN command is ordered.
After SOCK_INIT, user can use LISTEN /CONNECT command.init state

Definition at line 1022 of file w5200.h.

#define SOCK_LISTEN 0x14

Listen state.

This indicates Socket n is operating as TCP servermode and waiting for connection-request (SYN packet) from a peer (TCP client).
It will change to SOCK_ESTABLISHED when the connection-request is successfully accepted.
Otherwise it will change to SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = '1').

Definition at line 1030 of file w5200.h.

#define SOCK_SYNSENT 0x15

Connection state.

This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.
If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.
Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = '1') is occurred.

Definition at line 1039 of file w5200.h.

#define SOCK_SYNRECV 0x16

Connection state.

It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED.
If not, it changes to SOCK_CLOSED after timeout occurs (Sn_IR[TIMEOUT] = '1').

Definition at line 1047 of file w5200.h.

#define SOCK_ESTABLISHED 0x17

Success to connect.

This indicates the status of the connection of Socket n.
It changes to SOCK_ESTABLISHED when the TCP SERVERprocessed the SYN packet from the TCP CLIENTduring SOCK_LISTEN, or when the CONNECT command is successful.
During SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.

Definition at line 1056 of file w5200.h.

#define SOCK_FIN_WAIT 0x18

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1064 of file w5200.h.

#define SOCK_CLOSING 0x1A

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1072 of file w5200.h.

#define SOCK_TIME_WAIT 0x1B

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1080 of file w5200.h.

#define SOCK_CLOSE_WAIT 0x1C

Closing state.

This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.
This is half-closing status, and data can be transferred.
For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.

Definition at line 1088 of file w5200.h.

#define SOCK_LAST_ACK 0x1D

Closing state.

This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.
It changes to SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (Sn_IR[TIMEOUT] = '1').

Definition at line 1095 of file w5200.h.

#define SOCK_UDP 0x22

UDP socket.

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010).
It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.
Unlike TCP mode, data can be transfered without the connection-process.udp socket

Definition at line 1103 of file w5200.h.

#define SOCK_IPRAW 0x32

IP raw mode socket.

TThe socket is opened in IPRAW mode. The SOCKET status is change to SOCK_IPRAW when Sn_MR (P3:P0) is Sn_MR_IPRAW and OPEN command is used.
IP Packet can be transferred without a connection similar to the UDP mode.ip raw mode socket

Definition at line 1111 of file w5200.h.

#define SOCK_MACRAW 0x42

MAC raw mode socket.

This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.
It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100)and OPEN command is ordered.
Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.mac raw mode socket

Definition at line 1119 of file w5200.h.

#define SOCK_PPPOE 0x5F

PPPoE mode socket.

It is the status that SOCKET0 is open as PPPoE mode. It is changed to SOCK_PPPoE in case of S0_CR=OPEN and S0_MR (P3:P0)=S0_MR_PPPoE.
It is temporarily used at the PPPoE connection.pppoe socket

Definition at line 1128 of file w5200.h.

#define IPPROTO_IP 0

Dummy for IP.

Definition at line 1131 of file w5200.h.

#define IPPROTO_ICMP 1

Control message protocol.

Definition at line 1132 of file w5200.h.

#define IPPROTO_IGMP 2

Internet group management protocol.

Definition at line 1133 of file w5200.h.

#define IPPROTO_GGP 3

GW^2 (deprecated)

Definition at line 1134 of file w5200.h.

#define IPPROTO_TCP 6

TCP.

Definition at line 1135 of file w5200.h.

#define IPPROTO_PUP 12

PUP.

Definition at line 1136 of file w5200.h.

#define IPPROTO_UDP 17

UDP.

Definition at line 1137 of file w5200.h.

#define IPPROTO_IDP 22

XNS idp.

Definition at line 1138 of file w5200.h.

#define IPPROTO_ND 77

UNOFFICIAL net disk protocol.

Definition at line 1139 of file w5200.h.

#define IPPROTO_RAW 255

Raw IP packet.

Definition at line 1140 of file w5200.h.

#define WIZCHIP_CRITICAL_ENTER ( ) WIZCHIP.CRIS._enter()

Enter a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_EXIT()

Definition at line 1153 of file w5200.h.

#define WIZCHIP_CRITICAL_EXIT ( ) WIZCHIP.CRIS._exit()

Exit a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_ENTER()

Definition at line 1170 of file w5200.h.

#define setSIR ( ir2) setIR2(ir2)

Definition at line 1471 of file w5200.h.

Referenced by wizchip_clrinterrupt().

#define getSIR ( ) getIR2()

Definition at line 1481 of file w5200.h.

Referenced by wizchip_getinterrupt().

#define setSIMR ( imr2) setIMR2(imr2)

Definition at line 1499 of file w5200.h.

Referenced by wizchip_setinterruptmask().

#define getSIMR ( ) getIMR2()

Definition at line 1509 of file w5200.h.

Referenced by wizchip_getinterruptmask().

#define setSn_RXBUF_SIZE | ( | sn,
 |  | rxmemsize
 | ) | setSn_RXMEM_SIZE(sn,rxmemsize)

Definition at line 1778 of file w5200.h.

#define getSn_RXBUF_SIZE ( sn) getSn_RXMEM_SIZE(sn)

Definition at line 1790 of file w5200.h.

#define setSn_TXBUF_SIZE | ( | sn,
 |  | txmemsize
 | ) | setSn_TXMEM_SIZE(sn,txmemsize)

Definition at line 1802 of file w5200.h.

#define getSn_TXBUF_SIZE ( sn) getSn_TXMEM_SIZE(sn)

Definition at line 1814 of file w5200.h.

Generated on Thu Apr 9 2015 14:44:02 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5500 Directory Reference

  • Ethernet
  • W5500
W5500 Directory Reference

Files

file | w5500.c [code]
W5500 HAL Interface.
file | w5500.h [code]
W5500 HAL Header File.
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5500/w5500.c File Reference

  • Ethernet
  • W5500
Macros | Functions
w5500.c File Reference

W5500 HAL Interface. More...

#include "w5500.h"
Include dependency graph for w5500.c:

Go to the source code of this file.

Macros

#define | _W5500_SPI_VDM_OP_ 0x00
#define | _W5500_SPI_FDM_OP_LEN1_ 0x01
#define | _W5500_SPI_FDM_OP_LEN2_ 0x02
#define | _W5500_SPI_FDM_OP_LEN4_ 0x03

Functions

uint8_t | WIZCHIP_READ (uint32_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

W5500 HAL Interface.

Version
1.0.2
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2014/05/01> V1.0.2
  1. Implicit type casting -> Explicit type casting. Refer to M20140501 Fixed the problem on porting into under 32bit MCU Issued by Mathias ClauBen, wizwiki forum ID Think01 and bobh Thank for your interesting and serious advices. <2013/12/20> V1.0.1
  1. Remove warning
  2. WIZCHIP_READ_BUF WIZCHIP_WRITE_BUF in case WIZCHIP_IO_MODE_SPI_FDM for loop optimized(removed). refer to M20131220 <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5500.c.

Macro Definition Documentation

#define _W5500_SPI_VDM_OP_ 0x00

Definition at line 57 of file w5500.c.

Referenced by WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

#define _W5500_SPI_FDM_OP_LEN1_ 0x01

Definition at line 58 of file w5500.c.

#define _W5500_SPI_FDM_OP_LEN2_ 0x02

Definition at line 59 of file w5500.c.

#define _W5500_SPI_FDM_OP_LEN4_ 0x03

Definition at line 60 of file w5500.c.

Generated on Thu Apr 9 2015 14:44:02 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5500/w5500.h File Reference

  • Ethernet
  • W5500
Macros | Functions
w5500.h File Reference

W5500 HAL Header File. More...

#include <stdint.h>
#include "wizchip_conf.h"
Include dependency graph for w5500.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | _W5500_IO_BASE_ 0x00000000
#define | _W5500_SPI_READ_ (0x00 << 2)
#define | _W5500_SPI_WRITE_ (0x01 << 2)
#define | WIZCHIP_CREG_BLOCK 0x00
#define | WIZCHIP_SREG_BLOCK(N) (1+4*N)
#define | WIZCHIP_TXBUF_BLOCK(N) (2+4*N)
#define | WIZCHIP_RXBUF_BLOCK(N) (3+4*N)
#define | WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8))
#define | IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE(ADDR, VAL) WIZCHIP_WRITE(ADDR,VAL)
The defined for legacy chip driver. More...
#define | IINCHIP_READ_BUF(ADDR, BUF, LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | IINCHIP_WRITE_BUF(ADDR, BUF, LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
The defined for legacy chip driver. More...
#define | MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
#define | GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Gateway IP Register address(R/W) More...
#define | SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Subnet mask Register address(R/W) More...
#define | SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Source MAC Register address(R/W) More...
#define | SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
Source IP Register address(R/W) More...
#define | INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Set Interrupt low level timer register address(R/W) More...
#define | IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Interrupt Register(R/W) More...
#define | _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Interrupt mask register(R/W) More...
#define | SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Socket Interrupt Register(R/W) More...
#define | SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Socket Interrupt Mask Register(R/W) More...
#define | _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Timeout register address( 1 is 100us )(R/W) More...
#define | _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
Retry count register(R/W) More...
#define | PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP LCP Request Timer register in PPPoE mode(R/W) More...
#define | PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP LCP Magic number register in PPPoE mode(R/W) More...
#define | PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Destination MAC Register address(R/W) More...
#define | PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Session Identification Register(R/W) More...
#define | PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
PPP Maximum Segment Size(MSS) register(R/W) More...
#define | UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
Unreachable IP register address in UDP mode(R) More...
#define | UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
Unreachable Port register address in UDP mode(R) More...
#define | PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
PHY Status Register(R/W) More...
#define | VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
chip version register address(R) More...
#define | Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
socket Mode register(R/W) More...
#define | Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket command register(R/W) More...
#define | Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket interrupt register(R) More...
#define | Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Socket status register(R) More...
#define | Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
source port register(R/W) More...
#define | Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer MAC register address(R/W) More...
#define | Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer IP register address(R/W) More...
#define | Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Peer port register address(R/W) More...
#define | Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
#define | Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
IP Type of Service(TOS) Register(R/W) More...
#define | Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
IP Time to live(TTL) Register(R/W) More...
#define | Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Receive memory size register(R/W) More...
#define | Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory size register(R/W) More...
#define | Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit free memory size register(R) More...
#define | Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory read pointer register address(R) More...
#define | Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Transmit memory write pointer register address(R/W) More...
#define | Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Received data size register(R) More...
#define | Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Read point of Receive memory(R/W) More...
#define | Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Write point of Receive memory(R) More...
#define | Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
socket interrupt mask register(R) More...
#define | Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Fragment field value in IP header register(R/W) More...
#define | Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
Keep Alive Timer register(R/W) More...
#define | MR_RST 0x80
Reset. More...
#define | MR_WOL 0x20
Wake on LAN. More...
#define | MR_PB 0x10
Ping block. More...
#define | MR_PPPOE 0x08
Enable PPPoE. More...
#define | MR_FARP 0x02
Enable UDP_FORCE_ARP CHECHK. More...
#define | IR_CONFLICT 0x80
Check IP conflict. More...
#define | IR_UNREACH 0x40
Get the destination unreachable message in UDP sending. More...
#define | IR_PPPoE 0x20
Get the PPPoE close message. More...
#define | IR_MP 0x10
Get the magic packet interrupt. More...
#define | PHYCFGR_RST ~(1<<7)
#define | PHYCFGR_OPMD (1<<6)
#define | PHYCFGR_OPMDC_ALLA (7<<3)
#define | PHYCFGR_OPMDC_PDOWN (6<<3)
#define | PHYCFGR_OPMDC_NA (5<<3)
#define | PHYCFGR_OPMDC_100FA (4<<3)
#define | PHYCFGR_OPMDC_100F (3<<3)
#define | PHYCFGR_OPMDC_100H (2<<3)
#define | PHYCFGR_OPMDC_10F (1<<3)
#define | PHYCFGR_OPMDC_10H (0<<3)
#define | PHYCFGR_DPX_FULL (1<<2)
#define | PHYCFGR_DPX_HALF (0<<2)
#define | PHYCFGR_SPD_100 (1<<1)
#define | PHYCFGR_SPD_10 (0<<1)
#define | PHYCFGR_LNK_ON (1<<0)
#define | PHYCFGR_LNK_OFF (0<<0)
#define | IM_IR7 0x80
IP Conflict Interrupt Mask. More...
#define | IM_IR6 0x40
Destination unreachable Interrupt Mask. More...
#define | IM_IR5 0x20
PPPoE Close Interrupt Mask. More...
#define | IM_IR4 0x10
Magic Packet Interrupt Mask. More...
#define | Sn_MR_MULTI 0x80
Support UDP Multicasting. More...
#define | Sn_MR_BCASTB 0x40
Broadcast block in UDP Multicasting. More...
#define | Sn_MR_ND 0x20
No Delayed Ack(TCP), Multicast flag. More...
#define | Sn_MR_UCASTB 0x10
Unicast Block in UDP Multicasting. More...
#define | Sn_MR_MACRAW 0x04
MAC LAYER RAW SOCK. More...
#define | Sn_MR_UDP 0x02
UDP. More...
#define | Sn_MR_TCP 0x01
TCP. More...
#define | Sn_MR_CLOSE 0x00
Unused socket. More...
#define | Sn_MR_MFEN Sn_MR_MULTI
MAC filter enable in Sn_MR_MACRAW mode. More...
#define | Sn_MR_MMB Sn_MR_ND
Multicast Blocking in Sn_MR_MACRAW mode. More...
#define | Sn_MR_MIP6B Sn_MR_UCASTB
IPv6 packet Blocking in Sn_MR_MACRAW mode. More...
#define | Sn_MR_MC Sn_MR_ND
IGMP version used in UDP mulitcasting. More...
#define | SOCK_STREAM Sn_MR_TCP
For Berkeley Socket API. More...
#define | SOCK_DGRAM Sn_MR_UDP
For Berkeley Socket API. More...
#define | Sn_CR_OPEN 0x01
Initialize or open socket. More...
#define | Sn_CR_LISTEN 0x02
Wait connection request in TCP mode(Server mode) More...
#define | Sn_CR_CONNECT 0x04
Send connection request in TCP mode(Client mode) More...
#define | Sn_CR_DISCON 0x08
Send closing request in TCP mode. More...
#define | Sn_CR_CLOSE 0x10
Close socket. More...
#define | Sn_CR_SEND 0x20
Update TX buffer pointer and send data. More...
#define | Sn_CR_SEND_MAC 0x21
Send data with MAC address, so without ARP process. More...
#define | Sn_CR_SEND_KEEP 0x22
Send keep alive message. More...
#define | Sn_CR_RECV 0x40
Update RX buffer pointer and receive data. More...
#define | Sn_IR_SENDOK 0x10
SEND_OK Interrupt. More...
#define | Sn_IR_TIMEOUT 0x08
TIMEOUT Interrupt. More...
#define | Sn_IR_RECV 0x04
RECV Interrupt. More...
#define | Sn_IR_DISCON 0x02
DISCON Interrupt. More...
#define | Sn_IR_CON 0x01
CON Interrupt. More...
#define | SOCK_CLOSED 0x00
Closed. More...
#define | SOCK_INIT 0x13
Initiate state. More...
#define | SOCK_LISTEN 0x14
Listen state. More...
#define | SOCK_SYNSENT 0x15
Connection state. More...
#define | SOCK_SYNRECV 0x16
Connection state. More...
#define | SOCK_ESTABLISHED 0x17
Success to connect. More...
#define | SOCK_FIN_WAIT 0x18
Closing state. More...
#define | SOCK_CLOSING 0x1A
Closing state. More...
#define | SOCK_TIME_WAIT 0x1B
Closing state. More...
#define | SOCK_CLOSE_WAIT 0x1C
Closing state. More...
#define | SOCK_LAST_ACK 0x1D
Closing state. More...
#define | SOCK_UDP 0x22
UDP socket. More...
#define | SOCK_MACRAW 0x42
MAC raw mode socket. More...
#define | IPPROTO_IP 0
#define | IPPROTO_ICMP 1
#define | IPPROTO_IGMP 2
#define | IPPROTO_GGP 3
#define | IPPROTO_TCP 6
#define | IPPROTO_PUP 12
#define | IPPROTO_UDP 17
#define | IPPROTO_IDP 22
#define | IPPROTO_ND 77
#define | IPPROTO_RAW 255
#define | WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
Enter a critical section. More...
#define | WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
Exit a critical section. More...
#define | setMR(mr) WIZCHIP_WRITE(MR,mr)
Set Mode Register. More...
#define | getMR() WIZCHIP_READ(MR)
Get Mode Register. More...
#define | setGAR(gar) WIZCHIP_WRITE_BUF(GAR,gar,4)
Set gateway IP address. More...
#define | getGAR(gar) WIZCHIP_READ_BUF(GAR,gar,4)
Get gateway IP address. More...
#define | setSUBR(subr) WIZCHIP_WRITE_BUF(SUBR, subr,4)
Set subnet mask address. More...
#define | getSUBR(subr) WIZCHIP_READ_BUF(SUBR, subr, 4)
Get subnet mask address. More...
#define | setSHAR(shar) WIZCHIP_WRITE_BUF(SHAR, shar, 6)
Set local MAC address. More...
#define | getSHAR(shar) WIZCHIP_READ_BUF(SHAR, shar, 6)
Get local MAC address. More...
#define | setSIPR(sipr) WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
Set local IP address. More...
#define | getSIPR(sipr) WIZCHIP_READ_BUF(SIPR, sipr, 4)
Get local IP address. More...
#define | setINTLEVEL(intlevel)
Set INTLEVEL register. More...
#define | getINTLEVEL() (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
Get INTLEVEL register. More...
#define | setIR(ir) WIZCHIP_WRITE(IR, (ir & 0xF0))
Set IR register. More...
#define | getIR() (WIZCHIP_READ(IR) & 0xF0)
Get IR register. More...
#define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr)
Set IMR register. More...
#define | getIMR() WIZCHIP_READ(_IMR_)
Get IMR register. More...
#define | setSIR(sir) WIZCHIP_WRITE(SIR, sir)
Set SIR register. More...
#define | getSIR() WIZCHIP_READ(SIR)
Get SIR register. More...
#define | setSIMR(simr) WIZCHIP_WRITE(SIMR, simr)
Set SIMR register. More...
#define | getSIMR() WIZCHIP_READ(SIMR)
Get SIMR register. More...
#define | setRTR(rtr)
Set RTR register. More...
#define | getRTR() (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
Get RTR register. More...
#define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, rcr)
Set RCR register. More...
#define | getRCR() WIZCHIP_READ(_RCR_)
Get RCR register. More...
#define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ptimer)
Set PTIMER register. More...
#define | getPTIMER() WIZCHIP_READ(PTIMER)
Get PTIMER register. More...
#define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, pmagic)
Set PMAGIC register. More...
#define | getPMAGIC() WIZCHIP_READ(PMAGIC)
Get PMAGIC register. More...
#define | setPHAR(phar) WIZCHIP_WRITE_BUF(PHAR, phar, 6)
Set PHAR address. More...
#define | getPHAR(phar) WIZCHIP_READ_BUF(PHAR, phar, 6)
Get local IP address. More...
#define | setPSID(psid)
Set PSID register. More...
#define | getPSID() (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
Get PSID register. More...
#define | setPMRU(pmru)
Set PMRU register. More...
#define | getPMRU() (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
Get PMRU register. More...
#define | getUIPR(uipr) WIZCHIP_READ_BUF(UIPR,uipr,4)
Get unreachable IP address. More...
#define | getUPORTR() (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
Get UPORTR register. More...
#define | setPHYCFGR(phycfgr) WIZCHIP_WRITE(PHYCFGR, phycfgr)
Set PHYCFGR register. More...
#define | getPHYCFGR() WIZCHIP_READ(PHYCFGR)
Get PHYCFGR register. More...
#define | getVERSIONR() WIZCHIP_READ(VERSIONR)
Get VERSIONR register. More...
#define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr)
Set Sn_MR register. More...
#define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn))
Get Sn_MR register. More...
#define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), cr)
Set Sn_CR register. More...
#define | getSn_CR(sn) WIZCHIP_READ(Sn_CR(sn))
Get Sn_CR register. More...
#define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
Set Sn_IR register. More...
#define | getSn_IR(sn) (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
Get Sn_IR register. More...
#define | setSn_IMR(sn, imr) WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
Set Sn_IMR register. More...
#define | getSn_IMR(sn) (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
Get Sn_IMR register. More...
#define | getSn_SR(sn) WIZCHIP_READ(Sn_SR(sn))
Get Sn_SR register. More...
#define | setSn_PORT(sn, port)
Set Sn_PORT register. More...
#define | getSn_PORT(sn) (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
Get Sn_PORT register. More...
#define | setSn_DHAR(sn, dhar) WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
Set Sn_DHAR register. More...
#define | getSn_DHAR(sn, dhar) WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
Get Sn_MR register. More...
#define | setSn_DIPR(sn, dipr) WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
Set Sn_DIPR register. More...
#define | getSn_DIPR(sn, dipr) WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
Get Sn_DIPR register. More...
#define | setSn_DPORT(sn, dport)
Set Sn_DPORT register. More...
#define | getSn_DPORT(sn) (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
Get Sn_DPORT register. More...
#define | setSn_MSSR(sn, mss)
Set Sn_MSSR register. More...
#define | getSn_MSSR(sn) (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
Get Sn_MSSR register. More...
#define | setSn_TOS(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), tos)
Set Sn_TOS register. More...
#define | getSn_TOS(sn) WIZCHIP_READ(Sn_TOS(sn))
Get Sn_TOS register. More...
#define | setSn_TTL(sn, ttl) WIZCHIP_WRITE(Sn_TTL(sn), ttl)
Set Sn_TTL register. More...
#define | getSn_TTL(sn) WIZCHIP_READ(Sn_TTL(sn))
Get Sn_TTL register. More...
#define | setSn_RXBUF_SIZE(sn, rxbufsize) WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
Set Sn_RXBUF_SIZE register. More...
#define | getSn_RXBUF_SIZE(sn) WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
Get Sn_RXBUF_SIZE register. More...
#define | setSn_TXBUF_SIZE(sn, txbufsize) WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
Set Sn_TXBUF_SIZE register. More...
#define | getSn_TXBUF_SIZE(sn) WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
Get Sn_TXBUF_SIZE register. More...
#define | getSn_TX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
Get Sn_TX_RD register. More...
#define | setSn_TX_WR(sn, txwr)
Set Sn_TX_WR register. More...
#define | getSn_TX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
Get Sn_TX_WR register. More...
#define | setSn_RX_RD(sn, rxrd)
Set Sn_RX_RD register. More...
#define | getSn_RX_RD(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
Get Sn_RX_RD register. More...
#define | getSn_RX_WR(sn) (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
Get Sn_RX_WR register. More...
#define | setSn_FRAG(sn, frag)
Set Sn_FRAG register. More...
#define | getSn_FRAG(sn) (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
Get Sn_FRAG register. More...
#define | setSn_KPALVTR(sn, kpalvt) WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
Set Sn_KPALVTR register. More...
#define | getSn_KPALVTR(sn) WIZCHIP_READ(Sn_KPALVTR(sn))
Get Sn_KPALVTR register. More...
#define | getSn_RxMAX(sn) (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)
Gets the max buffer size of socket sn passed as parameter. More...
#define | getSn_TxMAX(sn) (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)
Gets the max buffer size of socket sn passed as parameters. More...

Functions

uint8_t | WIZCHIP_READ (uint32_t AddrSel)
It reads 1 byte value from a register. More...
void | WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register. More...
void | WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers. More...
void | WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers. More...
uint16_t | getSn_TX_FSR (uint8_t sn)
Get Sn_TX_FSR register. More...
uint16_t | getSn_RX_RSR (uint8_t sn)
Get Sn_RX_RSR register. More...
void | wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory. More...
void | wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory. More...
void | wiz_recv_ignore (uint8_t sn, uint16_t len)
It discard the received data in RX memory. More...

Detailed Description

W5500 HAL Header File.

Version
1.0.0
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5500.h.

Macro Definition Documentation

#define _W5500_IO_BASE_ 0x00000000

Definition at line 54 of file w5500.h.

#define _W5500_SPI_READ_ (0x00 << 2)

Definition at line 56 of file w5500.h.

Referenced by WIZCHIP_READ(), and WIZCHIP_READ_BUF().

#define _W5500_SPI_WRITE_ (0x01 << 2)

Definition at line 57 of file w5500.h.

Referenced by WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

#define WIZCHIP_CREG_BLOCK 0x00

Definition at line 59 of file w5500.h.

#define WIZCHIP_SREG_BLOCK ( N) (1+4*N)

Definition at line 60 of file w5500.h.

#define WIZCHIP_TXBUF_BLOCK ( N) (2+4*N)

Definition at line 61 of file w5500.h.

Referenced by wiz_send_data().

#define WIZCHIP_RXBUF_BLOCK ( N) (3+4*N)

Definition at line 62 of file w5500.h.

Referenced by wiz_recv_data().

#define WIZCHIP_OFFSET_INC | ( | ADDR,
 |  | N
 | ) | (ADDR + (N<<8))

Definition at line 64 of file w5500.h.

#define IINCHIP_READ ( ADDR) WIZCHIP_READ(ADDR)

The defined for legacy chip driver.

Definition at line 70 of file w5500.h.

#define IINCHIP_WRITE | ( | ADDR,
 |  | VAL
 | ) | WIZCHIP_WRITE(ADDR,VAL)

The defined for legacy chip driver.

Definition at line 71 of file w5500.h.

#define IINCHIP_READ_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_READ_BUF(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 72 of file w5500.h.

#define IINCHIP_WRITE_BUF | ( | ADDR,
 |  | BUF,
 |  | LEN
 | ) | WIZCHIP_WRITE(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 73 of file w5500.h.

#define MR_RST 0x80

Reset.

If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.

Definition at line 693 of file w5500.h.

#define MR_WOL 0x20

Wake on LAN.

0 : Disable WOL mode
1 : Enable WOL mode
If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (Sn_MR) for opening Socket.)

Note
The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.

Definition at line 704 of file w5500.h.

#define MR_PB 0x10

Ping block.

0 : Disable Ping block
1 : Enable Ping block
If the bit is it blocks the response to a ping request.

Definition at line 712 of file w5500.h.

#define MR_PPPOE 0x08

Enable PPPoE.

0 : DisablePPPoE mode
1 : EnablePPPoE mode
If you use ADSL, this bit should be

Definition at line 720 of file w5500.h.

#define MR_FARP 0x02

Enable UDP_FORCE_ARP CHECHK.

0 : Disable Force ARP mode
1 : Enable Force ARP mode
In Force ARP mode, It forces on sending ARP Request whenever data is sent.

Definition at line 728 of file w5500.h.

#define IR_CONFLICT 0x80

Check IP conflict.

Bit is set as when own source IP address is same with the sender IP address in the received ARP request.

Definition at line 735 of file w5500.h.

#define IR_UNREACH 0x40

Get the destination unreachable message in UDP sending.

When receiving the ICMP (Destination port unreachable) packet, this bit is set as When this bit is Destination Information such as IP address and Port number may be checked with the corresponding UIPR & UPORTR.

Definition at line 742 of file w5500.h.

#define IR_PPPoE 0x20

Get the PPPoE close message.

When PPPoE is disconnected during PPPoE mode, this bit is set.

Definition at line 748 of file w5500.h.

#define IR_MP 0x10

Get the magic packet interrupt.

When WOL mode is enabled and receives the magic packet over UDP, this bit is set.

Definition at line 754 of file w5500.h.

#define PHYCFGR_RST ~(1<<7)

Definition at line 758 of file w5500.h.

Referenced by wizphy_reset().

#define PHYCFGR_OPMD (1<<6)

Definition at line 759 of file w5500.h.

Referenced by wizphy_getphyconf(), wizphy_setphyconf(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_ALLA (7<<3)

Definition at line 760 of file w5500.h.

Referenced by wizphy_getphyconf(), wizphy_setphyconf(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_PDOWN (6<<3)

Definition at line 761 of file w5500.h.

Referenced by wizphy_getphypmode(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_NA (5<<3)

Definition at line 762 of file w5500.h.

#define PHYCFGR_OPMDC_100FA (4<<3)

Definition at line 763 of file w5500.h.

Referenced by wizphy_getphyconf().

#define PHYCFGR_OPMDC_100F (3<<3)

Definition at line 764 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_100H (2<<3)

Definition at line 765 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_10F (1<<3)

Definition at line 766 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_10H (0<<3)

Definition at line 767 of file w5500.h.

Referenced by wizphy_setphyconf().

#define PHYCFGR_DPX_FULL (1<<2)

Definition at line 768 of file w5500.h.

Referenced by wizphy_getphystat().

#define PHYCFGR_DPX_HALF (0<<2)

Definition at line 769 of file w5500.h.

#define PHYCFGR_SPD_100 (1<<1)

Definition at line 770 of file w5500.h.

Referenced by wizphy_getphystat().

#define PHYCFGR_SPD_10 (0<<1)

Definition at line 771 of file w5500.h.

#define PHYCFGR_LNK_ON (1<<0)

Definition at line 772 of file w5500.h.

Referenced by wizphy_getphylink().

#define PHYCFGR_LNK_OFF (0<<0)

Definition at line 773 of file w5500.h.

#define IM_IR7 0x80

IP Conflict Interrupt Mask.

0: Disable IP Conflict Interrupt
1: Enable IP Conflict Interrupt

Definition at line 781 of file w5500.h.

#define IM_IR6 0x40

Destination unreachable Interrupt Mask.

0: Disable Destination unreachable Interrupt
1: Enable Destination unreachable Interrupt

Definition at line 788 of file w5500.h.

#define IM_IR5 0x20

PPPoE Close Interrupt Mask.

0: Disable PPPoE Close Interrupt
1: Enable PPPoE Close Interrupt

Definition at line 795 of file w5500.h.

#define IM_IR4 0x10

Magic Packet Interrupt Mask.

0: Disable Magic Packet Interrupt
1: Enable Magic Packet Interrupt

Definition at line 802 of file w5500.h.

#define Sn_MR_MULTI 0x80

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010.
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.

Definition at line 813 of file w5500.h.

#define Sn_MR_BCASTB 0x40

Broadcast block in UDP Multicasting.

0 : disable Broadcast Blocking
1 : enable Broadcast Blocking
This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010. In addition, This bit does when MACRAW mode(P[3:0] = 100

Definition at line 822 of file w5500.h.

#define Sn_MR_ND 0x20

No Delayed Ack(TCP), Multicast flag.

0 : Disable No Delayed ACK option
1 : Enable No Delayed ACK option
This bit is applied only during TCP mode (P[3:0] = 001.
When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.
When this bit is It sends the ACK packet after waiting for the timeout time configured by RTR.

Definition at line 832 of file w5500.h.

#define Sn_MR_UCASTB 0x10

Unicast Block in UDP Multicasting.

0 : disable Unicast Blocking
1 : enable Unicast Blocking
This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI =

Definition at line 840 of file w5500.h.

#define Sn_MR_MACRAW 0x04

MAC LAYER RAW SOCK.

This configures the protocol mode of Socket n.

Note
MACRAW mode should be only used in Socket 0.

Definition at line 847 of file w5500.h.

#define Sn_MR_UDP 0x02

UDP.

This configures the protocol mode of Socket n.

Definition at line 855 of file w5500.h.

#define Sn_MR_TCP 0x01

TCP.

This configures the protocol mode of Socket n.

Definition at line 861 of file w5500.h.

#define Sn_MR_CLOSE 0x00

Unused socket.

This configures the protocol mode of Socket n.

Definition at line 867 of file w5500.h.

#define Sn_MR_MFEN Sn_MR_MULTI

MAC filter enable in Sn_MR_MACRAW mode.

0 : disable MAC Filtering
1 : enable MAC Filtering
This bit is applied only during MACRAW mode(P[3:0] = 100.
When set as W5500 can only receive broadcasting packet or packet sent to itself. When this bit is W5500 can receive all packets on Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended that this bit is set as for reducing host overhead to process the all received packets.

Definition at line 880 of file w5500.h.

#define Sn_MR_MMB Sn_MR_ND

Multicast Blocking in Sn_MR_MACRAW mode.

0 : using IGMP version 2
1 : using IGMP version 1
This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = It configures the version for IGMP messages (Join/Leave/Report).

Definition at line 889 of file w5500.h.

#define Sn_MR_MIP6B Sn_MR_UCASTB

IPv6 packet Blocking in Sn_MR_MACRAW mode.

0 : disable IPv6 Blocking
1 : enable IPv6 Blocking
This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.

Definition at line 897 of file w5500.h.

#define Sn_MR_MC Sn_MR_ND

IGMP version used in UDP mulitcasting.

0 : disable Multicast Blocking
1 : enable Multicast Blocking
This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.

Definition at line 906 of file w5500.h.

#define SOCK_STREAM Sn_MR_TCP

For Berkeley Socket API.

Definition at line 912 of file w5500.h.

#define SOCK_DGRAM Sn_MR_UDP

For Berkeley Socket API.

Definition at line 917 of file w5500.h.

#define Sn_CR_OPEN 0x01

Initialize or open socket.

Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). The table below shows the value of Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0]) | Sn_SR
Sn_MR_CLOSE (000 |
Sn_MR_TCP (001 | SOCK_INIT (0x13)
Sn_MR_UDP (010 | SOCK_UDP (0x22)
S0_MR_MACRAW (100 | SOCK_MACRAW (0x02)

Definition at line 933 of file w5500.h.

#define Sn_CR_LISTEN 0x02

Wait connection request in TCP mode(Server mode)

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). In this mode, Socket n operates as a �TCP serverand waits for connection-request (SYN packet) from any �TCP client The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN. When a �TCP clientconnection request is successfully established, the Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes But when a �TCP clientconnection request is failed, Sn_IR(3) becomes and the status of Sn_SR changes to SOCK_CLOSED.

Definition at line 944 of file w5500.h.

#define Sn_CR_CONNECT 0x04

Send connection request in TCP mode(Client mode)

To connect, a connect-request (SYN packet) is sent to b>TCP serverconfigured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes

The connect-request fails in the following three cases.

  1. When a ARPTO occurs (Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.
  2. When a SYN/ACK packet is not received and TCPTO (Sn_IR(3) = )
  3. When a RST packet is received instead of a SYN/ACK packet. In these cases, Sn_SR is changed to SOCK_CLOSED.
    Note
    This is valid only in TCP mode and operates when Socket n acts as b>TCP client

Definition at line 956 of file w5500.h.

#define Sn_CR_DISCON 0x08

Send closing request in TCP mode.

Regardless of b>TCP serveror b>TCP client the DISCON command processes the disconnect-process (b>Active closeor b>Passive close.

Active close
it transmits disconnect-request(FIN packet) to the connected peer
Passive close
When FIN packet is received from peer, a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), Sn_SR is changed to SOCK_CLOSED.
Otherwise, TCPTO occurs (Sn_IR(3)=)= and then Sn_SR is changed to SOCK_CLOSED.

Note
Valid only in TCP mode.

Definition at line 969 of file w5500.h.

#define Sn_CR_CLOSE 0x10

Close socket.

Sn_SR is changed to SOCK_CLOSED.

Definition at line 975 of file w5500.h.

#define Sn_CR_SEND 0x20

Update TX buffer pointer and send data.

SEND transmits all the data in the Socket n TX buffer.
For more details, please refer to Socket n TX Free Size Register (Sn_TX_FSR), Socket n, TX Write Pointer Register(Sn_TX_WR), and Socket n TX Read Pointer Register(Sn_TX_RD).

Definition at line 983 of file w5500.h.

#define Sn_CR_SEND_MAC 0x21

Send data with MAC address, so without ARP process.

The basic operation is same as SEND.
Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).
But SEND_MAC transmits data without the automatic ARP-process.
In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process.

Note
Valid only in UDP mode.

Definition at line 993 of file w5500.h.

#define Sn_CR_SEND_KEEP 0x22

Send keep alive message.

It checks the connection status by sending 1byte keep-alive packet.
If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.

Note
Valid only in TCP mode.

Definition at line 1001 of file w5500.h.

#define Sn_CR_RECV 0x40

Update RX buffer pointer and receive data.

RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD).
For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD).

Definition at line 1009 of file w5500.h.

#define Sn_IR_SENDOK 0x10

SEND_OK Interrupt.

This is issued when SEND command is completed.

Definition at line 1016 of file w5500.h.

#define Sn_IR_TIMEOUT 0x08

TIMEOUT Interrupt.

This is issued when ARPTO or TCPTO occurs.

Definition at line 1022 of file w5500.h.

#define Sn_IR_RECV 0x04

RECV Interrupt.

This is issued whenever data is received from a peer.

Definition at line 1028 of file w5500.h.

#define Sn_IR_DISCON 0x02

DISCON Interrupt.

This is issued when FIN or FIN/ACK packet is received from a peer.

Definition at line 1034 of file w5500.h.

#define Sn_IR_CON 0x01

CON Interrupt.

This is issued one time when the connection with peer is successful and then Sn_SR is changed to SOCK_ESTABLISHED.

Definition at line 1040 of file w5500.h.

#define SOCK_CLOSED 0x00

Closed.

This indicates that Socket n is released. When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status.

Definition at line 1048 of file w5500.h.

#define SOCK_INIT 0x13

Initiate state.

This indicates Socket n is opened with TCP mode. It is changed to SOCK_INIT when Sn_MR(P[3:0]) = 001and OPEN command is ordered. After SOCK_INIT, user can use LISTEN /CONNECT command.

Definition at line 1056 of file w5500.h.

#define SOCK_LISTEN 0x14

Listen state.

This indicates Socket n is operating as b>TCP servermode and waiting for connection-request (SYN packet) from a peer (b>TCP client.
It will change to SOCK_ESTALBLISHED when the connection-request is successfully accepted.
Otherwise it will change to SOCK_CLOSED after TCPTO occurred (Sn_IR(TIMEOUT) = .

Definition at line 1064 of file w5500.h.

#define SOCK_SYNSENT 0x15

Connection state.

This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.
If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.
Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = is occurred.

Definition at line 1073 of file w5500.h.

#define SOCK_SYNRECV 0x16

Connection state.

It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED.
If not, it changes to SOCK_CLOSED after timeout occurs (Sn_IR[TIMEOUT] = .

Definition at line 1081 of file w5500.h.

#define SOCK_ESTABLISHED 0x17

Success to connect.

This indicates the status of the connection of Socket n.
It changes to SOCK_ESTABLISHED when the b>TCP SERVERprocessed the SYN packet from the b>TCP CLIENTduring SOCK_LISTEN, or when the CONNECT command is successful.
During SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.

Definition at line 1090 of file w5500.h.

#define SOCK_FIN_WAIT 0x18

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1098 of file w5500.h.

#define SOCK_CLOSING 0x1A

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1106 of file w5500.h.

#define SOCK_TIME_WAIT 0x1B

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1114 of file w5500.h.

#define SOCK_CLOSE_WAIT 0x1C

Closing state.

This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.
This is half-closing status, and data can be transferred.
For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.

Definition at line 1122 of file w5500.h.

#define SOCK_LAST_ACK 0x1D

Closing state.

This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.
It changes to SOCK_CLOSED when Socket n received the response successfully, or when timeout occurs (Sn_IR[TIMEOUT] = .

Definition at line 1129 of file w5500.h.

#define SOCK_UDP 0x22

UDP socket.

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = 010.
It changes to SOCK_UPD when Sn_MR(P[3:0]) = 010 and OPEN command is ordered.
Unlike TCP mode, data can be transfered without the connection-process.

Definition at line 1137 of file w5500.h.

#define SOCK_MACRAW 0x42

MAC raw mode socket.

This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.
It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.
Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.

Definition at line 1147 of file w5500.h.

#define IPPROTO_IP 0

Definition at line 1152 of file w5500.h.

#define IPPROTO_ICMP 1

Definition at line 1153 of file w5500.h.

#define IPPROTO_IGMP 2

Definition at line 1154 of file w5500.h.

#define IPPROTO_GGP 3

Definition at line 1155 of file w5500.h.

#define IPPROTO_TCP 6

Definition at line 1156 of file w5500.h.

#define IPPROTO_PUP 12

Definition at line 1157 of file w5500.h.

#define IPPROTO_UDP 17

Definition at line 1158 of file w5500.h.

#define IPPROTO_IDP 22

Definition at line 1159 of file w5500.h.

#define IPPROTO_ND 77

Definition at line 1160 of file w5500.h.

#define IPPROTO_RAW 255

Definition at line 1161 of file w5500.h.

#define WIZCHIP_CRITICAL_ENTER ( ) WIZCHIP.CRIS._enter()

Enter a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_EXIT()

Definition at line 1175 of file w5500.h.

#define WIZCHIP_CRITICAL_EXIT ( ) WIZCHIP.CRIS._exit()

Exit a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See Also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_ENTER()

Definition at line 1192 of file w5500.h.

#define getSn_RxMAX ( sn) (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)

Gets the max buffer size of socket sn passed as parameter.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Socket n RX max buffer size.

Definition at line 2088 of file w5500.h.

#define getSn_TxMAX ( sn) (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)

Gets the max buffer size of socket sn passed as parameters.

Parameters
(uint8_t)sn Socket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Socket n TX max buffer size.

Definition at line 2101 of file w5500.h.

Generated on Thu Apr 9 2015 14:44:02 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/socket.c File Reference

  • Ethernet
Macros | Functions
socket.c File Reference

SOCKET APIs Implements file. More...

#include "socket.h"
Include dependency graph for socket.c:

Go to the source code of this file.

Macros

#define | SOCK_ANY_PORT_NUM 0xC000
#define | CHECK_SOCKNUM()
#define | CHECK_SOCKMODE(mode)
#define | CHECK_SOCKINIT()
#define | CHECK_SOCKDATA()

Functions

int8_t | socket (uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag)
Open a socket. More...
int8_t | close (uint8_t sn)
Close a socket. More...
int8_t | listen (uint8_t sn)
Listen to a connection request from a client. More...
int8_t | connect (uint8_t sn, uint8_t *addr, uint16_t port)
Try to connect a server. More...
int8_t | disconnect (uint8_t sn)
Try to disconnect a connection socket. More...
int32_t | send (uint8_t sn, uint8_t *buf, uint16_t len)
Send data to the connected peer in TCP socket. More...
int32_t | recv (uint8_t sn, uint8_t *buf, uint16_t len)
Receive data from the connected peer. More...
int32_t | sendto (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t port)
Sends datagram to the peer with destination IP address and port number passed as parameter. More...
int32_t | recvfrom (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t *port)
Receive datagram of UDP or MACRAW. More...
int8_t | ctlsocket (uint8_t sn, ctlsock_type cstype, void *arg)
Control socket. More...
int8_t | setsockopt (uint8_t sn, sockopt_type sotype, void *arg)
set socket options More...
int8_t | getsockopt (uint8_t sn, sockopt_type sotype, void *arg)
get socket options More...

Detailed Description

SOCKET APIs Implements file.

SOCKET APIs like as Berkeley Socket APIs.

Version
1.0.3
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2014/05/01> V1.0.3. Refer to M20140501
  1. Implicit type casting -> Explicit type casting.
  2. replace 0x01 with PACK_REMAINED in recvfrom()
  3. Validation a destination ip in connect() & sendto(): It occurs a fatal error on converting unint32 address if uint8* addr parameter is not aligned by 4byte address. Copy 4 byte addr value into temporary uint32 variable and then compares it. <2013/12/20> V1.0.2 Refer to M20131220 Remove Warning. <2013/11/04> V1.0.1 2nd Release. Refer to "20131104". In sendto(), Add to clear timeout interrupt status (Sn_IR_TIMEOUT) <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file socket.c.

Macro Definition Documentation

#define SOCK_ANY_PORT_NUM 0xC000

Definition at line 60 of file socket.c.

Referenced by socket().

#define CHECK_SOCKNUM ( )
Value:
do{ \
if(sn > _WIZCHIP_SOCK_NUM_) return SOCKERR_SOCKNUM; \
}while(0); \

Definition at line 72 of file socket.c.

Referenced by close(), connect(), ctlsocket(), disconnect(), getsockopt(), listen(), recv(), recvfrom(), send(), sendto(), setsockopt(), and socket().

#define CHECK_SOCKMODE ( mode)
Value:
do{ \
if((getSn_MR(sn) & 0x0F) != mode) return SOCKERR_SOCKMODE; \
}while(0); \

Definition at line 77 of file socket.c.

Referenced by connect(), disconnect(), getsockopt(), listen(), recv(), send(), and setsockopt().

#define CHECK_SOCKINIT ( )
Value:
do{ \
if((getSn_SR(sn) != SOCK_INIT)) return SOCKERR_SOCKINIT; \
}while(0); \

Definition at line 82 of file socket.c.

Referenced by connect(), and listen().

#define CHECK_SOCKDATA ( )
Value:
do{ \
if(len == 0) return SOCKERR_DATALEN; \
}while(0); \

Definition at line 87 of file socket.c.

Referenced by recv(), recvfrom(), send(), and sendto().

Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/socket.h File Reference

  • Ethernet
Macros | Enumerations | Functions
socket.h File Reference

SOCKET APIs Header file. More...

#include "wizchip_conf.h"
Include dependency graph for socket.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | SOCKET uint8_t
SOCKET type define for legacy driver. More...
#define | SOCK_OK 1
Result is OK about socket process. More...
#define | SOCK_BUSY 0
Socket is busy on processing the operation. Valid only Non-block IO Mode. More...
#define | SOCK_FATAL -1000
Result is fatal error about socket process. More...
#define | SOCK_ERROR 0
#define | SOCKERR_SOCKNUM (SOCK_ERROR - 1)
Invalid socket number. More...
#define | SOCKERR_SOCKOPT (SOCK_ERROR - 2)
Invalid socket option. More...
#define | SOCKERR_SOCKINIT (SOCK_ERROR - 3)
Socket is not initialized or SIPR is Zero IP address when Sn_MR_TCP. More...
#define | SOCKERR_SOCKCLOSED (SOCK_ERROR - 4)
Socket unexpectedly closed. More...
#define | SOCKERR_SOCKMODE (SOCK_ERROR - 5)
Invalid socket mode for socket operation. More...
#define | SOCKERR_SOCKFLAG (SOCK_ERROR - 6)
Invalid socket flag. More...
#define | SOCKERR_SOCKSTATUS (SOCK_ERROR - 7)
Invalid socket status for socket operation. More...
#define | SOCKERR_ARG (SOCK_ERROR - 10)
Invalid argument. More...
#define | SOCKERR_PORTZERO (SOCK_ERROR - 11)
Port number is zero. More...
#define | SOCKERR_IPINVALID (SOCK_ERROR - 12)
Invalid IP address. More...
#define | SOCKERR_TIMEOUT (SOCK_ERROR - 13)
Timeout occurred. More...
#define | SOCKERR_DATALEN (SOCK_ERROR - 14)
Data length is zero or greater than buffer max size. More...
#define | SOCKERR_BUFFER (SOCK_ERROR - 15)
Socket buffer is not enough for data communication. More...
#define | SOCKFATAL_PACKLEN (SOCK_FATAL - 1)
Invalid packet length. Fatal Error. More...
#define | SF_ETHER_OWN (Sn_MR_MFEN)
In Sn_MR_MACRAW, Receive only the packet as broadcast, multicast and own packet. More...
#define | SF_IGMP_VER2 (Sn_MR_MC)
In Sn_MR_UDP with SF_MULTI_ENABLE, Select IGMP version 2. More...
#define | SF_TCP_NODELAY (Sn_MR_ND)
In Sn_MR_TCP, Use to nodelayed ack. More...
#define | SF_MULTI_ENABLE (Sn_MR_MULTI)
In Sn_MR_UDP, Enable multicast mode. More...
#define | SF_BROAD_BLOCK (Sn_MR_BCASTB)
In Sn_MR_UDP or Sn_MR_MACRAW, Block broadcast packet. Valid only in W5500. More...
#define | SF_MULTI_BLOCK (Sn_MR_MMB)
In Sn_MR_MACRAW, Block multicast packet. Valid only in W5500. More...
#define | SF_IPv6_BLOCK (Sn_MR_MIP6B)
In Sn_MR_MACRAW, Block IPv6 packet. Valid only in W5500. More...
#define | SF_UNI_BLOCK (Sn_MR_UCASTB)
In Sn_MR_UDP with SF_MULTI_ENABLE. Valid only in W5500. More...
#define | SF_IO_NONBLOCK 0x01
Socket nonblock io mode. It used parameter in socket(). More...
#define | PACK_FIRST 0x80
In Non-TCP packet, It indicates to start receiving a packet. More...
#define | PACK_REMAINED 0x01
In Non-TCP packet, It indicates to remain a packet to be received. More...
#define | PACK_COMPLETED 0x00
In Non-TCP packet, It indicates to complete to receive a packet. More...
#define | SOCK_IO_BLOCK 0
Socket Block IO Mode in setsockopt(). More...
#define | SOCK_IO_NONBLOCK 1
Socket Non-block IO Mode in setsockopt(). More...

Enumerations

enum sockint_kind {
SIK_CONNECTED = (1 << 0), SIK_DISCONNECTED = (1 << 1), SIK_RECEIVED = (1 << 2), SIK_TIMEOUT = (1 << 3),
SIK_SENT = (1 << 4), SIK_ALL = 0x1F
}
The kind of Socket Interrupt. More...
enum ctlsock_type {
CS_SET_IOMODE, CS_GET_IOMODE, CS_GET_MAXTXBUF, CS_GET_MAXRXBUF,
CS_CLR_INTERRUPT, CS_GET_INTERRUPT, CS_SET_INTMASK, CS_GET_INTMASK
}
The type of ctlsocket(). More...
enum sockopt_type {
SO_FLAG, SO_TTL, SO_TOS, SO_MSS,
SO_DESTIP, SO_DESTPORT, SO_KEEPALIVESEND, SO_KEEPALIVEAUTO,
SO_SENDBUF, SO_RECVBUF, SO_STATUS, SO_REMAINSIZE,
SO_PACKINFO
}
The type of socket option in setsockopt() or getsockopt() More...

Functions

int8_t | socket (uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag)
Open a socket. More...
int8_t | close (uint8_t sn)
Close a socket. More...
int8_t | listen (uint8_t sn)
Listen to a connection request from a client. More...
int8_t | connect (uint8_t sn, uint8_t *addr, uint16_t port)
Try to connect a server. More...
int8_t | disconnect (uint8_t sn)
Try to disconnect a connection socket. More...
int32_t | send (uint8_t sn, uint8_t *buf, uint16_t len)
Send data to the connected peer in TCP socket. More...
int32_t | recv (uint8_t sn, uint8_t *buf, uint16_t len)
Receive data from the connected peer. More...
int32_t | sendto (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t port)
Sends datagram to the peer with destination IP address and port number passed as parameter. More...
int32_t | recvfrom (uint8_t sn, uint8_t *buf, uint16_t len, uint8_t *addr, uint16_t *port)
Receive datagram of UDP or MACRAW. More...
int8_t | ctlsocket (uint8_t sn, ctlsock_type cstype, void *arg)
Control socket. More...
int8_t | setsockopt (uint8_t sn, sockopt_type sotype, void *arg)
set socket options More...
int8_t | getsockopt (uint8_t sn, sockopt_type sotype, void *arg)
get socket options More...

Detailed Description

SOCKET APIs Header file.

SOCKET APIs like as berkeley socket api.

Version
1.0.2
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2014/05/01> V1.0.2. Refer to M20140501
  1. Modify the comment : SO_REMAINED -> PACK_REMAINED
  2. Add the comment as zero byte udp data reception in getsockopt(). <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file socket.h.

Macro Definition Documentation

#define SOCKET uint8_t

SOCKET type define for legacy driver.

Definition at line 90 of file socket.h.

#define SOCK_OK 1

Result is OK about socket process.

Definition at line 92 of file socket.h.

Referenced by close(), connect(), ctlsocket(), disconnect(), getsockopt(), listen(), and setsockopt().

#define SOCK_BUSY 0

Socket is busy on processing the operation. Valid only Non-block IO Mode.

Definition at line 93 of file socket.h.

Referenced by connect(), disconnect(), recv(), recvfrom(), send(), and sendto().

#define SOCK_FATAL -1000

Result is fatal error about socket process.

Definition at line 94 of file socket.h.

#define SOCK_ERROR 0

Definition at line 96 of file socket.h.

#define SOCKERR_SOCKNUM (SOCK_ERROR - 1)

Invalid socket number.

Definition at line 97 of file socket.h.

#define SOCKERR_SOCKOPT (SOCK_ERROR - 2)

Invalid socket option.

Definition at line 98 of file socket.h.

Referenced by getsockopt(), and setsockopt().

#define SOCKERR_SOCKINIT (SOCK_ERROR - 3)

Socket is not initialized or SIPR is Zero IP address when Sn_MR_TCP.

Definition at line 99 of file socket.h.

Referenced by socket().

#define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4)

Socket unexpectedly closed.

Definition at line 100 of file socket.h.

Referenced by connect(), listen(), recvfrom(), and sendto().

#define SOCKERR_SOCKMODE (SOCK_ERROR - 5)

Invalid socket mode for socket operation.

Definition at line 101 of file socket.h.

Referenced by recvfrom(), sendto(), and socket().

#define SOCKERR_SOCKFLAG (SOCK_ERROR - 6)

Invalid socket flag.

Definition at line 102 of file socket.h.

Referenced by socket().

#define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7)

Invalid socket status for socket operation.

Definition at line 103 of file socket.h.

Referenced by recv(), send(), and sendto().

#define SOCKERR_ARG (SOCK_ERROR - 10)

Invalid argument.

Definition at line 104 of file socket.h.

Referenced by ctlsocket(), and setsockopt().

#define SOCKERR_PORTZERO (SOCK_ERROR - 11)

Port number is zero.

Definition at line 105 of file socket.h.

Referenced by connect(), and sendto().

#define SOCKERR_IPINVALID (SOCK_ERROR - 12)

Invalid IP address.

Definition at line 106 of file socket.h.

Referenced by connect(), and sendto().

#define SOCKERR_TIMEOUT (SOCK_ERROR - 13)

Timeout occurred.

Definition at line 107 of file socket.h.

Referenced by connect(), disconnect(), send(), sendto(), and setsockopt().

#define SOCKERR_DATALEN (SOCK_ERROR - 14)

Data length is zero or greater than buffer max size.

Definition at line 108 of file socket.h.

#define SOCKERR_BUFFER (SOCK_ERROR - 15)

Socket buffer is not enough for data communication.

Definition at line 109 of file socket.h.

#define SOCKFATAL_PACKLEN (SOCK_FATAL - 1)

Invalid packet length. Fatal Error.

Definition at line 111 of file socket.h.

Referenced by recvfrom().

#define SF_ETHER_OWN (Sn_MR_MFEN)

In Sn_MR_MACRAW, Receive only the packet as broadcast, multicast and own packet.

Definition at line 116 of file socket.h.

#define SF_IGMP_VER2 (Sn_MR_MC)

In Sn_MR_UDP with SF_MULTI_ENABLE, Select IGMP version 2.

Definition at line 117 of file socket.h.

Referenced by socket().

#define SF_TCP_NODELAY (Sn_MR_ND)

In Sn_MR_TCP, Use to nodelayed ack.

Definition at line 118 of file socket.h.

Referenced by socket().

#define SF_MULTI_ENABLE (Sn_MR_MULTI)

In Sn_MR_UDP, Enable multicast mode.

Definition at line 119 of file socket.h.

Referenced by socket().

#define SF_BROAD_BLOCK (Sn_MR_BCASTB)

In Sn_MR_UDP or Sn_MR_MACRAW, Block broadcast packet. Valid only in W5500.

Definition at line 122 of file socket.h.

#define SF_MULTI_BLOCK (Sn_MR_MMB)

In Sn_MR_MACRAW, Block multicast packet. Valid only in W5500.

Definition at line 123 of file socket.h.

#define SF_IPv6_BLOCK (Sn_MR_MIP6B)

In Sn_MR_MACRAW, Block IPv6 packet. Valid only in W5500.

Definition at line 124 of file socket.h.

#define SF_UNI_BLOCK (Sn_MR_UCASTB)

In Sn_MR_UDP with SF_MULTI_ENABLE. Valid only in W5500.

Definition at line 125 of file socket.h.

Referenced by socket().

#define SF_IO_NONBLOCK 0x01

Socket nonblock io mode. It used parameter in socket().

Definition at line 128 of file socket.h.

Referenced by socket().

#define PACK_FIRST 0x80

In Non-TCP packet, It indicates to start receiving a packet.

Definition at line 133 of file socket.h.

Referenced by recvfrom().

#define PACK_REMAINED 0x01

In Non-TCP packet, It indicates to remain a packet to be received.

Definition at line 134 of file socket.h.

Referenced by recvfrom().

#define PACK_COMPLETED 0x00

In Non-TCP packet, It indicates to complete to receive a packet.

Definition at line 135 of file socket.h.

Referenced by recvfrom().

#define SOCK_IO_BLOCK 0

Socket Block IO Mode in setsockopt().

Definition at line 325 of file socket.h.

Referenced by ctlsocket().

#define SOCK_IO_NONBLOCK 1

Socket Non-block IO Mode in setsockopt().

Definition at line 326 of file socket.h.

Referenced by ctlsocket().

Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/wizchip_conf.c File Reference

  • Ethernet
Functions | Variables
wizchip_conf.c File Reference

WIZCHIP Config Header File. More...

#include <stddef.h>
#include "wizchip_conf.h"
Include dependency graph for wizchip_conf.c:

Go to the source code of this file.

Functions

void | wizchip_cris_enter (void)
Default function to enable interrupt. More...
void | wizchip_cris_exit (void)
Default function to disable interrupt. More...
void | wizchip_cs_select (void)
Default function to select chip. More...
void | wizchip_cs_deselect (void)
Default function to deselect chip. More...
uint8_t | wizchip_bus_readbyte (uint32_t AddrSel)
Default function to read in direct or indirect interface. More...
void | wizchip_bus_writebyte (uint32_t AddrSel, uint8_t wb)
Default function to write in direct or indirect interface. More...
uint8_t | wizchip_spi_readbyte (void)
Default function to read in SPI interface. More...
void | wizchip_spi_writebyte (uint8_t wb)
Default function to write in SPI interface. More...
void | wizchip_spi_readburst (uint8_t *pBuf, uint16_t len)
Default function to burst read in SPI interface. More...
void | wizchip_spi_writeburst (uint8_t *pBuf, uint16_t len)
Default function to burst write in SPI interface. More...
void | reg_wizchip_cris_cbfunc (void(*cris_en)(void), void(*cris_ex)(void))
Registers call back function for critical section of I/O functions such as WIZCHIP_READ, WIZCHIP_WRITE, WIZCHIP_READ_BUF and WIZCHIP_WRITE_BUF. More...
void | reg_wizchip_cs_cbfunc (void(*cs_sel)(void), void(*cs_desel)(void))
Registers call back function for WIZCHIP select & deselect. More...
void | reg_wizchip_bus_cbfunc (uint8_t(*bus_rb)(uint32_t addr), void(*bus_wb)(uint32_t addr, uint8_t wb))
Registers call back function for bus interface. More...
void | reg_wizchip_spi_cbfunc (uint8_t(*spi_rb)(void), void(*spi_wb)(uint8_t wb))
Registers call back function for SPI interface. More...
void | reg_wizchip_spiburst_cbfunc (void(*spi_rb)(uint8_t *pBuf, uint16_t len), void(*spi_wb)(uint8_t *pBuf, uint16_t len))
Registers call back function for SPI interface. More...
int8_t | ctlwizchip (ctlwizchip_type cwtype, void *arg)
Controls to the WIZCHIP. More...
int8_t | ctlnetwork (ctlnetwork_type cntype, void *arg)
Controls to network. More...
void | wizchip_sw_reset (void)
Reset WIZCHIP by softly. More...
int8_t | wizchip_init (uint8_t *txsize, uint8_t *rxsize)
Initializes WIZCHIP with socket buffer size. More...
void | wizchip_clrinterrupt (intr_kind intr)
Clear Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterrupt (void)
Get Interrupt of WIZCHIP. More...
void | wizchip_setinterruptmask (intr_kind intr)
Mask or Unmask Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterruptmask (void)
Get Interrupt mask of WIZCHIP. More...
int8_t | wizphy_getphylink (void)
get the link status of phy in WIZCHIP. No use in W5100 More...
int8_t | wizphy_getphypmode (void)
get the power mode of PHY in WIZCHIP. No use in W5100 More...
void | wizphy_reset (void)
Reset phy. Vailid only in W5500. More...
void | wizphy_setphyconf (wiz_PhyConf *phyconf)
Set the phy information for WIZCHIP without power mode. More...
void | wizphy_getphyconf (wiz_PhyConf *phyconf)
Get phy configuration information. More...
void | wizphy_getphystat (wiz_PhyConf *phyconf)
Get phy status. More...
int8_t | wizphy_setphypmode (uint8_t pmode)
set the power mode of phy inside WIZCHIP. Refer to PHYCFGR in W5500, PHYSTATUS in W5200 More...
void | wizchip_setnetinfo (wiz_NetInfo *pnetinfo)
Set the network information for WIZCHIP. More...
void | wizchip_getnetinfo (wiz_NetInfo *pnetinfo)
Get the network information for WIZCHIP. More...
int8_t | wizchip_setnetmode (netmode_type netmode)
Set the network mode such WOL, PPPoE, Ping Block, and etc. More...
netmode_type | wizchip_getnetmode (void)
Get the network mode such WOL, PPPoE, Ping Block, and etc. More...
void | wizchip_settimeout (wiz_NetTimeout *nettime)
Set retry time value(RTR) and retry count(RCR). More...
void | wizchip_gettimeout (wiz_NetTimeout *nettime)
Get retry time value(RTR) and retry count(RCR). More...

Variables

_WIZCHIP WIZCHIP

Detailed Description

WIZCHIP Config Header File.

Version
1.0.1
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2014/05/01> V1.0.1 Refer to M20140501
  1. Explicit type casting in wizchip_bus_readbyte() & wizchip_bus_writebyte()

Definition in file wizchip_conf.c.

Function Documentation

void wizchip_cris_enter ( void )

Default function to enable interrupt.

      uint32_t type converts into ptrdiff_t first. And then recoverting it into uint8_t*
      For remove the warning when pointer type size is not 32bit.
      If ptrdiff_t doesn't support in your complier, You should must replace ptrdiff_t into your suitable pointer type.
  <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 67 of file wizchip_conf.c.

Referenced by reg_wizchip_cris_cbfunc().

void wizchip_cris_exit ( void )

Default function to disable interrupt.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 75 of file wizchip_conf.c.

Referenced by reg_wizchip_cris_cbfunc().

void wizchip_cs_select ( void )

Default function to select chip.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 83 of file wizchip_conf.c.

Referenced by reg_wizchip_cs_cbfunc().

void wizchip_cs_deselect ( void )

Default function to deselect chip.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 91 of file wizchip_conf.c.

Referenced by reg_wizchip_cs_cbfunc().

uint8_t wizchip_bus_readbyte ( uint32_t AddrSel)

Default function to read in direct or indirect interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 101 of file wizchip_conf.c.

Referenced by reg_wizchip_bus_cbfunc().

void wizchip_bus_writebyte | ( | uint32_t | AddrSel,
 |  | uint8_t | wb
 | ) |  |

Default function to write in direct or indirect interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 112 of file wizchip_conf.c.

Referenced by reg_wizchip_bus_cbfunc().

uint8_t wizchip_spi_readbyte ( void )

Default function to read in SPI interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 120 of file wizchip_conf.c.

Referenced by reg_wizchip_spi_cbfunc().

void wizchip_spi_writebyte ( uint8_t wb)

Default function to write in SPI interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 128 of file wizchip_conf.c.

Referenced by reg_wizchip_spi_cbfunc().

void wizchip_spi_readburst | ( | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

Default function to burst read in SPI interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 136 of file wizchip_conf.c.

Referenced by reg_wizchip_spiburst_cbfunc().

void wizchip_spi_writeburst | ( | uint8_t * | pBuf,
 |  | uint16_t | len
 | ) |  |

Default function to burst write in SPI interface.

Note
This function help not to access wrong address. If you do not describe this function or register any functions, null function is called.

Definition at line 144 of file wizchip_conf.c.

Referenced by reg_wizchip_spiburst_cbfunc().

void reg_wizchip_cris_cbfunc | ( | void(*)(void) | cris_en,
 |  | void(*)(void) | cris_ex
 | ) |  |

Registers call back function for critical section of I/O functions such as WIZCHIP_READ, WIZCHIP_WRITE, WIZCHIP_READ_BUF and WIZCHIP_WRITE_BUF.

Parameters
cris_en | : callback function for critical section enter.
cris_ex | : callback function for critical section exit.
Todo:
Describe WIZCHIP_CRITICAL_ENTER and WIZCHIP_CRITICAL_EXIT marco or register your functions.
Note
If you do not describe or register, default functions(wizchip_cris_enter & wizchip_cris_exit) is called.

Definition at line 186 of file wizchip_conf.c.

References __WIZCHIP::_CRIS::_enter, __WIZCHIP::_CRIS::_exit, __WIZCHIP::CRIS, wizchip_cris_enter(), and wizchip_cris_exit().

void reg_wizchip_cs_cbfunc | ( | void(*)(void) | cs_sel,
 |  | void(*)(void) | cs_desel
 | ) |  |

Registers call back function for WIZCHIP select & deselect.

Parameters
cs_sel | : callback function for WIZCHIP select
cs_desel | : callback fucntion for WIZCHIP deselect
Todo:
Describe wizchip_cs_select and wizchip_cs_deselect function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 200 of file wizchip_conf.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, __WIZCHIP::CS, wizchip_cs_deselect(), and wizchip_cs_select().

void reg_wizchip_bus_cbfunc | ( | uint8_t(*)(uint32_t addr) | bus_rb,
 |  | void(*)(uint32_t addr, uint8_t wb) | bus_wb
 | ) |  |

Registers call back function for bus interface.

Parameters
bus_rb | : callback function to read byte data using system bus
bus_wb | : callback function to write byte data using system bus
Todo:
Describe wizchip_bus_readbyte and wizchip_bus_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 214 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_byte, _WIZCHIP_IO_MODE_BUS_, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::IF, __WIZCHIP::if_mode, wizchip_bus_readbyte(), and wizchip_bus_writebyte().

void reg_wizchip_spi_cbfunc | ( | uint8_t(*)(void) | spi_rb,
 |  | void(*)(uint8_t wb) | spi_wb
 | ) |  |

Registers call back function for SPI interface.

Parameters
spi_rb | : callback function to read byte using SPI
spi_wb | : callback function to write byte using SPI
Todo:
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 230 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_byte, _WIZCHIP_IO_MODE_SPI_, __WIZCHIP::_IF::_write_byte, __WIZCHIP::IF, __WIZCHIP::if_mode, __WIZCHIP::_IF::SPI, wizchip_spi_readbyte(), and wizchip_spi_writebyte().

void reg_wizchip_spiburst_cbfunc | ( | void(*)(uint8_t *pBuf, uint16_t len) | spi_rb,
 |  | void(*)(uint8_t *pBuf, uint16_t len) | spi_wb
 | ) |  |

Registers call back function for SPI interface.

Parameters
spi_rb | : callback function to burst read using SPI
spi_wb | : callback function to burst write using SPI
Todo:
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 247 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_burst, _WIZCHIP_IO_MODE_SPI_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::IF, __WIZCHIP::if_mode, __WIZCHIP::_IF::SPI, wizchip_spi_readburst(), and wizchip_spi_writeburst().

int8_t wizphy_getphylink ( void )

get the link status of phy in WIZCHIP. No use in W5100

Definition at line 504 of file wizchip_conf.c.

References getPHYCFGR, getPHYSTATUS, PHY_LINK_OFF, PHY_LINK_ON, PHYCFGR_LNK_ON, and PHYSTATUS_LINK.

Referenced by ctlwizchip().

int8_t wizphy_getphypmode ( void )

get the power mode of PHY in WIZCHIP. No use in W5100

Definition at line 525 of file wizchip_conf.c.

References getPHYCFGR, getPHYSTATUS, PHY_POWER_DOWN, PHY_POWER_NORM, PHYCFGR_OPMDC_PDOWN, and PHYSTATUS_POWERDOWN.

Referenced by ctlwizchip().

void wizphy_reset ( void )

Reset phy. Vailid only in W5500.

Definition at line 546 of file wizchip_conf.c.

References getPHYCFGR, PHYCFGR_RST, and setPHYCFGR.

Referenced by ctlwizchip(), wizphy_setphyconf(), and wizphy_setphypmode().

Variable Documentation

_WIZCHIP WIZCHIP
Initial value:
=
{
_WIZCHIP_IO_MODE_,
_WIZCHIP_ID_ ,
wizchip_cris_enter,
wizchip_cris_exit,
wizchip_cs_select,
wizchip_cs_deselect,
wizchip_bus_readbyte,
wizchip_bus_writebyte
}

\ref _WIZCHIP instance

Definition at line 168 of file wizchip_conf.c.

Referenced by WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

Generated on Thu Apr 9 2015 14:44:02 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/wizchip_conf.h File Reference

  • Ethernet
Classes | Macros | Typedefs | Enumerations | Functions | Variables
wizchip_conf.h File Reference

WIZCHIP Config Header File. More...

#include <stdint.h>
#include "W5500/w5500.h"
Include dependency graph for wizchip_conf.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | __WIZCHIP
The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions. More...
struct | __WIZCHIP::_CRIS
struct | __WIZCHIP::_CS
union | __WIZCHIP::_IF
struct | wiz_PhyConf_t
struct | wiz_NetInfo_t
struct | wiz_NetTimeout_t

Macros

#define | _WIZCHIP_ 5500
Select WIZCHIP. More...
#define | _WIZCHIP_IO_MODE_NONE_ 0x0000
#define | _WIZCHIP_IO_MODE_BUS_ 0x0100
#define | _WIZCHIP_IO_MODE_SPI_ 0x0200
#define | _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1)
#define | _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2)
#define | _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1)
#define | _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2)
#define | _WIZCHIP_ID_ "W5500\0"
#define | _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_
Define interface mode.
. More...
#define | _WIZCHIP_IO_BASE_ 0x00000000
Define I/O base address when BUS IF mode. More...
#define | _WIZCHIP_SOCK_NUM_ 8
The count of independant socket of WIZCHIP. More...
#define | PHY_CONFBY_HW 0
Configured PHY operation mode by HW pin. More...
#define | PHY_CONFBY_SW 1
Configured PHY operation mode by SW register. More...
#define | PHY_MODE_MANUAL 0
Configured PHY operation mode with user setting. More...
#define | PHY_MODE_AUTONEGO 1
Configured PHY operation mode with auto-negotiation. More...
#define | PHY_SPEED_10 0
Link Speed 10. More...
#define | PHY_SPEED_100 1
Link Speed 100. More...
#define | PHY_DUPLEX_HALF 0
Link Half-Duplex. More...
#define | PHY_DUPLEX_FULL 1
Link Full-Duplex. More...
#define | PHY_LINK_OFF 0
Link Off. More...
#define | PHY_LINK_ON 1
Link On. More...
#define | PHY_POWER_NORM 0
PHY power normal mode. More...
#define | PHY_POWER_DOWN 1
PHY power down mode. More...

Typedefs

typedef struct __WIZCHIP | _WIZCHIP
The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions. More...
typedef struct wiz_PhyConf_t | wiz_PhyConf
typedef struct wiz_NetInfo_t | wiz_NetInfo
typedef struct wiz_NetTimeout_t | wiz_NetTimeout

Enumerations

enum ctlwizchip_type {
CW_RESET_WIZCHIP, CW_INIT_WIZCHIP, CW_GET_INTERRUPT, CW_CLR_INTERRUPT,
CW_SET_INTRMASK, CW_GET_INTRMASK, CW_SET_INTRTIME, CW_GET_INTRTIME,
CW_GET_ID, CW_RESET_PHY, CW_SET_PHYCONF, CW_GET_PHYCONF,
CW_GET_PHYSTATUS, CW_SET_PHYPOWMODE, CW_GET_PHYPOWMODE, CW_GET_PHYLINK
}
enum ctlnetwork_type {
CN_SET_NETINFO, CN_GET_NETINFO, CN_SET_NETMODE, CN_GET_NETMODE,
CN_SET_TIMEOUT, CN_GET_TIMEOUT
}
enum intr_kind {
IK_WOL = (1 << 4), IK_PPPOE_TERMINATED = (1 << 5), IK_DEST_UNREACH = (1 << 6), IK_IP_CONFLICT = (1 << 7),
IK_SOCK_0 = (1 << 8), IK_SOCK_1 = (1 << 9), IK_SOCK_2 = (1 << 10), IK_SOCK_3 = (1 << 11),
IK_SOCK_4 = (1 << 12), IK_SOCK_5 = (1 << 13), IK_SOCK_6 = (1 << 14), IK_SOCK_7 = (1 << 15),
IK_SOCK_ALL = (0xFF << 8)
}
enum | dhcp_mode { NETINFO_STATIC = 1, NETINFO_DHCP }
enum | netmode_type { NM_FORCEARP = (1<<1), NM_WAKEONLAN = (1<<5), NM_PINGBLOCK = (1<<4), NM_PPPOE = (1<<3) }

Functions

void | reg_wizchip_cris_cbfunc (void(*cris_en)(void), void(*cris_ex)(void))
Registers call back function for critical section of I/O functions such as WIZCHIP_READ, WIZCHIP_WRITE, WIZCHIP_READ_BUF and WIZCHIP_WRITE_BUF. More...
void | reg_wizchip_cs_cbfunc (void(*cs_sel)(void), void(*cs_desel)(void))
Registers call back function for WIZCHIP select & deselect. More...
void | reg_wizchip_bus_cbfunc (uint8_t(*bus_rb)(uint32_t addr), void(*bus_wb)(uint32_t addr, uint8_t wb))
Registers call back function for bus interface. More...
void | reg_wizchip_spi_cbfunc (uint8_t(*spi_rb)(void), void(*spi_wb)(uint8_t wb))
Registers call back function for SPI interface. More...
void | reg_wizchip_spiburst_cbfunc (void(*spi_rb)(uint8_t *pBuf, uint16_t len), void(*spi_wb)(uint8_t *pBuf, uint16_t len))
Registers call back function for SPI interface. More...
int8_t | ctlwizchip (ctlwizchip_type cwtype, void *arg)
Controls to the WIZCHIP. More...
int8_t | ctlnetwork (ctlnetwork_type cntype, void *arg)
Controls to network. More...
void | wizchip_sw_reset (void)
Reset WIZCHIP by softly. More...
int8_t | wizchip_init (uint8_t *txsize, uint8_t *rxsize)
Initializes WIZCHIP with socket buffer size. More...
void | wizchip_clrinterrupt (intr_kind intr)
Clear Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterrupt (void)
Get Interrupt of WIZCHIP. More...
void | wizchip_setinterruptmask (intr_kind intr)
Mask or Unmask Interrupt of WIZCHIP. More...
intr_kind | wizchip_getinterruptmask (void)
Get Interrupt mask of WIZCHIP. More...
int8_t | wizphy_getphylink (void)
get the link status of phy in WIZCHIP. No use in W5100 More...
int8_t | wizphy_getphypmode (void)
get the power mode of PHY in WIZCHIP. No use in W5100 More...
void | wizphy_reset (void)
Reset phy. Vailid only in W5500. More...
void | wizphy_setphyconf (wiz_PhyConf *phyconf)
Set the phy information for WIZCHIP without power mode. More...
void | wizphy_getphyconf (wiz_PhyConf *phyconf)
Get phy configuration information. More...
void | wizphy_getphystat (wiz_PhyConf *phyconf)
Get phy status. More...
int8_t | wizphy_setphypmode (uint8_t pmode)
set the power mode of phy inside WIZCHIP. Refer to PHYCFGR in W5500, PHYSTATUS in W5200 More...
void | wizchip_setnetinfo (wiz_NetInfo *pnetinfo)
Set the network information for WIZCHIP. More...
void | wizchip_getnetinfo (wiz_NetInfo *pnetinfo)
Get the network information for WIZCHIP. More...
int8_t | wizchip_setnetmode (netmode_type netmode)
Set the network mode such WOL, PPPoE, Ping Block, and etc. More...
netmode_type | wizchip_getnetmode (void)
Get the network mode such WOL, PPPoE, Ping Block, and etc. More...
void | wizchip_settimeout (wiz_NetTimeout *nettime)
Set retry time value(RTR) and retry count(RCR). More...
void | wizchip_gettimeout (wiz_NetTimeout *nettime)
Get retry time value(RTR) and retry count(RCR). More...

Variables

_WIZCHIP WIZCHIP

Detailed Description

WIZCHIP Config Header File.

Version
1.0.0
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file wizchip_conf.h.

Macro Definition Documentation

#define _WIZCHIP_ 5500

Select WIZCHIP.

Todo:
You should select one, 5100, 5200 ,5500 or etc.

ex> #define _WIZCHIP_ 5500

Definition at line 63 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_NONE_ 0x0000

Definition at line 65 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_BUS_ 0x0100

Bus interface mode

Definition at line 66 of file wizchip_conf.h.

Referenced by reg_wizchip_bus_cbfunc().

#define _WIZCHIP_IO_MODE_SPI_ 0x0200

SPI interface mode

Definition at line 67 of file wizchip_conf.h.

Referenced by reg_wizchip_spi_cbfunc(), and reg_wizchip_spiburst_cbfunc().

#define _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1)

BUS interface mode for direct

Definition at line 73 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2)

BUS interface mode for indirect

Definition at line 74 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1)

SPI interface mode for variable length data

Definition at line 76 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2)

SPI interface mode for fixed length data mode

Definition at line 77 of file wizchip_conf.h.

#define _WIZCHIP_ID_ "W5500\0"

Definition at line 103 of file wizchip_conf.h.

#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_

Define interface mode.
.

Todo:
Should select interface mode as chip.
  • _WIZCHIP_IO_MODE_SPI_
    -_WIZCHIP_IO_MODE_SPI_VDM_ : Valid only in _WIZCHIP_ == 5500
    -_WIZCHIP_IO_MODE_SPI_FDM_ : Valid only in _WIZCHIP_ == 5500
  • _WIZCHIP_IO_MODE_BUS_
    • _WIZCHIP_IO_MODE_BUS_DIR_
    • _WIZCHIP_IO_MODE_BUS_INDIR_
  • Others will be defined in future.

    ex> #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_

Definition at line 119 of file wizchip_conf.h.

#define _WIZCHIP_IO_BASE_ 0x00000000

Define I/O base address when BUS IF mode.

Todo:
Should re-define it to fit your system when BUS IF Mode (_WIZCHIP_IO_MODE_BUS_, _WIZCHIP_IO_MODE_BUS_DIR_, _WIZCHIP_IO_MODE_BUS_INDIR_).

ex> #define _WIZCHIP_IO_BASE_ 0x00008000

Definition at line 135 of file wizchip_conf.h.

#define _WIZCHIP_SOCK_NUM_ 8

The count of independant socket of WIZCHIP.

Definition at line 146 of file wizchip_conf.h.

Referenced by ctlwizchip(), and wizchip_init().

#define PHY_CONFBY_HW 0

Configured PHY operation mode by HW pin.

Definition at line 292 of file wizchip_conf.h.

Referenced by wizphy_getphyconf().

#define PHY_CONFBY_SW 1

Configured PHY operation mode by SW register.

Definition at line 293 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHY_MODE_MANUAL 0

Configured PHY operation mode with user setting.

Definition at line 294 of file wizchip_conf.h.

Referenced by wizphy_getphyconf().

#define PHY_MODE_AUTONEGO 1

Configured PHY operation mode with auto-negotiation.

Definition at line 295 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHY_SPEED_10 0

Link Speed 10.

Definition at line 296 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_getphystat().

#define PHY_SPEED_100 1

Link Speed 100.

Definition at line 297 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), wizphy_getphystat(), and wizphy_setphyconf().

#define PHY_DUPLEX_HALF 0

Link Half-Duplex.

Definition at line 298 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), and wizphy_getphystat().

#define PHY_DUPLEX_FULL 1

Link Full-Duplex.

Definition at line 299 of file wizchip_conf.h.

Referenced by wizphy_getphyconf(), wizphy_getphystat(), and wizphy_setphyconf().

#define PHY_LINK_OFF 0

Link Off.

Definition at line 300 of file wizchip_conf.h.

Referenced by wizphy_getphylink().

#define PHY_LINK_ON 1

Link On.

Definition at line 301 of file wizchip_conf.h.

Referenced by wizphy_getphylink().

#define PHY_POWER_NORM 0

PHY power normal mode.

Definition at line 302 of file wizchip_conf.h.

Referenced by wizphy_getphypmode().

#define PHY_POWER_DOWN 1

PHY power down mode.

Definition at line 303 of file wizchip_conf.h.

Referenced by wizphy_getphypmode(), and wizphy_setphypmode().

Function Documentation

void reg_wizchip_cris_cbfunc | ( | void(*)(void) | cris_en,
 |  | void(*)(void) | cris_ex
 | ) |  |

Registers call back function for critical section of I/O functions such as WIZCHIP_READ, WIZCHIP_WRITE, WIZCHIP_READ_BUF and WIZCHIP_WRITE_BUF.

Parameters
cris_en | : callback function for critical section enter.
cris_ex | : callback function for critical section exit.
Todo:
Describe WIZCHIP_CRITICAL_ENTER and WIZCHIP_CRITICAL_EXIT marco or register your functions.
Note
If you do not describe or register, default functions(wizchip_cris_enter & wizchip_cris_exit) is called.

Definition at line 186 of file wizchip_conf.c.

References __WIZCHIP::_CRIS::_enter, __WIZCHIP::_CRIS::_exit, __WIZCHIP::CRIS, wizchip_cris_enter(), and wizchip_cris_exit().

void reg_wizchip_cs_cbfunc | ( | void(*)(void) | cs_sel,
 |  | void(*)(void) | cs_desel
 | ) |  |

Registers call back function for WIZCHIP select & deselect.

Parameters
cs_sel | : callback function for WIZCHIP select
cs_desel | : callback fucntion for WIZCHIP deselect
Todo:
Describe wizchip_cs_select and wizchip_cs_deselect function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 200 of file wizchip_conf.c.

References __WIZCHIP::_CS::_deselect, __WIZCHIP::_CS::_select, __WIZCHIP::CS, wizchip_cs_deselect(), and wizchip_cs_select().

void reg_wizchip_bus_cbfunc | ( | uint8_t(*)(uint32_t addr) | bus_rb,
 |  | void(*)(uint32_t addr, uint8_t wb) | bus_wb
 | ) |  |

Registers call back function for bus interface.

Parameters
bus_rb | : callback function to read byte data using system bus
bus_wb | : callback function to write byte data using system bus
Todo:
Describe wizchip_bus_readbyte and wizchip_bus_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 214 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_byte, _WIZCHIP_IO_MODE_BUS_, __WIZCHIP::_IF::_write_byte, __WIZCHIP::_IF::BUS, __WIZCHIP::IF, __WIZCHIP::if_mode, wizchip_bus_readbyte(), and wizchip_bus_writebyte().

void reg_wizchip_spi_cbfunc | ( | uint8_t(*)(void) | spi_rb,
 |  | void(*)(uint8_t wb) | spi_wb
 | ) |  |

Registers call back function for SPI interface.

Parameters
spi_rb | : callback function to read byte using SPI
spi_wb | : callback function to write byte using SPI
Todo:
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 230 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_byte, _WIZCHIP_IO_MODE_SPI_, __WIZCHIP::_IF::_write_byte, __WIZCHIP::IF, __WIZCHIP::if_mode, __WIZCHIP::_IF::SPI, wizchip_spi_readbyte(), and wizchip_spi_writebyte().

void reg_wizchip_spiburst_cbfunc | ( | void(*)(uint8_t *pBuf, uint16_t len) | spi_rb,
 |  | void(*)(uint8_t *pBuf, uint16_t len) | spi_wb
 | ) |  |

Registers call back function for SPI interface.

Parameters
spi_rb | : callback function to burst read using SPI
spi_wb | : callback function to burst write using SPI
Todo:
Describe wizchip_spi_readbyte and wizchip_spi_writebyte function or register your functions.
Note
If you do not describe or register, null function is called.

Definition at line 247 of file wizchip_conf.c.

References __WIZCHIP::_IF::_read_burst, _WIZCHIP_IO_MODE_SPI_, __WIZCHIP::_IF::_write_burst, __WIZCHIP::IF, __WIZCHIP::if_mode, __WIZCHIP::_IF::SPI, wizchip_spi_readburst(), and wizchip_spi_writeburst().

int8_t wizphy_getphylink ( void )

get the link status of phy in WIZCHIP. No use in W5100

Definition at line 504 of file wizchip_conf.c.

References getPHYCFGR, getPHYSTATUS, PHY_LINK_OFF, PHY_LINK_ON, PHYCFGR_LNK_ON, and PHYSTATUS_LINK.

Referenced by ctlwizchip().

int8_t wizphy_getphypmode ( void )

get the power mode of PHY in WIZCHIP. No use in W5100

Definition at line 525 of file wizchip_conf.c.

References getPHYCFGR, getPHYSTATUS, PHY_POWER_DOWN, PHY_POWER_NORM, PHYCFGR_OPMDC_PDOWN, and PHYSTATUS_POWERDOWN.

Referenced by ctlwizchip().

void wizphy_reset ( void )

Reset phy. Vailid only in W5500.

Definition at line 546 of file wizchip_conf.c.

References getPHYCFGR, PHYCFGR_RST, and setPHYCFGR.

Referenced by ctlwizchip(), wizphy_setphyconf(), and wizphy_setphypmode().

Variable Documentation

_WIZCHIP WIZCHIP

\ref _WIZCHIP instance

Definition at line 168 of file wizchip_conf.c.

Referenced by WIZCHIP_READ(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE(), and WIZCHIP_WRITE_BUF().

Generated on Thu Apr 9 2015 14:44:03 for Socket APIs by doxygen 1.8.4


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Here is a list of all file members with links to the files they belong to:

- _ -

  • _IMR_ : w5100.h , w5200.h , w5500.h
  • _RCR_ : w5100.h , w5200.h , w5500.h
  • _RTR_ : w5200.h , w5500.h , w5100.h
  • _W5100_IO_BASE_ : w5100.h
  • _W5200_SPI_READ_ : w5200.h
  • _W5200_SPI_WRITE_ : w5200.h
  • _W5500_IO_BASE_ : w5500.h
  • _W5500_SPI_FDM_OP_LEN1_ : w5500.c
  • _W5500_SPI_FDM_OP_LEN2_ : w5500.c
  • _W5500_SPI_FDM_OP_LEN4_ : w5500.c
  • _W5500_SPI_READ_ : w5500.h
  • _W5500_SPI_VDM_OP_ : w5500.c
  • _W5500_SPI_WRITE_ : w5500.h
  • _WIZCHIP : wizchip_conf.h
  • _WIZCHIP_ : wizchip_conf.h
  • _WIZCHIP_ID_ : wizchip_conf.h
  • _WIZCHIP_IO_BASE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_DIR_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_INDIR_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_NONE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_FDM_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_VDM_ : wizchip_conf.h
  • _WIZCHIP_IO_RXBUF_ : w5100.h , w5200.h
  • _WIZCHIP_IO_TXBUF_ : w5100.h , w5200.h
  • _WIZCHIP_SN_BASE_ : w5200.h , w5100.h
  • _WIZCHIP_SN_SIZE_ : w5100.h , w5200.h
  • _WIZCHIP_SOCK_NUM_ : wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- c -

  • CHECK_SOCKDATA : socket.c
  • CHECK_SOCKINIT : socket.c
  • CHECK_SOCKMODE : socket.c
  • CHECK_SOCKNUM : socket.c
  • close() : socket.c , socket.h
  • CN_GET_NETINFO : wizchip_conf.h
  • CN_GET_NETMODE : wizchip_conf.h
  • CN_GET_TIMEOUT : wizchip_conf.h
  • CN_SET_NETINFO : wizchip_conf.h
  • CN_SET_NETMODE : wizchip_conf.h
  • CN_SET_TIMEOUT : wizchip_conf.h
  • connect() : socket.c , socket.h
  • CS_CLR_INTERRUPT : socket.h
  • CS_GET_INTERRUPT : socket.h
  • CS_GET_INTMASK : socket.h
  • CS_GET_IOMODE : socket.h
  • CS_GET_MAXRXBUF : socket.h
  • CS_GET_MAXTXBUF : socket.h
  • CS_SET_INTMASK : socket.h
  • CS_SET_IOMODE : socket.h
  • ctlnetwork() : wizchip_conf.c , wizchip_conf.h
  • ctlnetwork_type : wizchip_conf.h
  • ctlsock_type : socket.h
  • ctlsocket() : socket.c , socket.h
  • ctlwizchip() : wizchip_conf.c , wizchip_conf.h
  • ctlwizchip_type : wizchip_conf.h
  • CW_CLR_INTERRUPT : wizchip_conf.h
  • CW_GET_ID : wizchip_conf.h
  • CW_GET_INTERRUPT : wizchip_conf.h
  • CW_GET_INTRMASK : wizchip_conf.h
  • CW_GET_INTRTIME : wizchip_conf.h
  • CW_GET_PHYCONF : wizchip_conf.h
  • CW_GET_PHYLINK : wizchip_conf.h
  • CW_GET_PHYPOWMODE : wizchip_conf.h
  • CW_GET_PHYSTATUS : wizchip_conf.h
  • CW_INIT_WIZCHIP : wizchip_conf.h
  • CW_RESET_PHY : wizchip_conf.h
  • CW_RESET_WIZCHIP : wizchip_conf.h
  • CW_SET_INTRMASK : wizchip_conf.h
  • CW_SET_INTRTIME : wizchip_conf.h
  • CW_SET_PHYCONF : wizchip_conf.h
  • CW_SET_PHYPOWMODE : wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


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Here is a list of all file members with links to the files they belong to:

- d -

  • dhcp_mode : wizchip_conf.h
  • disconnect() : socket.h , socket.c
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- g -

  • GAR : w5100.h , w5200.h , w5500.h
  • getGAR : w5100.h , w5200.h , w5500.h
  • getIMR : w5200.h , w5500.h , w5100.h
  • getIMR2 : w5200.h
  • getINTLEVEL : w5200.h , w5500.h
  • getIR : w5100.h , w5200.h , w5500.h
  • getIR2 : w5200.h
  • getMR : w5100.h , w5200.h , w5500.h
  • getPATR : w5100.h , w5200.h
  • getPHAR : w5500.h
  • getPHYCFGR : w5500.h
  • getPHYSTATUS : w5200.h
  • getPMAGIC : w5100.h , w5200.h , w5500.h
  • getPMRU : w5500.h
  • getPPPALGO : w5100.h , w5200.h
  • getPSID : w5500.h
  • getPTIMER : w5100.h , w5200.h , w5500.h
  • getRCR : w5100.h , w5200.h , w5500.h
  • getRMSR : w5100.h
  • getRTR : w5100.h , w5200.h , w5500.h
  • getSHAR : w5100.h , w5200.h , w5500.h
  • getSIMR : w5200.h , w5500.h
  • getSIPR : w5100.h , w5200.h , w5500.h
  • getSIR : w5200.h , w5500.h
  • getSn_CR : w5100.h , w5200.h , w5500.h
  • getSn_DHAR : w5100.h , w5200.h , w5500.h
  • getSn_DIPR : w5100.h , w5200.h , w5500.h
  • getSn_DPORT : w5100.h , w5200.h , w5500.h
  • getSn_FRAG : w5100.h , w5200.h , w5500.h
  • getSn_IMR : w5200.h , w5500.h
  • getSn_IR : w5100.h , w5200.h , w5500.h
  • getSn_KPALVTR : w5500.h
  • getSn_MR : w5100.h , w5200.h , w5500.h
  • getSn_MSSR : w5100.h , w5200.h , w5500.h
  • getSn_PORT : w5100.h , w5200.h , w5500.h
  • getSn_PROTO : w5100.h , w5200.h
  • getSn_RX_RD : w5500.h , w5100.h , w5200.h
  • getSn_RX_RSR() : w5200.h , w5100.c , w5100.h , w5200.c , w5500.c , w5500.h
  • getSn_RX_WR : w5100.h , w5500.h , w5200.h
  • getSn_RxBASE() : w5100.c , w5100.h , w5200.c , w5200.h
  • getSn_RXBUF_SIZE : w5100.h , w5200.h , w5500.h
  • getSn_RxMASK : w5100.h , w5200.h
  • getSn_RxMAX : w5200.h , w5100.h , w5500.h
  • getSn_RXMEM_SIZE : w5100.h , w5200.h
  • getSn_SR : w5100.h , w5200.h , w5500.h
  • getSn_TOS : w5200.h , w5100.h , w5500.h
  • getSn_TTL : w5200.h , w5500.h , w5100.h
  • getSn_TX_FSR() : w5200.h , w5100.h , w5500.h , w5100.c , w5200.c , w5500.c
  • getSn_TX_RD : w5500.h , w5200.h , w5100.h
  • getSn_TX_WR : w5100.h , w5200.h , w5500.h
  • getSn_TxBASE() : w5100.c , w5100.h , w5200.c , w5200.h
  • getSn_TXBUF_SIZE : w5500.h , w5200.h , w5100.h
  • getSn_TxMASK : w5100.h , w5200.h
  • getSn_TxMAX : w5200.h , w5500.h , w5100.h
  • getSn_TXMEM_SIZE : w5200.h , w5100.h
  • getsockopt() : socket.h , socket.c
  • getSUBR : w5200.h , w5500.h , w5100.h
  • getUIPR : w5500.h
  • getUPORTR : w5500.h
  • getVERSIONR : w5500.h , w5200.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


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Here is a list of all file members with links to the files they belong to:

- i -

  • IINCHIP_READ : w5100.h , w5200.h , w5500.h
  • IINCHIP_READ_BUF : w5100.h , w5200.h , w5500.h
  • IINCHIP_WRITE : w5200.h , w5500.h , w5100.h
  • IINCHIP_WRITE_BUF : w5100.h , w5200.h , w5500.h
  • IK_DEST_UNREACH : wizchip_conf.h
  • IK_IP_CONFLICT : wizchip_conf.h
  • IK_PPPOE_TERMINATED : wizchip_conf.h
  • IK_SOCK_0 : wizchip_conf.h
  • IK_SOCK_1 : wizchip_conf.h
  • IK_SOCK_2 : wizchip_conf.h
  • IK_SOCK_3 : wizchip_conf.h
  • IK_SOCK_4 : wizchip_conf.h
  • IK_SOCK_5 : wizchip_conf.h
  • IK_SOCK_6 : wizchip_conf.h
  • IK_SOCK_7 : wizchip_conf.h
  • IK_SOCK_ALL : wizchip_conf.h
  • IK_WOL : wizchip_conf.h
  • IM_IR4 : w5500.h
  • IM_IR5 : w5500.h
  • IM_IR6 : w5500.h
  • IM_IR7 : w5500.h
  • IMR2 : w5200.h
  • INTLEVEL : w5500.h , w5200.h
  • intr_kind : wizchip_conf.h
  • IPPROTO_GGP : w5100.h , w5200.h , w5500.h
  • IPPROTO_ICMP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IDP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IGMP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IP : w5100.h , w5200.h , w5500.h
  • IPPROTO_ND : w5100.h , w5200.h , w5500.h
  • IPPROTO_PUP : w5100.h , w5200.h , w5500.h
  • IPPROTO_RAW : w5500.h , w5100.h , w5200.h
  • IPPROTO_TCP : w5200.h , w5100.h , w5500.h
  • IPPROTO_UDP : w5100.h , w5200.h , w5500.h
  • IR : w5100.h , w5200.h , w5500.h
  • IR2 : w5200.h
  • IR_CONFLICT : w5100.h , w5200.h , w5500.h
  • IR_MP : w5500.h
  • IR_PPPoE : w5500.h , w5200.h , w5100.h
  • IR_SOCK : w5100.h
  • IR_UNREACH : w5100.h , w5500.h
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- l -

  • listen() : socket.c , socket.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • Enumerator
  • Macros
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  • w
Here is a list of all file members with links to the files they belong to:

- m -

  • MR : w5100.h , w5200.h , w5500.h
  • MR_AI : w5100.h , w5200.h
  • MR_FARP : w5500.h
  • MR_IND : w5200.h , w5100.h
  • MR_PB : w5100.h , w5200.h , w5500.h
  • MR_PPPOE : w5200.h , w5100.h , w5500.h
  • MR_RST : w5100.h , w5500.h , w5200.h
  • MR_WOL : w5200.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • Enumerator
  • Macros
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  • w
Here is a list of all file members with links to the files they belong to:

- n -

  • NETINFO_DHCP : wizchip_conf.h
  • NETINFO_STATIC : wizchip_conf.h
  • netmode_type : wizchip_conf.h
  • NM_FORCEARP : wizchip_conf.h
  • NM_PINGBLOCK : wizchip_conf.h
  • NM_PPPOE : wizchip_conf.h
  • NM_WAKEONLAN : wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • w
Here is a list of all file members with links to the files they belong to:

- p -

  • PACK_COMPLETED : socket.h
  • PACK_FIRST : socket.h
  • PACK_REMAINED : socket.h
  • PATR : w5100.h , w5200.h
  • PHAR : w5500.h
  • PHY_CONFBY_HW : wizchip_conf.h
  • PHY_CONFBY_SW : wizchip_conf.h
  • PHY_DUPLEX_FULL : wizchip_conf.h
  • PHY_DUPLEX_HALF : wizchip_conf.h
  • PHY_LINK_OFF : wizchip_conf.h
  • PHY_LINK_ON : wizchip_conf.h
  • PHY_MODE_AUTONEGO : wizchip_conf.h
  • PHY_MODE_MANUAL : wizchip_conf.h
  • PHY_POWER_DOWN : wizchip_conf.h
  • PHY_POWER_NORM : wizchip_conf.h
  • PHY_SPEED_10 : wizchip_conf.h
  • PHY_SPEED_100 : wizchip_conf.h
  • PHYCFGR : w5500.h
  • PHYCFGR_DPX_FULL : w5500.h
  • PHYCFGR_DPX_HALF : w5500.h
  • PHYCFGR_LNK_OFF : w5500.h
  • PHYCFGR_LNK_ON : w5500.h
  • PHYCFGR_OPMD : w5500.h
  • PHYCFGR_OPMDC_100F : w5500.h
  • PHYCFGR_OPMDC_100FA : w5500.h
  • PHYCFGR_OPMDC_100H : w5500.h
  • PHYCFGR_OPMDC_10F : w5500.h
  • PHYCFGR_OPMDC_10H : w5500.h
  • PHYCFGR_OPMDC_ALLA : w5500.h
  • PHYCFGR_OPMDC_NA : w5500.h
  • PHYCFGR_OPMDC_PDOWN : w5500.h
  • PHYCFGR_RST : w5500.h
  • PHYCFGR_SPD_10 : w5500.h
  • PHYCFGR_SPD_100 : w5500.h
  • PHYSTATUS : w5200.h
  • PHYSTATUS_LINK : w5200.h
  • PHYSTATUS_POWERDOWN : w5200.h
  • PHYSTATUS_POWERSAVE : w5200.h
  • PMAGIC : w5200.h , w5500.h , w5100.h
  • PMRU : w5500.h
  • PPPALGO : w5200.h
  • PSID : w5500.h
  • PTIMER : w5200.h , w5100.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • w
Here is a list of all file members with links to the files they belong to:

- r -

  • recv() : socket.c , socket.h
  • recvfrom() : socket.h , socket.c
  • reg_wizchip_bus_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_cris_cbfunc() : wizchip_conf.h , wizchip_conf.c
  • reg_wizchip_cs_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_spi_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_spiburst_cbfunc() : wizchip_conf.h , wizchip_conf.c
  • RMSR : w5100.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- s -

  • send() : socket.c , socket.h
  • sendto() : socket.h , socket.c
  • setGAR : w5100.h , w5200.h , w5500.h
  • setIMR : w5100.h , w5200.h , w5500.h
  • setIMR2 : w5200.h
  • setINTLEVEL : w5200.h , w5500.h
  • setIR : w5500.h , w5100.h , w5200.h
  • setIR2 : w5200.h
  • setMR : w5100.h , w5200.h , w5500.h
  • setPHAR : w5500.h
  • setPHYCFGR : w5500.h
  • setPMAGIC : w5100.h , w5200.h , w5500.h
  • setPMRU : w5500.h
  • setPSID : w5500.h
  • setPTIMER : w5100.h , w5200.h , w5500.h
  • setRCR : w5200.h , w5500.h , w5100.h
  • setRMSR : w5100.h
  • setRTR : w5100.h , w5200.h , w5500.h
  • setSHAR : w5100.h , w5200.h , w5500.h
  • setSIMR : w5200.h , w5500.h
  • setSIPR : w5100.h , w5200.h , w5500.h
  • setSIR : w5200.h , w5500.h
  • setSn_CR : w5100.h , w5200.h , w5500.h
  • setSn_DHAR : w5100.h , w5200.h , w5500.h
  • setSn_DIPR : w5100.h , w5200.h , w5500.h
  • setSn_DPORT : w5100.h , w5200.h , w5500.h
  • setSn_FRAG : w5100.h , w5200.h , w5500.h
  • setSn_IMR : w5200.h , w5500.h , w5200.h
  • setSn_IR : w5100.h , w5200.h , w5500.h
  • setSn_KPALVTR : w5500.h
  • setSn_MR : w5100.h , w5200.h , w5500.h
  • setSn_MSSR : w5100.h , w5200.h , w5500.h
  • setSn_PORT : w5100.h , w5200.h , w5500.h
  • setSn_PROTO : w5100.h , w5200.h
  • setSn_RX_RD : w5100.h , w5200.h , w5500.h
  • setSn_RX_WR : w5100.h , w5200.h
  • setSn_RXBUF_SIZE : w5100.h , w5200.h , w5500.h
  • setSn_RXMEM_SIZE : w5100.h , w5200.h
  • setSn_TOS : w5100.h , w5200.h , w5500.h
  • setSn_TTL : w5100.h , w5200.h , w5500.h
  • setSn_TX_WR : w5100.h , w5200.h , w5500.h
  • setSn_TXBUF_SIZE : w5100.h , w5200.h , w5500.h
  • setSn_TXMEM_SIZE : w5100.h , w5200.h
  • setsockopt() : socket.c , socket.h
  • setSUBR : w5100.h , w5200.h , w5500.h
  • setTMSR : w5100.h
  • SF_BROAD_BLOCK : socket.h
  • SF_ETHER_OWN : socket.h
  • SF_IGMP_VER2 : socket.h
  • SF_IO_NONBLOCK : socket.h
  • SF_IPv6_BLOCK : socket.h
  • SF_MULTI_BLOCK : socket.h
  • SF_MULTI_ENABLE : socket.h
  • SF_TCP_NODELAY : socket.h
  • SF_UNI_BLOCK : socket.h
  • SHAR : w5100.h , w5200.h , w5500.h
  • SIK_ALL : socket.h
  • SIK_CONNECTED : socket.h
  • SIK_DISCONNECTED : socket.h
  • SIK_RECEIVED : socket.h
  • SIK_SENT : socket.h
  • SIK_TIMEOUT : socket.h
  • SIMR : w5500.h
  • SIPR : w5100.h , w5200.h , w5500.h
  • SIR : w5500.h
  • Sn_CR : w5100.h , w5200.h , w5500.h
  • Sn_CR_CLOSE : w5100.h , w5200.h , w5500.h
  • Sn_CR_CONNECT : w5100.h , w5200.h , w5500.h
  • Sn_CR_DISCON : w5100.h , w5200.h , w5500.h
  • Sn_CR_LISTEN : w5100.h , w5200.h , w5500.h
  • Sn_CR_OPEN : w5100.h , w5200.h , w5500.h
  • Sn_CR_PCJ : w5100.h , w5200.h
  • Sn_CR_PCN : w5100.h , w5200.h
  • Sn_CR_PCON : w5100.h , w5200.h
  • Sn_CR_PCR : w5100.h , w5200.h
  • Sn_CR_PDISCON : w5100.h , w5200.h
  • Sn_CR_RECV : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND_KEEP : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND_MAC : w5100.h , w5200.h , w5500.h
  • Sn_DHAR : w5100.h , w5200.h , w5500.h
  • Sn_DIPR : w5100.h , w5200.h , w5500.h
  • Sn_DPORT : w5100.h , w5200.h , w5500.h
  • Sn_FRAG : w5200.h , w5500.h
  • Sn_IMR : w5200.h , w5500.h
  • Sn_IR : w5100.h , w5200.h , w5500.h
  • Sn_IR_CON : w5200.h , w5100.h , w5500.h
  • Sn_IR_DISCON : w5100.h , w5200.h , w5500.h
  • Sn_IR_PFAIL : w5100.h , w5200.h
  • Sn_IR_PNEXT : w5200.h , w5100.h
  • Sn_IR_PRECV : w5100.h , w5200.h
  • Sn_IR_RECV : w5200.h , w5100.h , w5500.h
  • Sn_IR_SENDOK : w5500.h , w5100.h , w5200.h
  • Sn_IR_TIMEOUT : w5100.h , w5200.h , w5500.h
  • Sn_KPALVTR : w5500.h
  • Sn_MR : w5100.h , w5200.h , w5500.h
  • Sn_MR_BCASTB : w5500.h
  • Sn_MR_CLOSE : w5100.h , w5200.h , w5500.h
  • Sn_MR_IPRAW : w5100.h , w5200.h
  • Sn_MR_MACRAW : w5500.h , w5100.h , w5200.h
  • Sn_MR_MC : w5100.h , w5200.h , w5500.h
  • Sn_MR_MF : w5100.h , w5200.h
  • Sn_MR_MFEN : w5500.h , w5100.h , w5200.h
  • Sn_MR_MIP6B : w5500.h
  • Sn_MR_MMB : w5500.h
  • Sn_MR_MULTI : w5200.h , w5100.h , w5500.h
  • Sn_MR_ND : w5500.h , w5100.h , w5200.h
  • Sn_MR_PPPOE : w5200.h
  • Sn_MR_PPPoE : w5100.h
  • Sn_MR_TCP : w5100.h , w5200.h , w5500.h
  • Sn_MR_UCASTB : w5500.h
  • Sn_MR_UDP : w5200.h , w5100.h , w5500.h
  • Sn_MSSR : w5500.h , w5100.h , w5200.h
  • Sn_PORT : w5200.h , w5100.h , w5500.h
  • Sn_PROTO : w5200.h , w5100.h
  • Sn_RX_RD : w5100.h , w5200.h , w5500.h
  • Sn_RX_RSR : w5200.h , w5100.h , w5500.h
  • Sn_RX_WR : w5200.h , w5500.h , w5100.h
  • Sn_RXBUF_SIZE : w5500.h
  • Sn_RXMEM_SIZE : w5200.h
  • Sn_SR : w5100.h , w5200.h , w5500.h
  • Sn_TOS : w5200.h , w5500.h , w5100.h
  • Sn_TTL : w5100.h , w5500.h , w5200.h
  • Sn_TX_FSR : w5100.h , w5200.h , w5500.h
  • Sn_TX_RD : w5200.h , w5100.h , w5500.h
  • Sn_TX_WR : w5200.h , w5100.h , w5500.h
  • Sn_TXBUF_SIZE : w5500.h
  • Sn_TXMEM_SIZE : w5200.h
  • SO_DESTIP : socket.h
  • SO_DESTPORT : socket.h
  • SO_FLAG : socket.h
  • SO_KEEPALIVEAUTO : socket.h
  • SO_KEEPALIVESEND : socket.h
  • SO_MSS : socket.h
  • SO_PACKINFO : socket.h
  • SO_RECVBUF : socket.h
  • SO_REMAINSIZE : socket.h
  • SO_SENDBUF : socket.h
  • SO_STATUS : socket.h
  • SO_TOS : socket.h
  • SO_TTL : socket.h
  • SOCK_ANY_PORT_NUM : socket.c
  • SOCK_BUSY : socket.h
  • SOCK_CLOSE_WAIT : w5200.h , w5100.h , w5500.h
  • SOCK_CLOSED : w5500.h , w5100.h , w5200.h
  • SOCK_CLOSING : w5100.h , w5500.h , w5200.h
  • SOCK_DGRAM : w5500.h
  • SOCK_ERROR : socket.h
  • SOCK_ESTABLISHED : w5100.h , w5500.h , w5200.h
  • SOCK_FATAL : socket.h
  • SOCK_FIN_WAIT : w5100.h , w5500.h , w5200.h
  • SOCK_INIT : w5200.h , w5500.h , w5100.h
  • SOCK_IO_BLOCK : socket.h
  • SOCK_IO_NONBLOCK : socket.h
  • SOCK_IPRAW : w5100.h , w5200.h
  • SOCK_LAST_ACK : w5100.h , w5500.h , w5200.h
  • SOCK_LISTEN : w5100.h , w5200.h , w5500.h
  • SOCK_MACRAW : w5100.h , w5500.h , w5200.h
  • SOCK_OK : socket.h
  • SOCK_PPPOE : w5200.h , w5100.h
  • SOCK_STREAM : w5500.h
  • SOCK_SYNRECV : w5100.h , w5200.h , w5500.h
  • SOCK_SYNSENT : w5200.h , w5500.h , w5100.h
  • SOCK_TIME_WAIT : w5100.h , w5500.h , w5200.h
  • SOCK_UDP : w5100.h , w5200.h , w5500.h
  • SOCKERR_ARG : socket.h
  • SOCKERR_BUFFER : socket.h
  • SOCKERR_DATALEN : socket.h
  • SOCKERR_IPINVALID : socket.h
  • SOCKERR_PORTZERO : socket.h
  • SOCKERR_SOCKCLOSED : socket.h
  • SOCKERR_SOCKFLAG : socket.h
  • SOCKERR_SOCKINIT : socket.h
  • SOCKERR_SOCKMODE : socket.h
  • SOCKERR_SOCKNUM : socket.h
  • SOCKERR_SOCKOPT : socket.h
  • SOCKERR_SOCKSTATUS : socket.h
  • SOCKERR_TIMEOUT : socket.h
  • SOCKET : socket.h
  • socket() : socket.c , socket.h
  • SOCKFATAL_PACKLEN : socket.h
  • sockint_kind : socket.h
  • sockopt_type : socket.h
  • SUBR : w5500.h , w5200.h , w5100.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- t -

  • TMSR : w5100.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- u -

  • UIPR : w5500.h
  • UIPR0 : w5100.h
  • UPORT0 : w5100.h
  • UPORTR : w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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Here is a list of all file members with links to the files they belong to:

- v -

  • VERSIONR : w5200.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • w
Here is a list of all file members with links to the files they belong to:

- w -

  • wiz_NetInfo : wizchip_conf.h
  • wiz_NetTimeout : wizchip_conf.h
  • wiz_PhyConf : wizchip_conf.h
  • wiz_recv_data() : w5100.c , w5500.c , w5500.h , w5100.h , w5200.c , w5200.h
  • wiz_recv_ignore() : w5100.c , w5100.h , w5200.c , w5200.h , w5500.c , w5500.h
  • wiz_send_data() : w5100.c , w5100.h , w5200.c , w5200.h , w5500.c , w5500.h
  • WIZCHIP : wizchip_conf.c , wizchip_conf.h
  • wizchip_bus_readbyte() : wizchip_conf.c
  • wizchip_bus_writebyte() : wizchip_conf.c
  • wizchip_clrinterrupt() : wizchip_conf.c , wizchip_conf.h
  • WIZCHIP_CREG_BLOCK : w5100.h , w5200.h , w5500.h
  • wizchip_cris_enter() : wizchip_conf.c
  • wizchip_cris_exit() : wizchip_conf.c
  • WIZCHIP_CRITICAL_ENTER : w5100.h , w5200.h , w5500.h
  • WIZCHIP_CRITICAL_EXIT : w5100.h , w5200.h , w5500.h
  • wizchip_cs_deselect() : wizchip_conf.c
  • wizchip_cs_select() : wizchip_conf.c
  • wizchip_getinterrupt() : wizchip_conf.c , wizchip_conf.h
  • wizchip_getinterruptmask() : wizchip_conf.c , wizchip_conf.h
  • wizchip_getnetinfo() : wizchip_conf.c , wizchip_conf.h
  • wizchip_getnetmode() : wizchip_conf.c , wizchip_conf.h
  • wizchip_gettimeout() : wizchip_conf.c , wizchip_conf.h
  • wizchip_init() : wizchip_conf.c , wizchip_conf.h
  • WIZCHIP_OFFSET_INC : w5100.h , w5200.h , w5500.h
  • WIZCHIP_READ() : w5200.h , w5100.c , w5100.h , w5200.c , w5500.c , w5500.h
  • WIZCHIP_READ_BUF() : w5200.c , w5200.h , w5500.c , w5500.h , w5100.h , w5100.c
  • WIZCHIP_RXBUF_BLOCK : w5500.h
  • wizchip_setinterruptmask() : wizchip_conf.c , wizchip_conf.h
  • wizchip_setnetinfo() : wizchip_conf.h , wizchip_conf.c
  • wizchip_setnetmode() : wizchip_conf.c , wizchip_conf.h
  • wizchip_settimeout() : wizchip_conf.h , wizchip_conf.c
  • wizchip_spi_readburst() : wizchip_conf.c
  • wizchip_spi_readbyte() : wizchip_conf.c
  • wizchip_spi_writeburst() : wizchip_conf.c
  • wizchip_spi_writebyte() : wizchip_conf.c
  • WIZCHIP_SREG_BLOCK : w5200.h , w5100.h , w5500.h
  • wizchip_sw_reset() : wizchip_conf.c , wizchip_conf.h
  • WIZCHIP_TXBUF_BLOCK : w5500.h
  • WIZCHIP_WRITE() : w5100.h , w5200.h , w5500.h , w5200.c , w5500.c , w5100.c
  • WIZCHIP_WRITE_BUF() : w5200.c , w5100.h , w5500.c , w5500.h , w5200.h , w5100.c
  • wizphy_getphyconf() : wizchip_conf.h , wizchip_conf.c
  • wizphy_getphylink() : wizchip_conf.c , wizchip_conf.h
  • wizphy_getphypmode() : wizchip_conf.c , wizchip_conf.h
  • wizphy_getphystat() : wizchip_conf.h , wizchip_conf.c
  • wizphy_reset() : wizchip_conf.h , wizchip_conf.c
  • wizphy_setphyconf() : wizchip_conf.h , wizchip_conf.c
  • wizphy_setphypmode() : wizchip_conf.c , wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • c
  • d
  • g
  • l
  • r
  • s
  • w

- c -

  • close() : socket.c , socket.h
  • connect() : socket.h , socket.c
  • ctlnetwork() : wizchip_conf.c , wizchip_conf.h
  • ctlsocket() : socket.c , socket.h
  • ctlwizchip() : wizchip_conf.h , wizchip_conf.c

- d -

  • disconnect() : socket.c , socket.h

- g -

  • getSn_RX_RSR() : w5100.c , w5100.h , w5200.h , w5500.c , w5200.c , w5500.h
  • getSn_RxBASE() : w5100.h , w5200.c , w5200.h , w5100.c
  • getSn_TX_FSR() : w5500.c , w5500.h , w5100.c , w5100.h , w5200.c , w5200.h
  • getSn_TxBASE() : w5100.c , w5100.h , w5200.c , w5200.h
  • getsockopt() : socket.h , socket.c

- l -

  • listen() : socket.c , socket.h

- r -

  • recv() : socket.c , socket.h
  • recvfrom() : socket.h , socket.c
  • reg_wizchip_bus_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_cris_cbfunc() : wizchip_conf.h , wizchip_conf.c
  • reg_wizchip_cs_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_spi_cbfunc() : wizchip_conf.c , wizchip_conf.h
  • reg_wizchip_spiburst_cbfunc() : wizchip_conf.h , wizchip_conf.c

- s -

  • send() : socket.c , socket.h
  • sendto() : socket.h , socket.c
  • setsockopt() : socket.c , socket.h
  • socket() : socket.h , socket.c

- w -

  • wiz_recv_data() : w5100.c , w5100.h , w5200.h , w5500.c , w5200.c , w5500.h
  • wiz_recv_ignore() : w5100.h , w5200.c , w5200.h , w5500.c , w5500.h , w5100.c
  • wiz_send_data() : w5200.h , w5500.c , w5500.h , w5100.c , w5100.h , w5200.c
  • wizchip_bus_readbyte() : wizchip_conf.c
  • wizchip_bus_writebyte() : wizchip_conf.c
  • wizchip_clrinterrupt() : wizchip_conf.c , wizchip_conf.h
  • wizchip_cris_enter() : wizchip_conf.c
  • wizchip_cris_exit() : wizchip_conf.c
  • wizchip_cs_deselect() : wizchip_conf.c
  • wizchip_cs_select() : wizchip_conf.c
  • wizchip_getinterrupt() : wizchip_conf.c , wizchip_conf.h
  • wizchip_getinterruptmask() : wizchip_conf.c , wizchip_conf.h
  • wizchip_getnetinfo() : wizchip_conf.h , wizchip_conf.c
  • wizchip_getnetmode() : wizchip_conf.c , wizchip_conf.h
  • wizchip_gettimeout() : wizchip_conf.c , wizchip_conf.h
  • wizchip_init() : wizchip_conf.c , wizchip_conf.h
  • WIZCHIP_READ() : w5100.c , w5100.h , w5200.c , w5200.h , w5500.c , w5500.h
  • WIZCHIP_READ_BUF() : w5100.c , w5100.h , w5200.c , w5200.h , w5500.c , w5500.h
  • wizchip_setinterruptmask() : wizchip_conf.c , wizchip_conf.h
  • wizchip_setnetinfo() : wizchip_conf.c , wizchip_conf.h
  • wizchip_setnetmode() : wizchip_conf.c , wizchip_conf.h
  • wizchip_settimeout() : wizchip_conf.c , wizchip_conf.h
  • wizchip_spi_readburst() : wizchip_conf.c
  • wizchip_spi_readbyte() : wizchip_conf.c
  • wizchip_spi_writeburst() : wizchip_conf.c
  • wizchip_spi_writebyte() : wizchip_conf.c
  • wizchip_sw_reset() : wizchip_conf.h , wizchip_conf.c
  • WIZCHIP_WRITE() : w5100.h , w5100.c , w5200.h , w5500.h , w5200.c , w5500.c
  • WIZCHIP_WRITE_BUF() : w5500.c , w5100.h , w5500.h , w5200.c , w5100.c , w5200.h
  • wizphy_getphyconf() : wizchip_conf.h , wizchip_conf.c
  • wizphy_getphylink() : wizchip_conf.c , wizchip_conf.h
  • wizphy_getphypmode() : wizchip_conf.c , wizchip_conf.h
  • wizphy_getphystat() : wizchip_conf.c , wizchip_conf.h
  • wizphy_reset() : wizchip_conf.c , wizchip_conf.h
  • wizphy_setphyconf() : wizchip_conf.h , wizchip_conf.c
  • wizphy_setphypmode() : wizchip_conf.h , wizchip_conf.c
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • WIZCHIP : wizchip_conf.c , wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _WIZCHIP : wizchip_conf.h
  • wiz_NetInfo : wizchip_conf.h
  • wiz_NetTimeout : wizchip_conf.h
  • wiz_PhyConf : wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • ctlnetwork_type : wizchip_conf.h
  • ctlsock_type : socket.h
  • ctlwizchip_type : wizchip_conf.h
  • dhcp_mode : wizchip_conf.h
  • intr_kind : wizchip_conf.h
  • netmode_type : wizchip_conf.h
  • sockint_kind : socket.h
  • sockopt_type : socket.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • c
  • i
  • n
  • s

- c -

  • CN_GET_NETINFO : wizchip_conf.h
  • CN_GET_NETMODE : wizchip_conf.h
  • CN_GET_TIMEOUT : wizchip_conf.h
  • CN_SET_NETINFO : wizchip_conf.h
  • CN_SET_NETMODE : wizchip_conf.h
  • CN_SET_TIMEOUT : wizchip_conf.h
  • CS_CLR_INTERRUPT : socket.h
  • CS_GET_INTERRUPT : socket.h
  • CS_GET_INTMASK : socket.h
  • CS_GET_IOMODE : socket.h
  • CS_GET_MAXRXBUF : socket.h
  • CS_GET_MAXTXBUF : socket.h
  • CS_SET_INTMASK : socket.h
  • CS_SET_IOMODE : socket.h
  • CW_CLR_INTERRUPT : wizchip_conf.h
  • CW_GET_ID : wizchip_conf.h
  • CW_GET_INTERRUPT : wizchip_conf.h
  • CW_GET_INTRMASK : wizchip_conf.h
  • CW_GET_INTRTIME : wizchip_conf.h
  • CW_GET_PHYCONF : wizchip_conf.h
  • CW_GET_PHYLINK : wizchip_conf.h
  • CW_GET_PHYPOWMODE : wizchip_conf.h
  • CW_GET_PHYSTATUS : wizchip_conf.h
  • CW_INIT_WIZCHIP : wizchip_conf.h
  • CW_RESET_PHY : wizchip_conf.h
  • CW_RESET_WIZCHIP : wizchip_conf.h
  • CW_SET_INTRMASK : wizchip_conf.h
  • CW_SET_INTRTIME : wizchip_conf.h
  • CW_SET_PHYCONF : wizchip_conf.h
  • CW_SET_PHYPOWMODE : wizchip_conf.h

- i -

  • IK_DEST_UNREACH : wizchip_conf.h
  • IK_IP_CONFLICT : wizchip_conf.h
  • IK_PPPOE_TERMINATED : wizchip_conf.h
  • IK_SOCK_0 : wizchip_conf.h
  • IK_SOCK_1 : wizchip_conf.h
  • IK_SOCK_2 : wizchip_conf.h
  • IK_SOCK_3 : wizchip_conf.h
  • IK_SOCK_4 : wizchip_conf.h
  • IK_SOCK_5 : wizchip_conf.h
  • IK_SOCK_6 : wizchip_conf.h
  • IK_SOCK_7 : wizchip_conf.h
  • IK_SOCK_ALL : wizchip_conf.h
  • IK_WOL : wizchip_conf.h

- n -

  • NETINFO_DHCP : wizchip_conf.h
  • NETINFO_STATIC : wizchip_conf.h
  • NM_FORCEARP : wizchip_conf.h
  • NM_PINGBLOCK : wizchip_conf.h
  • NM_PPPOE : wizchip_conf.h
  • NM_WAKEONLAN : wizchip_conf.h

- s -

  • SIK_ALL : socket.h
  • SIK_CONNECTED : socket.h
  • SIK_DISCONNECTED : socket.h
  • SIK_RECEIVED : socket.h
  • SIK_SENT : socket.h
  • SIK_TIMEOUT : socket.h
  • SO_DESTIP : socket.h
  • SO_DESTPORT : socket.h
  • SO_FLAG : socket.h
  • SO_KEEPALIVEAUTO : socket.h
  • SO_KEEPALIVESEND : socket.h
  • SO_MSS : socket.h
  • SO_PACKINFO : socket.h
  • SO_RECVBUF : socket.h
  • SO_REMAINSIZE : socket.h
  • SO_SENDBUF : socket.h
  • SO_STATUS : socket.h
  • SO_TOS : socket.h
  • SO_TTL : socket.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • c
  • g
  • i
  • m
  • p
  • r
  • s
  • t
  • u
  • v
  • w

- _ -

  • _IMR_ : w5100.h , w5200.h , w5500.h
  • _RCR_ : w5100.h , w5200.h , w5500.h
  • _RTR_ : w5200.h , w5500.h , w5100.h
  • _W5100_IO_BASE_ : w5100.h
  • _W5200_SPI_READ_ : w5200.h
  • _W5200_SPI_WRITE_ : w5200.h
  • _W5500_IO_BASE_ : w5500.h
  • _W5500_SPI_FDM_OP_LEN1_ : w5500.c
  • _W5500_SPI_FDM_OP_LEN2_ : w5500.c
  • _W5500_SPI_FDM_OP_LEN4_ : w5500.c
  • _W5500_SPI_READ_ : w5500.h
  • _W5500_SPI_VDM_OP_ : w5500.c
  • _W5500_SPI_WRITE_ : w5500.h
  • _WIZCHIP_ : wizchip_conf.h
  • _WIZCHIP_ID_ : wizchip_conf.h
  • _WIZCHIP_IO_BASE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_DIR_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_BUS_INDIR_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_NONE_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_FDM_ : wizchip_conf.h
  • _WIZCHIP_IO_MODE_SPI_VDM_ : wizchip_conf.h
  • _WIZCHIP_IO_RXBUF_ : w5200.h , w5100.h
  • _WIZCHIP_IO_TXBUF_ : w5100.h , w5200.h
  • _WIZCHIP_SN_BASE_ : w5200.h , w5100.h
  • _WIZCHIP_SN_SIZE_ : w5200.h , w5100.h
  • _WIZCHIP_SOCK_NUM_ : wizchip_conf.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • c
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  • r
  • s
  • t
  • u
  • v
  • w

- c -

  • CHECK_SOCKDATA : socket.c
  • CHECK_SOCKINIT : socket.c
  • CHECK_SOCKMODE : socket.c
  • CHECK_SOCKNUM : socket.c
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • Macros
  • _
  • c
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  • i
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  • p
  • r
  • s
  • t
  • u
  • v
  • w

- g -

  • GAR : w5100.h , w5200.h , w5500.h
  • getGAR : w5100.h , w5200.h , w5500.h
  • getIMR : w5200.h , w5500.h , w5100.h
  • getIMR2 : w5200.h
  • getINTLEVEL : w5200.h , w5500.h
  • getIR : w5100.h , w5200.h , w5500.h
  • getIR2 : w5200.h
  • getMR : w5100.h , w5200.h , w5500.h
  • getPATR : w5100.h , w5200.h
  • getPHAR : w5500.h
  • getPHYCFGR : w5500.h
  • getPHYSTATUS : w5200.h
  • getPMAGIC : w5100.h , w5200.h , w5500.h
  • getPMRU : w5500.h
  • getPPPALGO : w5100.h , w5200.h
  • getPSID : w5500.h
  • getPTIMER : w5100.h , w5200.h , w5500.h
  • getRCR : w5100.h , w5200.h , w5500.h
  • getRMSR : w5100.h
  • getRTR : w5100.h , w5200.h , w5500.h
  • getSHAR : w5100.h , w5200.h , w5500.h
  • getSIMR : w5200.h , w5500.h
  • getSIPR : w5100.h , w5200.h , w5500.h
  • getSIR : w5200.h , w5500.h
  • getSn_CR : w5100.h , w5200.h , w5500.h
  • getSn_DHAR : w5100.h , w5200.h , w5500.h
  • getSn_DIPR : w5100.h , w5200.h , w5500.h
  • getSn_DPORT : w5100.h , w5200.h , w5500.h
  • getSn_FRAG : w5100.h , w5200.h , w5500.h
  • getSn_IMR : w5200.h , w5500.h
  • getSn_IR : w5100.h , w5500.h , w5200.h
  • getSn_KPALVTR : w5500.h
  • getSn_MR : w5100.h , w5500.h , w5200.h
  • getSn_MSSR : w5100.h , w5200.h , w5500.h
  • getSn_PORT : w5100.h , w5200.h , w5500.h
  • getSn_PROTO : w5100.h , w5200.h
  • getSn_RX_RD : w5500.h , w5100.h , w5200.h
  • getSn_RX_WR : w5100.h , w5200.h , w5500.h
  • getSn_RXBUF_SIZE : w5500.h , w5100.h , w5200.h
  • getSn_RxMASK : w5100.h , w5200.h
  • getSn_RxMAX : w5500.h , w5100.h , w5200.h
  • getSn_RXMEM_SIZE : w5200.h , w5100.h
  • getSn_SR : w5100.h , w5200.h , w5500.h
  • getSn_TOS : w5100.h , w5500.h , w5200.h
  • getSn_TTL : w5200.h , w5100.h , w5500.h
  • getSn_TX_RD : w5200.h , w5100.h , w5500.h
  • getSn_TX_WR : w5200.h , w5500.h , w5100.h
  • getSn_TXBUF_SIZE : w5200.h , w5100.h , w5500.h
  • getSn_TxMASK : w5200.h , w5100.h
  • getSn_TxMAX : w5500.h , w5200.h , w5100.h
  • getSn_TXMEM_SIZE : w5200.h , w5100.h
  • getSUBR : w5100.h , w5200.h , w5500.h
  • getUIPR : w5500.h
  • getUPORTR : w5500.h
  • getVERSIONR : w5500.h , w5200.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • r
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  • t
  • u
  • v
  • w

- i -

  • IINCHIP_READ : w5100.h , w5200.h , w5500.h
  • IINCHIP_READ_BUF : w5100.h , w5200.h , w5500.h
  • IINCHIP_WRITE : w5200.h , w5500.h , w5100.h
  • IINCHIP_WRITE_BUF : w5100.h , w5200.h , w5500.h
  • IM_IR4 : w5500.h
  • IM_IR5 : w5500.h
  • IM_IR6 : w5500.h
  • IM_IR7 : w5500.h
  • IMR2 : w5200.h
  • INTLEVEL : w5200.h , w5500.h
  • IPPROTO_GGP : w5100.h , w5200.h , w5500.h
  • IPPROTO_ICMP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IDP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IGMP : w5100.h , w5200.h , w5500.h
  • IPPROTO_IP : w5100.h , w5200.h , w5500.h
  • IPPROTO_ND : w5100.h , w5200.h , w5500.h
  • IPPROTO_PUP : w5100.h , w5500.h , w5200.h
  • IPPROTO_RAW : w5500.h , w5100.h , w5200.h
  • IPPROTO_TCP : w5200.h , w5100.h , w5500.h
  • IPPROTO_UDP : w5100.h , w5200.h , w5500.h
  • IR : w5100.h , w5500.h , w5200.h
  • IR2 : w5200.h
  • IR_CONFLICT : w5500.h , w5100.h , w5200.h
  • IR_MP : w5500.h
  • IR_PPPoE : w5500.h , w5100.h , w5200.h
  • IR_SOCK : w5100.h
  • IR_UNREACH : w5100.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • r
  • s
  • t
  • u
  • v
  • w

- m -

  • MR : w5100.h , w5200.h , w5500.h
  • MR_AI : w5100.h , w5200.h
  • MR_FARP : w5500.h
  • MR_IND : w5200.h , w5100.h
  • MR_PB : w5100.h , w5200.h , w5500.h
  • MR_PPPOE : w5200.h , w5100.h , w5500.h
  • MR_RST : w5100.h , w5500.h , w5200.h
  • MR_WOL : w5200.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • u
  • v
  • w

- p -

  • PACK_COMPLETED : socket.h
  • PACK_FIRST : socket.h
  • PACK_REMAINED : socket.h
  • PATR : w5100.h , w5200.h
  • PHAR : w5500.h
  • PHY_CONFBY_HW : wizchip_conf.h
  • PHY_CONFBY_SW : wizchip_conf.h
  • PHY_DUPLEX_FULL : wizchip_conf.h
  • PHY_DUPLEX_HALF : wizchip_conf.h
  • PHY_LINK_OFF : wizchip_conf.h
  • PHY_LINK_ON : wizchip_conf.h
  • PHY_MODE_AUTONEGO : wizchip_conf.h
  • PHY_MODE_MANUAL : wizchip_conf.h
  • PHY_POWER_DOWN : wizchip_conf.h
  • PHY_POWER_NORM : wizchip_conf.h
  • PHY_SPEED_10 : wizchip_conf.h
  • PHY_SPEED_100 : wizchip_conf.h
  • PHYCFGR : w5500.h
  • PHYCFGR_DPX_FULL : w5500.h
  • PHYCFGR_DPX_HALF : w5500.h
  • PHYCFGR_LNK_OFF : w5500.h
  • PHYCFGR_LNK_ON : w5500.h
  • PHYCFGR_OPMD : w5500.h
  • PHYCFGR_OPMDC_100F : w5500.h
  • PHYCFGR_OPMDC_100FA : w5500.h
  • PHYCFGR_OPMDC_100H : w5500.h
  • PHYCFGR_OPMDC_10F : w5500.h
  • PHYCFGR_OPMDC_10H : w5500.h
  • PHYCFGR_OPMDC_ALLA : w5500.h
  • PHYCFGR_OPMDC_NA : w5500.h
  • PHYCFGR_OPMDC_PDOWN : w5500.h
  • PHYCFGR_RST : w5500.h
  • PHYCFGR_SPD_10 : w5500.h
  • PHYCFGR_SPD_100 : w5500.h
  • PHYSTATUS : w5200.h
  • PHYSTATUS_LINK : w5200.h
  • PHYSTATUS_POWERDOWN : w5200.h
  • PHYSTATUS_POWERSAVE : w5200.h
  • PMAGIC : w5200.h , w5500.h , w5100.h
  • PMRU : w5500.h
  • PPPALGO : w5200.h
  • PSID : w5500.h
  • PTIMER : w5200.h , w5100.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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- r -

  • RMSR : w5100.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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  • Typedefs
  • Enumerations
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  • u
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  • w

- s -

  • setGAR : w5100.h , w5200.h , w5500.h
  • setIMR : w5100.h , w5200.h , w5500.h
  • setIMR2 : w5200.h
  • setINTLEVEL : w5200.h , w5500.h
  • setIR : w5100.h , w5200.h , w5500.h
  • setIR2 : w5200.h
  • setMR : w5500.h , w5100.h , w5200.h
  • setPHAR : w5500.h
  • setPHYCFGR : w5500.h
  • setPMAGIC : w5100.h , w5200.h , w5500.h
  • setPMRU : w5500.h
  • setPSID : w5500.h
  • setPTIMER : w5100.h , w5200.h , w5500.h
  • setRCR : w5100.h , w5200.h , w5500.h
  • setRMSR : w5100.h
  • setRTR : w5200.h , w5500.h , w5100.h
  • setSHAR : w5100.h , w5200.h , w5500.h
  • setSIMR : w5200.h , w5500.h
  • setSIPR : w5100.h , w5200.h , w5500.h
  • setSIR : w5200.h , w5500.h
  • setSn_CR : w5100.h , w5200.h , w5500.h
  • setSn_DHAR : w5100.h , w5200.h , w5500.h
  • setSn_DIPR : w5100.h , w5200.h , w5500.h
  • setSn_DPORT : w5100.h , w5200.h , w5500.h
  • setSn_FRAG : w5100.h , w5200.h , w5500.h
  • setSn_IMR : w5200.h , w5500.h
  • setSn_IR : w5500.h , w5100.h , w5200.h
  • setSn_KPALVTR : w5500.h
  • setSn_MR : w5100.h , w5200.h , w5500.h
  • setSn_MSSR : w5100.h , w5200.h , w5500.h
  • setSn_PORT : w5100.h , w5200.h , w5500.h
  • setSn_PROTO : w5100.h , w5200.h
  • setSn_RX_RD : w5100.h , w5200.h , w5500.h
  • setSn_RX_WR : w5100.h , w5200.h
  • setSn_RXBUF_SIZE : w5100.h , w5200.h , w5500.h
  • setSn_RXMEM_SIZE : w5100.h , w5200.h
  • setSn_TOS : w5100.h , w5200.h , w5500.h
  • setSn_TTL : w5100.h , w5200.h , w5500.h
  • setSn_TX_WR : w5100.h , w5200.h , w5500.h
  • setSn_TXBUF_SIZE : w5100.h , w5200.h , w5500.h
  • setSn_TXMEM_SIZE : w5100.h , w5200.h
  • setSUBR : w5100.h , w5200.h , w5500.h
  • setTMSR : w5100.h
  • SF_BROAD_BLOCK : socket.h
  • SF_ETHER_OWN : socket.h
  • SF_IGMP_VER2 : socket.h
  • SF_IO_NONBLOCK : socket.h
  • SF_IPv6_BLOCK : socket.h
  • SF_MULTI_BLOCK : socket.h
  • SF_MULTI_ENABLE : socket.h
  • SF_TCP_NODELAY : socket.h
  • SF_UNI_BLOCK : socket.h
  • SHAR : w5100.h , w5200.h , w5500.h
  • SIMR : w5500.h
  • SIPR : w5100.h , w5200.h , w5500.h
  • SIR : w5500.h
  • Sn_CR : w5100.h , w5200.h , w5500.h
  • Sn_CR_CLOSE : w5100.h , w5200.h , w5500.h
  • Sn_CR_CONNECT : w5100.h , w5200.h , w5500.h
  • Sn_CR_DISCON : w5100.h , w5200.h , w5500.h
  • Sn_CR_LISTEN : w5100.h , w5200.h , w5500.h
  • Sn_CR_OPEN : w5100.h , w5200.h , w5500.h
  • Sn_CR_PCJ : w5100.h , w5200.h
  • Sn_CR_PCN : w5100.h , w5200.h
  • Sn_CR_PCON : w5100.h , w5200.h
  • Sn_CR_PCR : w5100.h , w5200.h
  • Sn_CR_PDISCON : w5100.h , w5200.h
  • Sn_CR_RECV : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND_KEEP : w5100.h , w5200.h , w5500.h
  • Sn_CR_SEND_MAC : w5100.h , w5200.h , w5500.h
  • Sn_DHAR : w5100.h , w5200.h , w5500.h
  • Sn_DIPR : w5100.h , w5200.h , w5500.h
  • Sn_DPORT : w5100.h , w5200.h , w5500.h
  • Sn_FRAG : w5200.h , w5500.h
  • Sn_IMR : w5200.h , w5500.h
  • Sn_IR : w5100.h , w5200.h , w5500.h
  • Sn_IR_CON : w5100.h , w5200.h , w5500.h
  • Sn_IR_DISCON : w5500.h , w5100.h , w5200.h
  • Sn_IR_PFAIL : w5100.h , w5200.h
  • Sn_IR_PNEXT : w5200.h , w5100.h
  • Sn_IR_PRECV : w5100.h , w5200.h
  • Sn_IR_RECV : w5200.h , w5100.h , w5500.h
  • Sn_IR_SENDOK : w5100.h , w5200.h , w5500.h
  • Sn_IR_TIMEOUT : w5100.h , w5200.h , w5500.h
  • Sn_KPALVTR : w5500.h
  • Sn_MR : w5100.h , w5200.h , w5500.h
  • Sn_MR_BCASTB : w5500.h
  • Sn_MR_CLOSE : w5100.h , w5200.h , w5500.h
  • Sn_MR_IPRAW : w5100.h , w5200.h
  • Sn_MR_MACRAW : w5100.h , w5200.h , w5500.h
  • Sn_MR_MC : w5100.h , w5200.h , w5500.h
  • Sn_MR_MF : w5100.h , w5200.h
  • Sn_MR_MFEN : w5500.h , w5100.h , w5200.h
  • Sn_MR_MIP6B : w5500.h
  • Sn_MR_MMB : w5500.h
  • Sn_MR_MULTI : w5100.h , w5500.h , w5200.h
  • Sn_MR_ND : w5100.h , w5200.h , w5500.h
  • Sn_MR_PPPOE : w5200.h
  • Sn_MR_PPPoE : w5100.h
  • Sn_MR_TCP : w5100.h , w5200.h , w5500.h
  • Sn_MR_UCASTB : w5500.h
  • Sn_MR_UDP : w5200.h , w5100.h , w5500.h
  • Sn_MSSR : w5200.h , w5100.h , w5500.h
  • Sn_PORT : w5100.h , w5200.h , w5500.h
  • Sn_PROTO : w5100.h , w5200.h
  • Sn_RX_RD : w5100.h , w5200.h , w5500.h
  • Sn_RX_RSR : w5200.h , w5100.h , w5500.h
  • Sn_RX_WR : w5500.h , w5100.h , w5200.h
  • Sn_RXBUF_SIZE : w5500.h
  • Sn_RXMEM_SIZE : w5200.h
  • Sn_SR : w5100.h , w5200.h , w5500.h
  • Sn_TOS : w5200.h , w5500.h , w5100.h
  • Sn_TTL : w5500.h , w5200.h , w5100.h
  • Sn_TX_FSR : w5200.h , w5500.h , w5100.h
  • Sn_TX_RD : w5100.h , w5500.h , w5200.h
  • Sn_TX_WR : w5200.h , w5500.h , w5100.h
  • Sn_TXBUF_SIZE : w5500.h
  • Sn_TXMEM_SIZE : w5200.h
  • SOCK_ANY_PORT_NUM : socket.c
  • SOCK_BUSY : socket.h
  • SOCK_CLOSE_WAIT : w5500.h , w5200.h , w5100.h
  • SOCK_CLOSED : w5500.h , w5100.h , w5200.h
  • SOCK_CLOSING : w5200.h , w5100.h , w5500.h
  • SOCK_DGRAM : w5500.h
  • SOCK_ERROR : socket.h
  • SOCK_ESTABLISHED : w5200.h , w5100.h , w5500.h
  • SOCK_FATAL : socket.h
  • SOCK_FIN_WAIT : w5100.h , w5200.h , w5500.h
  • SOCK_INIT : w5100.h , w5500.h , w5200.h
  • SOCK_IO_BLOCK : socket.h
  • SOCK_IO_NONBLOCK : socket.h
  • SOCK_IPRAW : w5100.h , w5200.h
  • SOCK_LAST_ACK : w5100.h , w5200.h , w5500.h
  • SOCK_LISTEN : w5100.h , w5200.h , w5500.h
  • SOCK_MACRAW : w5500.h , w5100.h , w5200.h
  • SOCK_OK : socket.h
  • SOCK_PPPOE : w5200.h , w5100.h
  • SOCK_STREAM : w5500.h
  • SOCK_SYNRECV : w5100.h , w5500.h , w5200.h
  • SOCK_SYNSENT : w5100.h , w5500.h , w5200.h
  • SOCK_TIME_WAIT : w5200.h , w5500.h , w5100.h
  • SOCK_UDP : w5200.h , w5100.h , w5500.h
  • SOCKERR_ARG : socket.h
  • SOCKERR_BUFFER : socket.h
  • SOCKERR_DATALEN : socket.h
  • SOCKERR_IPINVALID : socket.h
  • SOCKERR_PORTZERO : socket.h
  • SOCKERR_SOCKCLOSED : socket.h
  • SOCKERR_SOCKFLAG : socket.h
  • SOCKERR_SOCKINIT : socket.h
  • SOCKERR_SOCKMODE : socket.h
  • SOCKERR_SOCKNUM : socket.h
  • SOCKERR_SOCKOPT : socket.h
  • SOCKERR_SOCKSTATUS : socket.h
  • SOCKERR_TIMEOUT : socket.h
  • SOCKET : socket.h
  • SOCKFATAL_PACKLEN : socket.h
  • SUBR : w5500.h , w5100.h , w5200.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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- t -

  • TMSR : w5100.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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- u -

  • UIPR : w5500.h
  • UIPR0 : w5100.h
  • UPORT0 : w5100.h
  • UPORTR : w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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- v -

  • VERSIONR : w5200.h , w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: File Members

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- w -

  • WIZCHIP_CREG_BLOCK : w5100.h , w5200.h , w5500.h
  • WIZCHIP_CRITICAL_ENTER : w5100.h , w5200.h , w5500.h
  • WIZCHIP_CRITICAL_EXIT : w5200.h , w5500.h , w5100.h
  • WIZCHIP_OFFSET_INC : w5200.h , w5100.h , w5500.h
  • WIZCHIP_RXBUF_BLOCK : w5500.h
  • WIZCHIP_SREG_BLOCK : w5100.h , w5500.h , w5200.h
  • WIZCHIP_TXBUF_BLOCK : w5500.h
Generated on Thu Apr 9 2015 14:44:07 for Socket APIs by doxygen 1.8.4


Socket APIs: Doxygen/Doxyfile.dox File Reference

Doxygen/Doxyfile.dox File Reference
Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Doxygen/Main_page.txt File Reference

Doxygen/Main_page.txt File Reference
Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a grey border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Socket APIs

Socket APIs

This Socket APIs provide guides to WIZnet Hardwired TCP/IP Chips (WIZCHIP) user.
It contains not olny Socket APIs but also accessing registers, configuration and interface to WIZCHIP.
It proposes to integrate for user application program. It is easy to change the enhanced WIZCHIP and migrate user application.

Available WIZCHIP product
  • W5500
  • W5200
  • W5100
  • Available soon
    • W5300
Version 2.0.0
Release Notes
  • 2013/10/01
    • First Released V1.0.0
  • 2015/04/01
    • Second Released V2.0.0
    • Add W5100 & W5200 to ioLibrary
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Related Pages

Related Pages
Here is a list of all related documentation pages:
\ Todo List
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/socket.c Source File

  • Ethernet
socket.c
Go to the documentation of this file.
1 //*****************************************************************************
2 //
54 //
55 //*****************************************************************************
56 #include "socket.h"
57
58 //M20150401 : Typing Error
59 //#define SOCK_ANY_PORT_NUM 0xC000;
60 #define SOCK_ANY_PORT_NUM 0xC000
61
62 static uint16_t sock_any_port = SOCK_ANY_PORT_NUM;
63 static uint16_t sock_io_mode = 0;
64 static uint16_t sock_is_sending = 0;
65 static uint16_t sock_remained_size[_WIZCHIP_SOCK_NUM_] = {0,0,};
66 static uint8_t sock_pack_info[_WIZCHIP_SOCK_NUM_] = {0,};
67
68 #if _WIZCHIP_ == 5200
69 static uint16_t sock_next_rd[_WIZCHIP_SOCK_NUM_] ={0,};
70 #endif
71
72 #define CHECK_SOCKNUM() \
73 do{ \
74 if(sn > _WIZCHIP_SOCK_NUM_) return SOCKERR_SOCKNUM; \
75 }while(0); \
76
77 #define CHECK_SOCKMODE(mode) \
78 do{ \
79 if((getSn_MR(sn) & 0x0F) != mode) return SOCKERR_SOCKMODE; \
80 }while(0); \
81
82 #define CHECK_SOCKINIT() \
83 do{ \
84 if((getSn_SR(sn) != SOCK_INIT)) return SOCKERR_SOCKINIT; \
85 }while(0); \
86
87 #define CHECK_SOCKDATA() \
88 do{ \
89 if(len == 0) return SOCKERR_DATALEN; \
90 }while(0); \
91
92
93
94 int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag)
95 {
96 CHECK_SOCKNUM();
97 switch(protocol)
98 {
99 case Sn_MR_TCP :
100 {
101 uint8_t taddr[4];
102 getSIPR(taddr);
103 if(taddr == 0) return SOCKERR_SOCKINIT;
104 }
105 case Sn_MR_UDP :
106 case Sn_MR_MACRAW :
107 break;
108 #if ( _WIZCHIP_ < 5200 )
109 case Sn_MR_IPRAW :
110 case Sn_MR_PPPoE :
111 break;
112 #endif
113 default :
114 return SOCKERR_SOCKMODE;
115 }
116 if((flag & 0x06) != 0) return SOCKERR_SOCKFLAG;
117 #if _WIZCHIP_ == 5200
118 if(flag & 0x10) return SOCKERR_SOCKFLAG;
119 #endif
120
121 if(flag != 0)
122 {
123 switch(protocol)
124 {
125 case Sn_MR_TCP:
126 if((flag & (SF_TCP_NODELAY|SF_IO_NONBLOCK))==0) return SOCKERR_SOCKFLAG;
127 break;
128 case Sn_MR_UDP:
129 if(flag & SF_IGMP_VER2)
130 {
131 if((flag & SF_MULTI_ENABLE)==0) return SOCKERR_SOCKFLAG;
132 }
133 #if _WIZCHIP_ == 5500
134 if(flag & SF_UNI_BLOCK)
135 {
136 if((flag & SF_MULTI_ENABLE) == 0) return SOCKERR_SOCKFLAG;
137 }
138 #endif
139 break;
140 default:
141 break;
142 }
143 }
144 close(sn);
145 setSn_MR(sn, (protocol | (flag & 0xF0)));
146 if(!port)
147 {
148 port = sock_any_port++;
149 if(sock_any_port == 0xFFF0) sock_any_port = SOCK_ANY_PORT_NUM;
150 }
151 setSn_PORT(sn,port);
152 setSn_CR(sn,Sn_CR_OPEN);
153 while(getSn_CR(sn));
154 //A20150401 : For release the previous sock_io_mode
155 sock_io_mode &= ~(1 <<sn);
156 //
157 sock_io_mode |= ((flag & SF_IO_NONBLOCK) << sn);
158 sock_is_sending &= ~(1<<sn);
159 sock_remained_size[sn] = 0;
160 sock_pack_info[sn] = 0;
161 while(getSn_SR(sn) == SOCK_CLOSED);
162 return (int8_t)sn;
163 }
164
165 int8_t close(uint8_t sn)
166 {
167 CHECK_SOCKNUM();
168
169 setSn_CR(sn,Sn_CR_CLOSE);
170 /* wait to process the command... */
171 while( getSn_CR(sn) );
172 /* clear all interrupt of the socket. */
173 setSn_IR(sn, 0xFF);
174 //A20150401 : Release the sock_io_mode of socket n.
175 sock_io_mode &= ~(1<<sn);
176 //
177 sock_is_sending &= ~(1<<sn);
178 sock_remained_size[sn] = 0;
179 sock_pack_info[sn] = 0;
180 while(getSn_SR(sn) != SOCK_CLOSED);
181 return SOCK_OK;
182 }
183
184 int8_t listen(uint8_t sn)
185 {
186 CHECK_SOCKNUM();
187 CHECK_SOCKMODE(Sn_MR_TCP);
188 CHECK_SOCKINIT();
189 setSn_CR(sn,Sn_CR_LISTEN);
190 while(getSn_CR(sn));
191 while(getSn_SR(sn) != SOCK_LISTEN)
192 {
193 if(getSn_CR(sn) == SOCK_CLOSED)
194 {
195 close(sn);
196 return SOCKERR_SOCKCLOSED;
197 }
198 }
199 return SOCK_OK;
200 }
201
202
203 int8_t connect(uint8_t sn, uint8_t * addr, uint16_t port)
204 {
205 CHECK_SOCKNUM();
206 CHECK_SOCKMODE(Sn_MR_TCP);
207 CHECK_SOCKINIT();
208 //M20140501 : For avoiding fatal error on memory align mismatched
209 //if( *((uint32_t*)addr) == 0xFFFFFFFF || *((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
210 {
211 uint32_t taddr;
212 taddr = ((uint32_t)addr[0] & 0x000000FF);
213 taddr = (taddr << 8) + ((uint32_t)addr[1] & 0x000000FF);
214 taddr = (taddr << 8) + ((uint32_t)addr[2] & 0x000000FF);
215 taddr = (taddr << 8) + ((uint32_t)addr[3] & 0x000000FF);
216 if( taddr == 0xFFFFFFFF || taddr == 0) return SOCKERR_IPINVALID;
217 }
218 //
219
220 if(port == 0) return SOCKERR_PORTZERO;
221 setSn_DIPR(sn,addr);
222 setSn_DPORT(sn,port);
223 setSn_CR(sn,Sn_CR_CONNECT);
224 while(getSn_CR(sn));
225 if(sock_io_mode & (1<<sn)) return SOCK_BUSY;
226 while(getSn_SR(sn) != SOCK_ESTABLISHED)
227 {
228 if (getSn_IR(sn) & Sn_IR_TIMEOUT)
229 {
230 setSn_IR(sn, Sn_IR_TIMEOUT);
231 return SOCKERR_TIMEOUT;
232 }
233
234 if (getSn_SR(sn) == SOCK_CLOSED)
235 {
236 return SOCKERR_SOCKCLOSED;
237 }
238 }
239
240 return SOCK_OK;
241 }
242
243 int8_t disconnect(uint8_t sn)
244 {
245 CHECK_SOCKNUM();
246 CHECK_SOCKMODE(Sn_MR_TCP);
247 setSn_CR(sn,Sn_CR_DISCON);
248 /* wait to process the command... */
249 while(getSn_CR(sn));
250 sock_is_sending &= ~(1<<sn);
251 if(sock_io_mode & (1<<sn)) return SOCK_BUSY;
252 while(getSn_SR(sn) != SOCK_CLOSED)
253 {
254 if(getSn_IR(sn) & Sn_IR_TIMEOUT)
255 {
256 close(sn);
257 return SOCKERR_TIMEOUT;
258 }
259 }
260 return SOCK_OK;
261 }
262
263 int32_t send(uint8_t sn, uint8_t * buf, uint16_t len)
264 {
265 uint8_t tmp=0;
266 uint16_t freesize=0;
267
268 CHECK_SOCKNUM();
269 CHECK_SOCKMODE(Sn_MR_TCP);
270 CHECK_SOCKDATA();
271 tmp = getSn_SR(sn);
272 if(tmp != SOCK_ESTABLISHED && tmp != SOCK_CLOSE_WAIT) return SOCKERR_SOCKSTATUS;
273 if( sock_is_sending & (1<<sn) )
274 {
275 tmp = getSn_IR(sn);
276 if(tmp & Sn_IR_SENDOK)
277 {
278 setSn_IR(sn, Sn_IR_SENDOK);
279 //M20150401 : Typing Error
280 //#if _WZICHIP_ == 5200
281 #if _WIZCHIP_ == 5200
282 if(getSn_TX_RD(sn) != sock_next_rd[sn])
283 {
284 setSn_CR(sn,Sn_CR_SEND);
285 while(getSn_CR(sn));
286 return SOCK_BUSY;
287 }
288 #endif
289 sock_is_sending &= ~(1<<sn);
290 }
291 else if(tmp & Sn_IR_TIMEOUT)
292 {
293 close(sn);
294 return SOCKERR_TIMEOUT;
295 }
296 else return SOCK_BUSY;
297 }
298 freesize = getSn_TxMAX(sn);
299 if (len > freesize) len = freesize; // check size not to exceed MAX size.
300 while(1)
301 {
302 freesize = getSn_TX_FSR(sn);
303 tmp = getSn_SR(sn);
304 if ((tmp != SOCK_ESTABLISHED) && (tmp != SOCK_CLOSE_WAIT))
305 {
306 close(sn);
307 return SOCKERR_SOCKSTATUS;
308 }
309 if( (sock_io_mode & (1<<sn)) && (len > freesize) ) return SOCK_BUSY;
310 if(len <= freesize) break;
311 }
312 wiz_send_data(sn, buf, len);
313 #if _WIZCHIP_ == 5200
314 sock_next_rd[sn] = getSn_TX_RD(sn) + len;
315 #endif
316 setSn_CR(sn,Sn_CR_SEND);
317 /* wait to process the command... */
318 while(getSn_CR(sn));
319 sock_is_sending |= (1 << sn);
320 //M20150409 : Explicit Type Casting
321 //return len;
322 return (int32_t)len;
323 }
324
325
326 int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len)
327 {
328 uint8_t tmp = 0;
329 uint16_t recvsize = 0;
330 CHECK_SOCKNUM();
331 CHECK_SOCKMODE(Sn_MR_TCP);
332 CHECK_SOCKDATA();
333
334 recvsize = getSn_RxMAX(sn);
335 if(recvsize < len) len = recvsize;
336 while(1)
337 {
338 recvsize = getSn_RX_RSR(sn);
339 tmp = getSn_SR(sn);
340 if (tmp != SOCK_ESTABLISHED)
341 {
342 if(tmp == SOCK_CLOSE_WAIT)
343 {
344 if(recvsize != 0) break;
345 else if(getSn_TX_FSR(sn) == getSn_TxMAX(sn))
346 {
347 close(sn);
348 return SOCKERR_SOCKSTATUS;
349 }
350 }
351 else
352 {
353 close(sn);
354 return SOCKERR_SOCKSTATUS;
355 }
356 }
357 if((sock_io_mode & (1<<sn)) && (recvsize == 0)) return SOCK_BUSY;
358 if(recvsize != 0) break;
359 };
360 if(recvsize < len) len = recvsize;
361 wiz_recv_data(sn, buf, len);
362 setSn_CR(sn,Sn_CR_RECV);
363 while(getSn_CR(sn));
364 //M20150409 : Explicit Type Casting
365 //return len;
366 return (int32_t)len;
367 }
368
369 int32_t sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port)
370 {
371 uint8_t tmp = 0;
372 uint16_t freesize = 0;
373 uint32_t taddr;
374
375 CHECK_SOCKNUM();
376 switch(getSn_MR(sn) & 0x0F)
377 {
378 case Sn_MR_UDP:
379 case Sn_MR_MACRAW:
380 break;
381 default:
382 return SOCKERR_SOCKMODE;
383 }
384 CHECK_SOCKDATA();
385 //M20140501 : For avoiding fatal error on memory align mismatched
386 //if(*((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
387 //{
388 //uint32_t taddr;
389 taddr = ((uint32_t)addr[0]) & 0x000000FF;
390 taddr = (taddr << 8) + ((uint32_t)addr[1] & 0x000000FF);
391 taddr = (taddr << 8) + ((uint32_t)addr[2] & 0x000000FF);
392 taddr = (taddr << 8) + ((uint32_t)addr[3] & 0x000000FF);
393 //}
394 //
395 //if(*((uint32_t*)addr) == 0) return SOCKERR_IPINVALID;
396 if(taddr == 0) return SOCKERR_IPINVALID;
397 if(port == 0) return SOCKERR_PORTZERO;
398 tmp = getSn_SR(sn);
399 if(tmp != SOCK_MACRAW && tmp != SOCK_UDP) return SOCKERR_SOCKSTATUS;
400
401 setSn_DIPR(sn,addr);
402 setSn_DPORT(sn,port);
403 freesize = getSn_TxMAX(sn);
404 if (len > freesize) len = freesize; // check size not to exceed MAX size.
405 while(1)
406 {
407 freesize = getSn_TX_FSR(sn);
408 if(getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
409 if( (sock_io_mode & (1<<sn)) && (len > freesize) ) return SOCK_BUSY;
410 if(len <= freesize) break;
411 };
412 wiz_send_data(sn, buf, len);
413
414 #if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
415 getSIPR((uint8_t*)&taddr);
416 if(taddr == 0)
417 {
418 getSUBR((uint8_t*)&taddr);
419 setSUBR((uint8_t*)"\x00\x00\x00\x00");
420 }
421 else taddr = 0;
422 #endif
423
424 setSn_CR(sn,Sn_CR_SEND);
425 /* wait to process the command... */
426 while(getSn_CR(sn));
427 while(1)
428 {
429 tmp = getSn_IR(sn);
430 if(tmp & Sn_IR_SENDOK)
431 {
432 setSn_IR(sn, Sn_IR_SENDOK);
433 break;
434 }
435 //M:20131104
436 //else if(tmp & Sn_IR_TIMEOUT) return SOCKERR_TIMEOUT;
437 else if(tmp & Sn_IR_TIMEOUT)
438 {
439 setSn_IR(sn, Sn_IR_TIMEOUT);
440 //M20150409 : Fixed the lost of sign bits by type casting.
441 //len = (uint16_t)SOCKERR_TIMEOUT;
442 //break;
443 #if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
444 if(taddr) setSUBR((uint8_t*)&taddr);
445 #endif
446 return SOCKERR_TIMEOUT;
447 }
449 }
450 #if _WIZCHIP_ < 5500 //M20150401 : for WIZCHIP Errata #4, #5 (ARP errata)
451 if(taddr) setSUBR((uint8_t*)&taddr);
452 #endif
453 //M20150409 : Explicit Type Casting
454 //return len;
455 return (int32_t)len;
456 }
457
458
459
460 int32_t recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port)
461 {
462 uint8_t mr;
463 uint8_t head[8];
464 uint16_t pack_len=0;
465
466 CHECK_SOCKNUM();
467 //CHECK_SOCKMODE(Sn_MR_UDP);
468 switch((mr=getSn_MR(sn)) & 0x0F)
469 {
470 case Sn_MR_UDP:
471 case Sn_MR_MACRAW:
472 break;
473 #if ( _WIZCHIP_ < 5200 )
474 case Sn_MR_IPRAW:
475 case Sn_MR_PPPoE:
476 break;
477 #endif
478 default:
479 return SOCKERR_SOCKMODE;
480 }
481 CHECK_SOCKDATA();
482 if(sock_remained_size[sn] == 0)
483 {
484 while(1)
485 {
486 pack_len = getSn_RX_RSR(sn);
487 if(getSn_SR(sn) == SOCK_CLOSED) return SOCKERR_SOCKCLOSED;
488 if( (sock_io_mode & (1<<sn)) && (pack_len == 0) ) return SOCK_BUSY;
489 if(pack_len != 0) break;
490 };
491 }
492 sock_pack_info[sn] = PACK_COMPLETED;
493 switch (mr & 0x07)
494 {
495 case Sn_MR_UDP :
496 if(sock_remained_size[sn] == 0)
497 {
498 wiz_recv_data(sn, head, 8);
499 setSn_CR(sn,Sn_CR_RECV);
500 while(getSn_CR(sn));
501 // read peer's IP address, port number & packet length
502 addr[0] = head[0];
503 addr[1] = head[1];
504 addr[2] = head[2];
505 addr[3] = head[3];
506 *port = head[4];
507 *port = (*port << 8) + head[5];
508 sock_remained_size[sn] = head[6];
509 sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[7];
510 sock_pack_info[sn] = PACK_FIRST;
511 }
512 if(len < sock_remained_size[sn]) pack_len = len;
513 else pack_len = sock_remained_size[sn];
514 //
515 // Need to packet length check (default 1472)
516 //
517 wiz_recv_data(sn, buf, pack_len); // data copy.
518 break;
519 case Sn_MR_MACRAW :
520 if(sock_remained_size[sn] == 0)
521 {
522 wiz_recv_data(sn, head, 2);
523 setSn_CR(sn,Sn_CR_RECV);
524 while(getSn_CR(sn));
525 // read peer's IP address, port number & packet length
526 sock_remained_size[sn] = head[0];
527 sock_remained_size[sn] = (sock_remained_size[sn] <<8) + head[1];
528 if(sock_remained_size[sn] > 1514)
529 {
530 close(sn);
531 return SOCKFATAL_PACKLEN;
532 }
533 sock_pack_info[sn] = PACK_FIRST;
534 }
535 if(len < sock_remained_size[sn]) pack_len = len;
536 else pack_len = sock_remained_size[sn];
537 wiz_recv_data(sn,buf,pack_len);
538 break;
539 #if ( _WIZCHIP_ < 5200 )
540 case Sn_MR_IPRAW:
541 if(sock_remained_size[sn] == 0)
542 {
543 wiz_recv_data(sn, head, 6);
544 setSn_CR(sn,Sn_CR_RECV);
545 while(getSn_CR(sn));
546 addr[0] = head[0];
547 addr[1] = head[1];
548 addr[2] = head[2];
549 addr[3] = head[3];
550 sock_remained_size[sn] = head[4];
551 //M20150401 : For Typing Error
552 //sock_remaiend_size[sn] = (sock_remained_size[sn] << 8) + head[5];
553 sock_remained_size[sn] = (sock_remained_size[sn] << 8) + head[5];
554 sock_pack_info[sn] = PACK_FIRST;
555 }
556 //
557 // Need to packet length check
558 //
559 if(len < sock_remained_size[sn]) pack_len = len;
560 else pack_len = sock_remained_size[sn];
561 wiz_recv_data(sn, buf, pack_len); // data copy.
562 break;
563 #endif
564 default:
565 wiz_recv_ignore(sn, pack_len); // data copy.
566 sock_remained_size[sn] = pack_len;
567 break;
568 }
569 setSn_CR(sn,Sn_CR_RECV);
570 /* wait to process the command... */
571 while(getSn_CR(sn)) ;
572 sock_remained_size[sn] -= pack_len;
573 //M20140501 : replace 0x01 with PACK_REMAINED
574 //if(sock_remained_size[sn] != 0) sock_pack_info[sn] |= 0x01;
575 if(sock_remained_size[sn] != 0) sock_pack_info[sn] |= PACK_REMAINED;
576 //
577 //M20150409 : Explicit Type Casting
578 //return pack_len;
579 return (int32_t)pack_len;
580 }
581
582
583 int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg)
584 {
585 uint8_t tmp = 0;
586 CHECK_SOCKNUM();
587 switch(cstype)
588 {
589 case CS_SET_IOMODE:
590 tmp = *((uint8_t*)arg);
591 if(tmp == SOCK_IO_NONBLOCK) sock_io_mode |= (1<<sn);
592 else if(tmp == SOCK_IO_BLOCK) sock_io_mode &= ~(1<<sn);
593 else return SOCKERR_ARG;
594 break;
595 case CS_GET_IOMODE:
596 //M20140501 : implict type casting -> explict type casting
597 //*((uint8_t*)arg) = (sock_io_mode >> sn) & 0x0001;
598 *((uint8_t*)arg) = (uint8_t)((sock_io_mode >> sn) & 0x0001);
599 //
600 break;
601 case CS_GET_MAXTXBUF:
602 *((uint16_t*)arg) = getSn_TxMAX(sn);
603 break;
604 case CS_GET_MAXRXBUF:
605 *((uint16_t*)arg) = getSn_RxMAX(sn);
606 break;
607 case CS_CLR_INTERRUPT:
608 if( (*(uint8_t*)arg) > SIK_ALL) return SOCKERR_ARG;
609 setSn_IR(sn,*(uint8_t*)arg);
610 break;
611 case CS_GET_INTERRUPT:
612 *((uint8_t*)arg) = getSn_IR(sn);
613 break;
614 #if _WIZCHIP_ != 5100
615 case CS_SET_INTMASK:
616 if( (*(uint8_t*)arg) > SIK_ALL) return SOCKERR_ARG;
617 setSn_IMR(sn,*(uint8_t*)arg);
618 break;
619 case CS_GET_INTMASK:
620 *((uint8_t*)arg) = getSn_IMR(sn);
621 break;
622 #endif
623 default:
624 return SOCKERR_ARG;
625 }
626 return SOCK_OK;
627 }
628
629 int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg)
630 {
631 // M20131220 : Remove warning
632 //uint8_t tmp;
633 CHECK_SOCKNUM();
634 switch(sotype)
635 {
636 case SO_TTL:
637 setSn_TTL(sn,*(uint8_t*)arg);
638 break;
639 case SO_TOS:
640 setSn_TOS(sn,*(uint8_t*)arg);
641 break;
642 case SO_MSS:
643 setSn_MSSR(sn,*(uint16_t*)arg);
644 break;
645 case SO_DESTIP:
646 setSn_DIPR(sn, (uint8_t*)arg);
647 break;
648 case SO_DESTPORT:
649 setSn_DPORT(sn, *(uint16_t*)arg);
650 break;
651 #if _WIZCHIP_ != 5100
652 case SO_KEEPALIVESEND:
653 CHECK_SOCKMODE(Sn_MR_TCP);
654 #if _WIZCHIP_ > 5200
655 if(getSn_KPALVTR(sn) != 0) return SOCKERR_SOCKOPT;
656 #endif
657 setSn_CR(sn,Sn_CR_SEND_KEEP);
658 while(getSn_CR(sn) != 0)
659 {
660 // M20131220
661 //if ((tmp = getSn_IR(sn)) & Sn_IR_TIMEOUT)
662 if (getSn_IR(sn) & Sn_IR_TIMEOUT)
663 {
664 setSn_IR(sn, Sn_IR_TIMEOUT);
665 return SOCKERR_TIMEOUT;
666 }
667 }
668 break;
669 #if _WIZCHIP_ > 5200
670 case SO_KEEPALIVEAUTO:
671 CHECK_SOCKMODE(Sn_MR_TCP);
672 setSn_KPALVTR(sn,*(uint8_t*)arg);
673 break;
674 #endif
675 #endif
676 default:
677 return SOCKERR_ARG;
678 }
679 return SOCK_OK;
680 }
681
682 int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg)
683 {
684 CHECK_SOCKNUM();
685 switch(sotype)
686 {
687 case SO_FLAG:
688 *(uint8_t*)arg = getSn_MR(sn) & 0xF0;
689 break;
690 case SO_TTL:
691 *(uint8_t*) arg = getSn_TTL(sn);
692 break;
693 case SO_TOS:
694 *(uint8_t*) arg = getSn_TOS(sn);
695 break;
696 case SO_MSS:
697 *(uint8_t*) arg = getSn_MSSR(sn);
698 break;
699 case SO_DESTIP:
700 getSn_DIPR(sn, (uint8_t*)arg);
701 break;
702 case SO_DESTPORT:
703 *(uint16_t*) arg = getSn_DPORT(sn);
704 break;
705 #if _WIZCHIP_ > 5200
706 case SO_KEEPALIVEAUTO:
707 CHECK_SOCKMODE(Sn_MR_TCP);
708 *(uint16_t*) arg = getSn_KPALVTR(sn);
709 break;
710 #endif
711 case SO_SENDBUF:
712 *(uint16_t*) arg = getSn_TX_FSR(sn);
713 break;
714 case SO_RECVBUF:
715 *(uint16_t*) arg = getSn_RX_RSR(sn);
716 break;
717 case SO_STATUS:
718 *(uint8_t*) arg = getSn_SR(sn);
719 break;
720 case SO_REMAINSIZE:
721 if(getSn_MR(sn) == Sn_MR_TCP)
722 *(uint16_t*)arg = getSn_RX_RSR(sn);
723 else
724 *(uint16_t*)arg = sock_remained_size[sn];
725 break;
726 case SO_PACKINFO:
727 CHECK_SOCKMODE(Sn_MR_TCP);
728 *(uint8_t*)arg = sock_pack_info[sn];
729 break;
730 default:
731 return SOCKERR_SOCKOPT;
732 }
733 return SOCK_OK;
734 }
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/socket.h Source File

  • Ethernet
socket.h
Go to the documentation of this file.
1 //*****************************************************************************
2 //
47 //
48 //*****************************************************************************
85 #ifndef _SOCKET_H_
86 #define _SOCKET_H_
87
88 #include "wizchip_conf.h"
89
90 #define SOCKET uint8_t
91
92 #define SOCK_OK 1
93 #define SOCK_BUSY 0
94 #define SOCK_FATAL -1000
95
96 #define SOCK_ERROR 0
97 #define SOCKERR_SOCKNUM (SOCK_ERROR - 1)
98 #define SOCKERR_SOCKOPT (SOCK_ERROR - 2)
99 #define SOCKERR_SOCKINIT (SOCK_ERROR - 3)
100 #define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4)
101 #define SOCKERR_SOCKMODE (SOCK_ERROR - 5)
102 #define SOCKERR_SOCKFLAG (SOCK_ERROR - 6)
103 #define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7)
104 #define SOCKERR_ARG (SOCK_ERROR - 10)
105 #define SOCKERR_PORTZERO (SOCK_ERROR - 11)
106 #define SOCKERR_IPINVALID (SOCK_ERROR - 12)
107 #define SOCKERR_TIMEOUT (SOCK_ERROR - 13)
108 #define SOCKERR_DATALEN (SOCK_ERROR - 14)
109 #define SOCKERR_BUFFER (SOCK_ERROR - 15)
110
111 #define SOCKFATAL_PACKLEN (SOCK_FATAL - 1)
112
113 /*
114 * SOCKET FLAG
115 */
116 #define SF_ETHER_OWN (Sn_MR_MFEN)
117 #define SF_IGMP_VER2 (Sn_MR_MC)
118 #define SF_TCP_NODELAY (Sn_MR_ND)
119 #define SF_MULTI_ENABLE (Sn_MR_MULTI)
120
121 #if _WIZCHIP_ == 5500
122 #define SF_BROAD_BLOCK (Sn_MR_BCASTB)
123 #define SF_MULTI_BLOCK (Sn_MR_MMB)
124 #define SF_IPv6_BLOCK (Sn_MR_MIP6B)
125 #define SF_UNI_BLOCK (Sn_MR_UCASTB)
126 #endif
127
128 #define SF_IO_NONBLOCK 0x01
129
130 /*
131 * UDP & MACRAW Packet Infomation
132 */
133 #define PACK_FIRST 0x80
134 #define PACK_REMAINED 0x01
135 #define PACK_COMPLETED 0x00
136
137
154 int8_t socket(uint8_t sn, uint8_t protocol, uint16_t port, uint8_t flag);
155
166 int8_t close(uint8_t sn);
167
179 int8_t listen(uint8_t sn);
180
202 int8_t connect(uint8_t sn, uint8_t * addr, uint16_t port);
203
219 int8_t disconnect(uint8_t sn);
220
239 int32_t send(uint8_t sn, uint8_t * buf, uint16_t len);
240
261 int32_t recv(uint8_t sn, uint8_t * buf, uint16_t len);
262
289 int32_t sendto(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t port);
290
319 int32_t recvfrom(uint8_t sn, uint8_t * buf, uint16_t len, uint8_t * addr, uint16_t *port);
320
321
323 // SOCKET CONTROL & OPTION //
325 #define SOCK_IO_BLOCK 0
326 #define SOCK_IO_NONBLOCK 1
327
328
337 typedef enum
338 {
339 SIK_CONNECTED = (1 << 0),
340 SIK_DISCONNECTED = (1 << 1),
341 SIK_RECEIVED = (1 << 2),
342 SIK_TIMEOUT = (1 << 3),
343 SIK_SENT = (1 << 4),
344 SIK_ALL = 0x1F,
345 }sockint_kind;
346
351 typedef enum
352 {
353 CS_SET_IOMODE,
354 CS_GET_IOMODE,
355 CS_GET_MAXTXBUF,
356 CS_GET_MAXRXBUF,
357 CS_CLR_INTERRUPT,
358 CS_GET_INTERRUPT,
359 #if _WIZCHIP_ > 5100
360 CS_SET_INTMASK,
361 CS_GET_INTMASK
362 #endif
363 }ctlsock_type;
364
365
370 typedef enum
371 {
372 SO_FLAG,
373 SO_TTL,
374 SO_TOS,
375 SO_MSS,
376 SO_DESTIP,
377 SO_DESTPORT,
378 #if _WIZCHIP_ != 5100
379 SO_KEEPALIVESEND,
380 #if _WIZCHIP_ > 5200
381 SO_KEEPALIVEAUTO,
382 #endif
383 #endif
384 SO_SENDBUF,
385 SO_RECVBUF,
386 SO_STATUS,
387 SO_REMAINSIZE,
388 SO_PACKINFO
389 }sockopt_type;
390
408 int8_t ctlsocket(uint8_t sn, ctlsock_type cstype, void* arg);
409
436 int8_t setsockopt(uint8_t sn, sockopt_type sotype, void* arg);
437
470 int8_t getsockopt(uint8_t sn, sockopt_type sotype, void* arg);
471
472 #endif // _SOCKET_H_
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

  • Class List
  • Class Index
  • Class Members
__WIZCHIP Member List

This is the complete list of members for __WIZCHIP, including all inherited members.

CRIS | __WIZCHIP
CS | __WIZCHIP
id | __WIZCHIP
IF | __WIZCHIP
if_mode | __WIZCHIP
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _CRIS
__WIZCHIP::_CRIS Member List

This is the complete list of members for __WIZCHIP::_CRIS, including all inherited members.

_enter | __WIZCHIP::_CRIS
_exit | __WIZCHIP::_CRIS
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _CS
__WIZCHIP::_CS Member List

This is the complete list of members for __WIZCHIP::_CS, including all inherited members.

_deselect | __WIZCHIP::_CS
_select | __WIZCHIP::_CS
Generated on Thu Apr 9 2015 14:44:05 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

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  • Class Index
  • Class Members
wiz_NetInfo_t Member List

This is the complete list of members for wiz_NetInfo_t, including all inherited members.

dhcp | wiz_NetInfo_t
dns | wiz_NetInfo_t
gw | wiz_NetInfo_t
ip | wiz_NetInfo_t
mac | wiz_NetInfo_t
sn | wiz_NetInfo_t
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

  • Class List
  • Class Index
  • Class Members
wiz_NetTimeout_t Member List

This is the complete list of members for wiz_NetTimeout_t, including all inherited members.

retry_cnt | wiz_NetTimeout_t
time_100us | wiz_NetTimeout_t
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Socket APIs: Member List

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wiz_PhyConf_t Member List

This is the complete list of members for wiz_PhyConf_t, including all inherited members.

by | wiz_PhyConf_t
duplex | wiz_PhyConf_t
mode | wiz_PhyConf_t
speed | wiz_PhyConf_t
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Member List

  • Class List
  • Class Index
  • Class Members
  • __WIZCHIP
  • _IF
__WIZCHIP::_IF Member List

This is the complete list of members for __WIZCHIP::_IF, including all inherited members.

_read_burst | __WIZCHIP::_IF
_read_byte | __WIZCHIP::_IF
_write_burst | __WIZCHIP::_IF
_write_byte | __WIZCHIP::_IF
BUS | __WIZCHIP::_IF
SPI | __WIZCHIP::_IF
Generated on Thu Apr 9 2015 14:44:06 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5100/w5100.c Source File

  • Ethernet
  • W5100
w5100.c
Go to the documentation of this file.
1 //*****************************************************************************
2 //
38 //
39 //*****************************************************************************
40
41 #include "w5100.h"
42
46 void WIZCHIP_WRITE(uint16_t AddrSel, uint8_t wb )
47 {
48 WIZCHIP_CRITICAL_ENTER();
49 WIZCHIP.CS._select();
50
51 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
52 WIZCHIP.IF.SPI._write_byte(0xF0);
53 WIZCHIP.IF.SPI._write_byte((AddrSel & 0xFF00) >> 8);
54 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF) >> 0);
55 WIZCHIP.IF.SPI._write_byte(wb); // Data write (write 1byte data)
56 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_) )
57 WIZCHIP.IF.BUS._write_byte(AddrSel,wb);
58 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_) )
59
60 //add indirect bus
61 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0xFF00) >> 8);
62 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x00FF));
63 WIZCHIP.IF.BUS._write_byte(IDM_DR,wb);
64 #else
65 #error "Unknown _WIZCHIP_IO_MODE_ in W5100. !!!"
66 #endif
67
68 WIZCHIP.CS._deselect();
69 WIZCHIP_CRITICAL_EXIT();
70 }
74 uint8_t WIZCHIP_READ(uint16_t AddrSel)
75 {
76 uint8_t ret;
77
78 WIZCHIP_CRITICAL_ENTER();
79 WIZCHIP.CS._select();
80
81 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
82 WIZCHIP.IF.SPI._write_byte(0x0F);
83 WIZCHIP.IF.SPI._write_byte((AddrSel & 0xFF00) >> 8);
84 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF) >> 0);
85 ret = WIZCHIP.IF.SPI._read_byte();
86 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_) )
87 ret = WIZCHIP.IF.BUS._read_byte(AddrSel);
88 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_) )
89
90 //add indirect bus
91 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0xFF00) >> 8);
92 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x00FF));
93 ret = WIZCHIP.IF.BUS._read_byte(IDM_DR);
94 #else
95 #error "Unknown _WIZCHIP_IO_MODE_ in W5100. !!!"
96 #endif
97
98 WIZCHIP.CS._deselect();
99 WIZCHIP_CRITICAL_EXIT();
100 return ret;
101 }
102
103
107 void WIZCHIP_WRITE_BUF(uint16_t AddrSel, uint8_t* pBuf, uint16_t len)
108 {
109 uint16_t i = 0;
110
111 WIZCHIP_CRITICAL_ENTER();
112
113 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
114 for(i = 0; i < len; i++)
115 {
116 WIZCHIP.CS._select();
117 WIZCHIP.IF.SPI._write_byte(0xF0);
118 WIZCHIP.IF.SPI._write_byte((((uint16_t)(AddrSel+i)) & 0xFF00) >> 8);
119 WIZCHIP.IF.SPI._write_byte((((uint16_t)(AddrSel+i)) & 0x00FF) >> 0);
120 WIZCHIP.IF.SPI._write_byte(pBuf[i]); // Data write (write 1byte data)
121 WIZCHIP.CS._deselect();
122 }
123 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_) )
124 for(i = 0; i < len; i++)
125 WIZCHIP.IF.BUS._write_byte(AddrSel+i,pBuf[i]);
126 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_) )
127 WIZCHIP_WRITE(MR,WIZCHIP_READ(MR) | MR_AI);
128 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0xFF00) >> 8);
129 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x00FF));
130 for(i = 0 ; i < len; i++)
131 WIZCHIP.IF.BUS._write_byte(IDM_DR,pBuf[i]);
132 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) & ~MR_AI);
133 #else
134 #error "Unknown _WIZCHIP_IO_MODE_ in W5100. !!!!"
135 #endif
136
137 WIZCHIP_CRITICAL_EXIT();
138 }
139
144 void WIZCHIP_READ_BUF (uint16_t AddrSel, uint8_t* pBuf, uint16_t len)
145 {
146 uint16_t i = 0;
147 WIZCHIP_CRITICAL_ENTER();
148
149 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
150 for(i = 0; i < len; i++)
151 {
152 WIZCHIP.CS._select();
153 WIZCHIP.IF.SPI._write_byte(0x0F);
154 WIZCHIP.IF.SPI._write_byte((uint16_t)((AddrSel+i) & 0xFF00) >> 8);
155 WIZCHIP.IF.SPI._write_byte((uint16_t)((AddrSel+i) & 0x00FF) >> 0);
156 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
157 WIZCHIP.CS._deselect();
158 }
159 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_) )
160 for(i = 0 ; i < len; i++)
161 pBuf[i] = WIZCHIP.IF.BUS._read_byte(AddrSel+i);
162 #elif ( (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_) )
163 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) | MR_AI);
164 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0xFF00) >> 8);
165 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x00FF));
166 for(i = 0 ; i < len; i++)
167 pBuf[i] = WIZCHIP.IF.BUS._read_byte(IDM_DR);
168 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) & ~MR_AI);
169 #else
170 #error "Unknown _WIZCHIP_IO_MODE_ in W5100. !!!!"
171 #endif
172
173 WIZCHIP_CRITICAL_EXIT();
174 }
175
177 // Socket N regsiter IO function //
179
180 uint16_t getSn_TX_FSR(uint8_t sn)
181 {
182 uint16_t val=0,val1=0;
183 do
184 {
185 val1 = WIZCHIP_READ(Sn_TX_FSR(sn));
186 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
187 if (val1 != 0)
188 {
189 val = WIZCHIP_READ(Sn_TX_FSR(sn));
190 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
191 }
192 }while (val != val1);
193 return val;
194 }
195
196
197 uint16_t getSn_RX_RSR(uint8_t sn)
198 {
199 uint16_t val=0,val1=0;
200 do
201 {
202 val1 = WIZCHIP_READ(Sn_RX_RSR(sn));
203 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
204 if (val1 != 0)
205 {
206 val = WIZCHIP_READ(Sn_RX_RSR(sn));
207 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
208 }
209 }while (val != val1);
210 return val;
211 }
212
214 // Sn_TXBUF & Sn_RXBUF IO function //
216 uint32_t getSn_RxBASE(uint8_t sn)
217 {
218 int8_t i;
219 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
220 uint32_t rxbase = _W5100_IO_BASE_ + _WIZCHIP_IO_RXBUF_;
221 #else
222 uint32_t rxbase = _WIZCHIP_IO_RXBUF_;
223 #endif
224 for(i = 0; i < sn; i++)
225 rxbase += getSn_RxMAX(i);
226
227 return rxbase;
228 }
229
230 uint32_t getSn_TxBASE(uint8_t sn)
231 {
232 int8_t i;
233 #if ( _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
234 uint32_t txbase = _W5100_IO_BASE_ + _WIZCHIP_IO_TXBUF_;
235 #else
236 uint32_t txbase = _WIZCHIP_IO_TXBUF_;
237 #endif
238 for(i = 0; i < sn; i++)
239 txbase += getSn_TxMAX(i);
240 return txbase;
241 }
242
254 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
255 {
256 uint16_t ptr;
257 uint16_t size;
258 uint16_t dst_mask;
259 uint16_t dst_ptr;
260
261 ptr = getSn_TX_WR(sn);
262
263 dst_mask = ptr & getSn_TxMASK(sn);
264 dst_ptr = getSn_TxBASE(sn) + dst_mask;
265
266 if (dst_mask + len > getSn_TxMAX(sn))
267 {
268 size = getSn_TxMAX(sn) - dst_mask;
269 WIZCHIP_WRITE_BUF(dst_ptr, wizdata, size);
270 wizdata += size;
271 size = len - size;
272 dst_ptr = getSn_TxBASE(sn);
273 WIZCHIP_WRITE_BUF(dst_ptr, wizdata, size);
274 }
275 else
276 {
277 WIZCHIP_WRITE_BUF(dst_ptr, wizdata, len);
278 }
279
280 ptr += len;
281
282 setSn_TX_WR(sn, ptr);
283 }
284
285
296 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
297 {
298 uint16_t ptr;
299 uint16_t size;
300 uint16_t src_mask;
301 uint16_t src_ptr;
302
303 ptr = getSn_RX_RD(sn);
304
305 src_mask = (uint32_t)ptr & getSn_RxMASK(sn);
306 src_ptr = (getSn_RxBASE(sn) + src_mask);
307
308
309 if( (src_mask + len) > getSn_RxMAX(sn) )
310 {
311 size = getSn_RxMAX(sn) - src_mask;
312 WIZCHIP_READ_BUF((uint32_t)src_ptr, (uint8_t*)wizdata, size);
313 wizdata += size;
314 size = len - size;
315 src_ptr = getSn_RxBASE(sn);
316 WIZCHIP_READ_BUF(src_ptr, (uint8_t*)wizdata, size);
317 }
318 else
319 {
320 WIZCHIP_READ_BUF(src_ptr, (uint8_t*)wizdata, len);
321 }
322
323 ptr += len;
324
325 setSn_RX_RD(sn, ptr);
326 }
327
328 void wiz_recv_ignore(uint8_t sn, uint16_t len)
329 {
330 uint16_t ptr;
331
332 ptr = getSn_RX_RD(sn);
333
334 ptr += len;
335 setSn_RX_RD(sn,ptr);
336 }
337
338
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5100/w5100.h Source File

  • Ethernet
  • W5100
w5100.h
Go to the documentation of this file.
1 //* ****************************************************************************
38 //
39 //*****************************************************************************
40
41 #ifndef _W5100_H_
42 #define _W5100_H_
43 #include <stdint.h>
44 #include "Ethernet/wizchip_conf.h"
45
46 #define _WIZCHIP_SN_BASE_ (0x0400)
47 #define _WIZCHIP_SN_SIZE_ (0x0100)
48 #define _WIZCHIP_IO_TXBUF_ (0x4000) /* Internal Tx buffer address of the iinchip */
49 #define _WIZCHIP_IO_RXBUF_ (0x6000) /* Internal Rx buffer address of the iinchip */
50
51
52 #define WIZCHIP_CREG_BLOCK 0x00
53 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
54
55 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
56
57 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
58 #define _W5100_IO_BASE_ _WIZCHIP_IO_BASE_
59 #elif (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
60 #define IDM_OR ((_WIZCHIP_IO_BASE + 0x0000))
61 #define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0001))
62 #define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0002))
63 #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003))
64 #define _W5100_IO_BASE_ 0x0000
65 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
66 #define _W5100_IO_BASE_ 0x0000
67 #endif
68
70 // Definition For Legacy Chip Driver //
72 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
73 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
74 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
75 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
76
77
78 //----------- defgroup --------------------------------
79
179 //-----------------------------------------------------------------------------------
180
181 //----------------------------- W5100 Common Registers IOMAP -----------------------------
197 #define MR (_W5100_IO_BASE_ + (0x0000)) // Mode
198
204 #define GAR (_W5100_IO_BASE_ + (0x0001)) // GW Address
205
211 #define SUBR (_W5100_IO_BASE_ + (0x0005)) // SN Mask Address
212
218 #define SHAR (_W5100_IO_BASE_ + (0x0009)) // Source Hardware Address
219
225 #define SIPR (_W5100_IO_BASE_ + (0x000F)) // Source IP Address
226
227 // Reserved (_W5100_IO_BASE_ + (0x0013))
228 // Reserved (_W5100_IO_BASE_ + (0x0014))
229
248 #define IR (_W5100_IO_BASE_ + (0x0015)) // Interrupt
249
256 #define _IMR_ (_W5100_IO_BASE_ + (0x0016)) // Socket Interrupt Mask
257
266 #define _RTR_ (_W5100_IO_BASE_ + (0x0017)) // Retry Time
267
274 #define _RCR_ (_W5100_IO_BASE_ + (0x0019)) // Retry Count
275 #define RMSR (_W5100_IO_BASE_ + (0x001A)) // Receicve Memory Size
276 #define TMSR (_W5100_IO_BASE_ + (0x001B)) // Trnasmit Memory Size
277
278
285 #define PATR (_W5100_IO_BASE_ + (0x001C))
286
287
293 #define PTIMER (_W5100_IO_BASE_ + (0x0028)) // PPP LCP RequestTimer
294
300 #define PMAGIC (_W5100_IO_BASE_ + (0x0029)) // PPP LCP Magic number
301
302 #define UIPR0 (_W5100_IO_BASE_ + (0x002A))
303 #define UPORT0 (_W5100_IO_BASE + (0x002E))
304
305
306
307 //----------------------------- W5100 Socket Registers -----------------------------
308
309 //--------------------------- For Backward Compatibility ---------------------------
310
344 #define Sn_MR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000)) // socket Mode register
345
372 #define Sn_CR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001)) // channel Sn_CR register
373
393 #define Sn_IR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002)) // channel interrupt register
394
416 #define Sn_SR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003)) // channel status register
417
424 #define Sn_PORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004)) // source port register
425
432 #define Sn_DHAR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006)) // Peer MAC register address
433
442 #define Sn_DIPR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C)) // Peer IP register address
443
452 #define Sn_DPORT(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010)) // Peer port register address
453
459 #define Sn_MSSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012)) // Maximum Segment Size(Sn_MSSR0) register address
460
467 #define Sn_PROTO(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014)) // Protocol of IP Header field register in IP raw mode
468
475 #define Sn_TOS(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + 0x0015) // IP Type of Service(TOS) Register
476
483 #define Sn_TTL(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016)) // IP Time to live(TTL) Register
484
485 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0017))
486 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0018))
487 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0019))
488 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001A))
489 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001B))
490 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001C))
491 // Reserved (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001D))
492
502 #define Sn_TX_FSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020)) // Transmit free memory size register
503
514 #define Sn_TX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022)) // Transmit memory read pointer register address
515
528 #define Sn_TX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024)) // Transmit memory write pointer register address
529
537 #define Sn_RX_RSR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026)) // Received data size register
538
550 #define Sn_RX_RD(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028)) // Read point of Receive memory
551
559 #define Sn_RX_WR(sn) (_W5100_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A)) // Write point of Receive memory
560
561
562 //----------------------------- W5100 Register values -----------------------------
563
564 /* MODE register values */
569 #define MR_RST 0x80
570
571
578 #define MR_PB 0x10
579
580
586 #define MR_PPPOE 0x08
587
588
595 #define MR_AI 0x02
596
597
603 #define MR_IND 0x01
604
605 /* IR register values */
610 #define IR_CONFLICT 0x80
611
612
617 #define IR_UNREACH 0x40
618
619
623 #define IR_PPPoE 0x20
624
625 #define IR_SOCK(sn) (0x01 << sn)
626
627
628 // Sn_MR values
629 /* Sn_MR Default values */
634 #define Sn_MR_CLOSE 0x00
635
636
640 #define Sn_MR_TCP 0x01
641
642
646 #define Sn_MR_UDP 0x02
647 #define Sn_MR_IPRAW 0x03
648
649
654 #define Sn_MR_MACRAW 0x04
655
656
661 #define Sn_MR_PPPoE 0x05
662
663
671 #define Sn_MR_ND 0x20
672
673
680 #define Sn_MR_MC Sn_MR_ND
681
682
692 #define Sn_MR_MF 0x40
693 #define Sn_MR_MFEN Sn_MR_MF
694
695
696 /* Sn_MR Default values */
705 #define Sn_MR_MULTI 0x80
706
707 /* Sn_CR values */
722 #define Sn_CR_OPEN 0x01
723
724
733 #define Sn_CR_LISTEN 0x02
734
735
745 #define Sn_CR_CONNECT 0x04
746
747
758 #define Sn_CR_DISCON 0x08
759
760
764 #define Sn_CR_CLOSE 0x10
765
772 #define Sn_CR_SEND 0x20
773
782 #define Sn_CR_SEND_MAC 0x21
783
790 #define Sn_CR_SEND_KEEP 0x22
791
798 #define Sn_CR_RECV 0x40
799
804 #define Sn_CR_PCON 0x23
805
810 #define Sn_CR_PDISCON 0x24
811
816 #define Sn_CR_PCR 0x25
817
822 #define Sn_CR_PCN 0x26
823
828 #define Sn_CR_PCJ 0x27
829
830 /* Sn_IR values */
835 #define Sn_IR_PRECV 0x80
836
841 #define Sn_IR_PFAIL 0x40
842
847 #define Sn_IR_PNEXT 0x20
848
853 #define Sn_IR_SENDOK 0x10
854
855
859 #define Sn_IR_TIMEOUT 0x08
860
861
865 #define Sn_IR_RECV 0x04
866
871 #define Sn_IR_DISCON 0x02
872
877 #define Sn_IR_CON 0x01
878
879 /* Sn_SR values */
885 #define SOCK_CLOSED 0x00
886
887
893 #define SOCK_INIT 0x13
894
895
901 #define SOCK_LISTEN 0x14
902
910 #define SOCK_SYNSENT 0x15
911
918 #define SOCK_SYNRECV 0x16
919
927 #define SOCK_ESTABLISHED 0x17
928
935 #define SOCK_FIN_WAIT 0x18
936
943 #define SOCK_CLOSING 0x1A
944
951 #define SOCK_TIME_WAIT 0x1B
952
959 #define SOCK_CLOSE_WAIT 0x1C
960
966 #define SOCK_LAST_ACK 0x1D
967
974 #define SOCK_UDP 0x22
975
976
982 #define SOCK_IPRAW 0x32
983
984
990 #define SOCK_MACRAW 0x42
991
992
999 #define SOCK_PPPOE 0x5F
1000
1001 // IP PROTOCOL
1002 #define IPPROTO_IP 0
1003 #define IPPROTO_ICMP 1
1004 #define IPPROTO_IGMP 2
1005 #define IPPROTO_GGP 3
1006 #define IPPROTO_TCP 6
1007 #define IPPROTO_PUP 12
1008 #define IPPROTO_UDP 17
1009 #define IPPROTO_IDP 22
1010 #define IPPROTO_ND 77
1011 #define IPPROTO_RAW 255
1012
1013
1024 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1025
1026 #ifdef _exit
1027 #undef _exit
1028 #endif
1029
1041 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1042
1043
1044
1046 // Basic I/O Function //
1048
1054 uint8_t WIZCHIP_READ (uint16_t AddrSel);
1055
1063 void WIZCHIP_WRITE(uint16_t AddrSel, uint8_t wb );
1064
1072 void WIZCHIP_READ_BUF (uint16_t AddrSel, uint8_t* pBuf, uint16_t len);
1073
1081 void WIZCHIP_WRITE_BUF(uint16_t AddrSel, uint8_t* pBuf, uint16_t len);
1082
1083
1085 // Common Register IO function //
1087
1094 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1095 #define setMR(mr) WIZCHIP_WRITE(MR,mr)
1096 #else
1097 #define setMR(mr) (*((uint8_t*)MR) = mr)
1098 #endif
1099
1106 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1107 #define getMR() WIZCHIP_READ(MR)
1108 #else
1109 #define getMR() (*(uint8_t*)MR)
1110 #endif
1111
1118 #define setGAR(gar) \
1119 WIZCHIP_WRITE_BUF(GAR,gar,4)
1120
1127 #define getGAR(gar) \
1128 WIZCHIP_READ_BUF(GAR,gar,4)
1129
1139 #define setSUBR(subr) \
1140 WIZCHIP_WRITE_BUF(SUBR,subr,4)
1141
1148 #define getSUBR(subr) \
1149 WIZCHIP_READ_BUF(SUBR, subr, 4)
1150
1157 #define setSHAR(shar) \
1158 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1159
1166 #define getSHAR(shar) \
1167 WIZCHIP_READ_BUF(SHAR, shar, 6)
1168
1175 #define setSIPR(sipr) \
1176 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1177
1184 #define getSIPR(sipr) \
1185 WIZCHIP_READ_BUF(SIPR, sipr, 4)
1186
1193 #define setIR(ir) \
1194 WIZCHIP_WRITE(IR, (ir & 0xA0))
1195
1201 #define getIR() \
1202 (WIZCHIP_READ(IR) & 0xA0)
1203
1210 #define setIMR(imr) \
1211 WIZCHIP_WRITE(_IMR_, imr)
1212
1219 #define getIMR() \
1220 WIZCHIP_READ(_IMR_)
1221
1228 #define setRTR(rtr) {\
1229 WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
1230 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1231 }
1232
1239 #define getRTR() \
1240 (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1241
1248 #define setRCR(rcr) \
1249 WIZCHIP_WRITE(_RCR_, rcr)
1250
1257 #define getRCR() \
1258 WIZCHIP_READ(_RCR_)
1259
1265 #define setRMSR(rmsr) \
1266 WIZCHIP_WRITE(RMSR) // Receicve Memory Size
1267
1274 #define getRMSR() \
1275 WIZCHIP_READ() // Receicve Memory Size
1276
1282 #define setTMSR(rmsr) \
1283 WIZCHIP_WRITE(TMSR) // Receicve Memory Size
1284
1298 #define getPATR() \
1299 (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
1300
1306 #define getPPPALGO() \
1307 WIZCHIP_READ(PPPALGO)
1308
1309
1316 #define setPTIMER(ptimer) \
1317 WIZCHIP_WRITE(PTIMER, ptimer)
1318
1325 #define getPTIMER() \
1326 WIZCHIP_READ(PTIMER)
1327
1334 #define setPMAGIC(pmagic) \
1335 WIZCHIP_WRITE(PMAGIC, pmagic)
1336
1343 #define getPMAGIC() \
1344 WIZCHIP_READ(PMAGIC)
1345
1347 // Socket N register I/O function //
1349
1356 #define setSn_MR(sn, mr) \
1357 WIZCHIP_WRITE(Sn_MR(sn),mr)
1358
1366 #define getSn_MR(sn) \
1367 WIZCHIP_READ(Sn_MR(sn))
1368
1376 #define setSn_CR(sn, cr) \
1377 WIZCHIP_WRITE(Sn_CR(sn), cr)
1378
1386 #define getSn_CR(sn) \
1387 WIZCHIP_READ(Sn_CR(sn))
1388
1396 #define setSn_IR(sn, ir) \
1397 WIZCHIP_WRITE(Sn_IR(sn), ir)
1398
1406 #define getSn_IR(sn) \
1407 WIZCHIP_READ(Sn_IR(sn))
1408
1415 #define getSn_SR(sn) \
1416 WIZCHIP_READ(Sn_SR(sn))
1417
1425 #define setSn_PORT(sn, port) { \
1426 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1427 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1428 }
1429
1437 #define getSn_PORT(sn) \
1438 (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1439
1447 #define setSn_DHAR(sn, dhar) \
1448 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1449
1457 #define getSn_DHAR(sn, dhar) \
1458 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1459
1467 #define setSn_DIPR(sn, dipr) \
1468 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1469
1477 #define getSn_DIPR(sn, dipr) \
1478 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1479
1487 #define setSn_DPORT(sn, dport) { \
1488 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1489 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1490 }
1491
1499 #define getSn_DPORT(sn) \
1500 (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1501
1509 #define setSn_MSSR(sn, mss) { \
1510 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1511 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1512 }
1513
1521 #define getSn_MSSR(sn) \
1522 (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1523
1531 #define setSn_PROTO(sn, proto) \
1532 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1533
1541 #define getSn_PROTO(sn) \
1542 WIZCHIP_READ(Sn_TOS(sn))
1543
1551 #define setSn_TOS(sn, tos) \
1552 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1553
1561 #define getSn_TOS(sn) \
1562 WIZCHIP_READ(Sn_TOS(sn))
1563
1571 #define setSn_TTL(sn, ttl) \
1572 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1573
1581 #define getSn_TTL(sn) \
1582 WIZCHIP_READ(Sn_TTL(sn))
1583
1591 #define setSn_RXMEM_SIZE(sn, rxmemsize) \
1592 WIZCHIP_WRITE(RMSR, (WIZCHIP_READ(RMSR) & ~(0x03 << (2*sn))) | (rxmemsize << (2*sn)))
1593 #define setSn_RXBUF_SIZE(sn,rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
1594
1602 #define getSn_RXMEM_SIZE(sn) \
1603 ((WIZCHIP_READ(RMSR) & (0x03 << (2*sn))) >> (2*sn))
1604 #define getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
1605
1613 #define setSn_TXMEM_SIZE(sn, txmemsize) \
1614 WIZCHIP_WRITE(TMSR, (WIZCHIP_READ(TMSR) & ~(0x03 << (2*sn))) | (txmemsize << (2*sn)))
1615 #define setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
1616
1624 #define getSn_TXMEM_SIZE(sn) \
1625 ((WIZCHIP_READ(TMSR) & (0x03 << (2*sn))) >> (2*sn))
1626 #define getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
1627
1634 uint16_t getSn_TX_FSR(uint8_t sn);
1635
1642 #define getSn_TX_RD(sn) \
1643 (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1644
1652 #define setSn_TX_WR(sn, txwr) { \
1653 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1654 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1655 }
1656
1664 #define getSn_TX_WR(sn) \
1665 (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1666
1673 uint16_t getSn_RX_RSR(uint8_t sn);
1674
1682 #define setSn_RX_RD(sn, rxrd) { \
1683 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1684 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1685 }
1686
1694 #define getSn_RX_RD(sn) \
1695 (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1696
1704 #define setSn_RX_WR(sn, rxwr) { \
1705 WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
1706 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
1707 }
1708
1709
1716 #define getSn_RX_WR(sn) \
1717 (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1718
1726 #define setSn_FRAG(sn, frag) { \
1727 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1728 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1729 }
1730
1738 #define getSn_FRAG(sn) \
1739 (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1740
1747 #define getSn_RxMAX(sn) \
1748 ((uint16_t)(1 << getSn_RXMEM_SIZE(sn)) << 10)
1749
1750
1757 #define getSn_TxMAX(sn) \
1758 ((uint16_t)(1 << getSn_TXMEM_SIZE(sn)) << 10)
1759
1766 #define getSn_RxMASK(sn) \
1767 (getSn_RxMAX(sn) - 1)
1768
1775 #define getSn_TxMASK(sn) \
1776 (getSn_TxMAX(sn) - 1)
1777
1784 uint32_t getSn_RxBASE(uint8_t sn);
1785
1792 uint32_t getSn_TxBASE(uint8_t sn);
1793
1795 // Sn_TXBUF & Sn_RXBUF IO function //
1797
1812 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1813
1829 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1830
1838 void wiz_recv_ignore(uint8_t sn, uint16_t len);
1839
1840 #endif //_W5100_H_
1841
1842
1843
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5200/w5200.c Source File

  • Ethernet
  • W5200
w5200.c
Go to the documentation of this file.
1 //*****************************************************************************
2 //
38 //
39 //*****************************************************************************
40
41 #include "w5200.h"
42
46 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb )
47 {
48 WIZCHIP_CRITICAL_ENTER();
49 WIZCHIP.CS._select();
50
51 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
52 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
53 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
54 WIZCHIP.IF.SPI._write_byte(_W5200_SPI_WRITE_); // Data write command and Write data length upper
55 WIZCHIP.IF.SPI._write_byte(0x01); // Write data length lower
56 WIZCHIP.IF.SPI._write_byte(wb); // Data write (write 1byte data)
57
58 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
59
60 //add indirect bus
61 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0x0000FF00) >> 8);
62 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x000000FF));
63 WIZCHIP.IF.BUS._write_byte(IDM_DR,wb);
64 #else
65 #error "Unknown _WIZCHIP_IO_MODE_ in W5200. !!!"
66 #endif
67
68 WIZCHIP.CS._deselect();
69 WIZCHIP_CRITICAL_EXIT();
70 }
74 uint8_t WIZCHIP_READ(uint32_t AddrSel)
75 {
76 uint8_t ret;
77
78 WIZCHIP_CRITICAL_ENTER();
79 WIZCHIP.CS._select();
80
81 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
82 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
83 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
84 WIZCHIP.IF.SPI._write_byte(_W5200_SPI_READ_); // Read data length upper
85 WIZCHIP.IF.SPI._write_byte(0x01); // Data length lower
86 ret = WIZCHIP.IF.SPI._read_byte();
87
88 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
89
90 //add indirect bus
91 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0x0000FF00) >> 8);
92 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x000000FF));
93 ret = WIZCHIP.IF.BUS._read_byte(IDM_DR);
94
95 #else
96 #error "Unknown _WIZCHIP_IO_MODE_ in W5200. !!!"
97 #endif
98
99 WIZCHIP.CS._deselect();
100 WIZCHIP_CRITICAL_EXIT();
101 return ret;
102 }
103
104
108 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
109 {
110 uint16_t i = 0;
111 WIZCHIP_CRITICAL_ENTER();
112 WIZCHIP.CS._select();
113
114 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
115 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
116 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
117 WIZCHIP.IF.SPI._write_byte(_W5200_SPI_WRITE_ | ((len & 0x7F00) >> 8)); // Write data op code and length upper
118 WIZCHIP.IF.SPI._write_byte((len & 0x00FF) >> 0); // length lower
119 for(i = 0; i < len; i++)
120 WIZCHIP.IF.SPI._write_byte(pBuf[i]);
121
122 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
123 WIZCHIP_WRITE(MR,WIZCHIP_READ(MR) | MR_AI);
124 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0x0000FF00) >> 8);
125 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x000000FF));
126 for(i = 0 ; i < len; i++)
127 WIZCHIP.IF.BUS._write_byte(IDM_DR,pBuf[i]);
128 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) & ~MR_AI);
129 #else
130 #error "Unknown _WIZCHIP_IO_MODE_ in W5200. !!!!"
131 #endif
132
133 WIZCHIP.CS._deselect();
134 WIZCHIP_CRITICAL_EXIT();
135 }
136
141 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
142 {
143 uint16_t i = 0;
144 WIZCHIP_CRITICAL_ENTER();
145 WIZCHIP.CS._select();
146
147 #if( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_))
148 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
149 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
150 WIZCHIP.IF.SPI._write_byte( _W5200_SPI_READ_ | ((len & 0x7F00) >> 8)); // Write data op code and length upper
151 WIZCHIP.IF.SPI._write_byte((len & 0x00FF) >> 0); // length lower
152 for(i = 0; i < len; i++)
153 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
154
155 #elif ( (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) )
156 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) | MR_AI);
157 WIZCHIP.IF.BUS._write_byte(IDM_AR0,(AddrSel & 0x0000FF00) >> 8);
158 WIZCHIP.IF.BUS._write_byte(IDM_AR1,(AddrSel & 0x000000FF));
159 for(i = 0 ; i < len; i++)
160 pBuf[i] = WIZCHIP.IF.BUS._read_byte(IDM_DR);
161 WIZCHIP_WRITE(MR, WIZCHIP_READ(MR) & ~MR_AI);
162 #else
163 #error "Unknown _WIZCHIP_IO_MODE_ in W5200. !!!!"
164 #endif
165
166 WIZCHIP.CS._deselect();
167 WIZCHIP_CRITICAL_EXIT();
168 }
169
171 // Socket N regsiter IO function //
173
174 uint16_t getSn_TX_FSR(uint8_t sn)
175 {
176 uint16_t val=0,val1=0;
177 do
178 {
179 val1 = WIZCHIP_READ(Sn_TX_FSR(sn));
180 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
181 if (val1 != 0)
182 {
183 val = WIZCHIP_READ(Sn_TX_FSR(sn));
184 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
185 }
186 }while (val != val1);
187 return val;
188 }
189
190
191 uint16_t getSn_RX_RSR(uint8_t sn)
192 {
193 uint16_t val=0,val1=0;
194 do
195 {
196 val1 = WIZCHIP_READ(Sn_RX_RSR(sn));
197 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
198 if (val1 != 0)
199 {
200 val = WIZCHIP_READ(Sn_RX_RSR(sn));
201 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
202 }
203 }while (val != val1);
204 return val;
205 }
206
208 // Sn_TXBUF & Sn_RXBUF IO function //
210
211 uint16_t getSn_RxBASE(uint8_t sn)
212 {
213 int8_t i;
214 uint16_t rxbase = _WIZCHIP_IO_RXBUF_;
215 for(i = 0; i < sn; i++)
216 rxbase += getSn_RxMAX(i);
217 return rxbase;
218 }
219
220 uint16_t getSn_TxBASE(uint8_t sn)
221 {
222 int8_t i;
223 uint16_t txbase = _WIZCHIP_IO_TXBUF_;
224 for(i = 0; i < sn; i++)
225 txbase += getSn_TxMAX(i);
226 return txbase;
227 }
228
241 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
242 {
243
244 uint16_t ptr;
245 uint16_t size;
246 uint16_t dst_mask;
247 uint8_t * dst_ptr;
248
249 ptr = getSn_TX_WR(sn);
250
251
252 dst_mask = (uint32_t)ptr & getSn_TxMASK(sn);
253 dst_ptr = (uint8_t*)((uint32_t)getSn_TxBASE(sn) + dst_mask);
254
255 if (dst_mask + len > getSn_TxMAX(sn))
256 {
257 size = getSn_TxMAX(sn) - dst_mask;
258 WIZCHIP_WRITE_BUF((uint32_t)dst_ptr, wizdata, size);
259 wizdata += size;
260 size = len - size;
261 dst_ptr = (uint8_t*)((uint32_t)getSn_TxBASE(sn));
262 WIZCHIP_WRITE_BUF((uint32_t)dst_ptr, wizdata, size);
263 }
264 else
265 {
266 WIZCHIP_WRITE_BUF((uint32_t)dst_ptr, wizdata, len);
267 }
268
269 ptr += len;
270
271 setSn_TX_WR(sn, ptr);
272 }
273
274
285 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
286 {
287 uint16_t ptr;
288 uint16_t size;
289 uint16_t src_mask;
290 uint8_t * src_ptr;
291
292 ptr = getSn_RX_RD(sn);
293
294 src_mask = (uint32_t)ptr & getSn_RxMASK(sn);
295 src_ptr = (uint8_t *)((uint32_t)getSn_RxBASE(sn) + src_mask);
296
297 if( (src_mask + len) > getSn_RxMAX(sn) )
298 {
299 size = getSn_RxMAX(sn) - src_mask;
300 WIZCHIP_READ_BUF((uint32_t)src_ptr, (uint8_t*)wizdata, size);
301 wizdata += size;
302 size = len - size;
303 src_ptr = (uint8_t*)((uint32_t)getSn_RxBASE(sn));
304 WIZCHIP_READ_BUF((uint32_t)src_ptr, (uint8_t*)wizdata, size);
305 }
306 else
307 {
308 WIZCHIP_READ_BUF((uint32_t)src_ptr, (uint8_t*)wizdata, len);
309 }
310
311 ptr += len;
312
313 setSn_RX_RD(sn, ptr);
314 }
315
316 void wiz_recv_ignore(uint8_t sn, uint16_t len)
317 {
318 uint16_t ptr;
319
320 ptr = getSn_RX_RD(sn);
321
322 ptr += len;
323 setSn_RX_RD(sn,ptr);
324 }
325
326
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5200/w5200.h Source File

  • Ethernet
  • W5200
w5200.h
Go to the documentation of this file.
1 //* ****************************************************************************
38 //
39 //*****************************************************************************
40
41 #ifndef _W5200_H
42 #define _W5200_H
43 #include <stdint.h>
44 #include "Ethernet/wizchip_conf.h"
45
46 #define _WIZCHIP_SN_BASE_ (0x4000)
47 #define _WIZCHIP_SN_SIZE_ (0x0100)
48 #define _WIZCHIP_IO_TXBUF_ (0x8000) /* Internal Tx buffer address of the iinchip */
49 #define _WIZCHIP_IO_RXBUF_ (0xC000) /* Internal Rx buffer address of the iinchip */
50
51 #define _W5200_SPI_READ_ (0x00 << 7)
52 #define _W5200_SPI_WRITE_ (0x01 << 7)
53
54 #define WIZCHIP_CREG_BLOCK 0x00
55 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
56
57 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
58
59 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
60 #define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0001))
61 #define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0002))
62 #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003))
63 #define _W5200_IO_BASE_ 0x0000
64 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
65 #define _W5200_IO_BASE_ 0x0000
66 #endif
67
69 // Definition For Legacy Chip Driver //
71 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
72 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
73 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
74 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
75
76
77 //----------- defgroup --------------------------------
78
181 //-----------------------------------------------------------------------------------
182
183 //----------------------------- W5200 Common Registers IOMAP -----------------------------
200 #define MR (_W5200_IO_BASE_ + (0x0000)) // Mode
201
207 #define GAR (_W5200_IO_BASE_ + (0x0001)) // GW Address
208
214 #define SUBR (_W5200_IO_BASE_ + (0x0005)) // SN Mask Address
215
221 #define SHAR (_W5200_IO_BASE_ + (0x0009)) // Source Hardware Address
222
228 #define SIPR (_W5200_IO_BASE_ + (0x000F)) // Source IP Address
229
230 // Reserved (_W5200_IO_BASE_ + (0x0013))
231 // Reserved (_W5200_IO_BASE_ + (0x0014))
232
246 #define IR (_W5200_IO_BASE_ + (0x0015)) // Interrupt
247
255 #define _IMR_ (_W5200_IO_BASE_ + (0x0016)) // Socket Interrupt Mask
256
265 #define _RTR_ (_W5200_IO_BASE_ + (0x0017)) // Retry Time
266
273 #define _RCR_ (_W5200_IO_BASE_ + (0x0019)) // Retry Count
274
275 // Reserved (_W5200_IO_BASE_ + (0x001A))
276 // Reserved (_W5200_IO_BASE_ + (0x001B))
277
284 #define PATR (_W5200_IO_BASE_ + (0x001C))
285
292 #define PPPALGO (_W5200_IO_BASE_ + (0x001E)) // Authentication Algorithm in PPPoE
293
299 #define VERSIONR (_W5200_IO_BASE_ + (0x001F)) // Chip version
300
301 // Reserved (_W5200_IO_BASE_ + (0x0020))
302 // Reserved (_W5200_IO_BASE_ + (0x0021))
303 // Reserved (_W5200_IO_BASE_ + (0x0022))
304 // Reserved (_W5200_IO_BASE_ + (0x0023))
305 // Reserved (_W5200_IO_BASE_ + (0x0024))
306 // Reserved (_W5200_IO_BASE_ + (0x0025))
307 // Reserved (_W5200_IO_BASE_ + (0x0026))
308 // Reserved (_W5200_IO_BASE_ + (0x0027))
309
315 #define PTIMER (_W5200_IO_BASE_ + (0x0028)) // PPP LCP RequestTimer
316
322 #define PMAGIC (_W5200_IO_BASE_ + (0x0029)) // PPP LCP Magic number
323
324 // Reserved (_W5200_IO_BASE_ + (0x002A))
325 // Reserved (_W5200_IO_BASE_ + (0x002B))
326 // Reserved (_W5200_IO_BASE_ + (0x002C))
327 // Reserved (_W5200_IO_BASE_ + (0x002D))
328 // Reserved (_W5200_IO_BASE_ + (0x002E))
329 // Reserved (_W5200_IO_BASE_ + (0x002F))
330
336 #define INTLEVEL (_W5200_IO_BASE_ + (0x0030)) // Interrupt Low Level Timer
337
338 // Reserved (_W5200_IO_BASE_ + (0x0032))
339 // Reserved (_W5200_IO_BASE_ + (0x0033))
340
347 #define IR2 (_W5200_IO_BASE_ + (0x0034)) // Socket Interrupt
348
361 #define PHYSTATUS (_W5200_IO_BASE_ + (0x0035)) // PHY Status
362
377 #define IMR2 (_W5200_IO_BASE_ + (0x0036)) // Interrupt Mask
378
379
380 //----------------------------- W5200 Socket Registers -----------------------------
381
382 //--------------------------- For Backward Compatibility ---------------------------
383
417 #define Sn_MR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000)) // socket Mode register
418
445 #define Sn_CR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001)) // channel Sn_CR register
446
466 #define Sn_IR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002)) // channel interrupt register
467
489 #define Sn_SR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003)) // channel status register
490
497 #define Sn_PORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004)) // source port register
498
505 #define Sn_DHAR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006)) // Peer MAC register address
506
515 #define Sn_DIPR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C)) // Peer IP register address
516
525 #define Sn_DPORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010)) // Peer port register address
526
532 #define Sn_MSSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012)) // Maximum Segment Size(Sn_MSSR0) register address
533
540 #define Sn_PROTO(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014)) // Protocol of IP Header field register in IP raw mode
541
548 #define Sn_TOS(sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015) // IP Type of Service(TOS) Register
549
556 #define Sn_TTL(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016)) // IP Time to live(TTL) Register
557
558 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0017))
559 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0018))
560 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0019))
561 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001A))
562 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001B))
563 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001C))
564 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001D))
565
576 #define Sn_RXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E)) // Receive memory size reigster
577
587 #define Sn_TXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F)) // Transmit memory size reigster
588
598 #define Sn_TX_FSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020)) // Transmit free memory size register
599
610 #define Sn_TX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022)) // Transmit memory read pointer register address
611
624 #define Sn_TX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024)) // Transmit memory write pointer register address
625
633 #define Sn_RX_RSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026)) // Received data size register
634
646 #define Sn_RX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028)) // Read point of Receive memory
647
655 #define Sn_RX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A)) // Write point of Receive memory
656
665 #define Sn_IMR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C)) // socket interrupt mask register
666
672 #define Sn_FRAG(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D)) // frag field value in IP header register
673
674
675 //----------------------------- W5200 Register values -----------------------------
676
677 /* MODE register values */
682 #define MR_RST 0x80
683
684
693 #define MR_WOL 0x20
694
695
701 #define MR_PB 0x10
702
703
709 #define MR_PPPOE 0x08
710
711
718 #define MR_AI 0x02
719
720
726 #define MR_IND 0x01
727
728 /* IR register values */
733 #define IR_CONFLICT 0x80
734
735
739 #define IR_PPPoE 0x20
740
741
745 #define PHYSTATUS_LINK 0x20
746
751 #define PHYSTATUS_POWERSAVE 0x10
752
757 #define PHYSTATUS_POWERDOWN 0x08
758
759 // Sn_MR values
760 /* Sn_MR Default values */
765 #define Sn_MR_CLOSE 0x00
766
767
771 #define Sn_MR_TCP 0x01
772
773
777 #define Sn_MR_UDP 0x02
778 #define Sn_MR_IPRAW 0x03
779
780
785 #define Sn_MR_MACRAW 0x04
786
787
792 #define Sn_MR_PPPOE 0x05
793
794
802 #define Sn_MR_ND 0x20
803
804 /* Sn_MR Default values */
813 #define Sn_MR_MC Sn_MR_ND
814
815
822 #define Sn_MR_MF 0x40
823 #define Sn_MR_MFEN Sn_MR_MF
824
825 /* Sn_MR Default values */
834 #define Sn_MR_MULTI 0x80
835
836 /* Sn_CR values */
851 #define Sn_CR_OPEN 0x01
852
853
862 #define Sn_CR_LISTEN 0x02
863
864
874 #define Sn_CR_CONNECT 0x04
875
876
887 #define Sn_CR_DISCON 0x08
888
889
893 #define Sn_CR_CLOSE 0x10
894
901 #define Sn_CR_SEND 0x20
902
911 #define Sn_CR_SEND_MAC 0x21
912
919 #define Sn_CR_SEND_KEEP 0x22
920
927 #define Sn_CR_RECV 0x40
928
933 #define Sn_CR_PCON 0x23
934
939 #define Sn_CR_PDISCON 0x24
940
945 #define Sn_CR_PCR 0x25
946
951 #define Sn_CR_PCN 0x26
952
957 #define Sn_CR_PCJ 0x27
958
959 /* Sn_IR values */
964 #define Sn_IR_PRECV 0x80
965
970 #define Sn_IR_PFAIL 0x40
971
976 #define Sn_IR_PNEXT 0x20
977
982 #define Sn_IR_SENDOK 0x10
983
984
988 #define Sn_IR_TIMEOUT 0x08
989
990
994 #define Sn_IR_RECV 0x04
995
1000 #define Sn_IR_DISCON 0x02
1001
1006 #define Sn_IR_CON 0x01
1007
1008 /* Sn_SR values */
1014 #define SOCK_CLOSED 0x00
1015
1016
1022 #define SOCK_INIT 0x13
1023
1024
1030 #define SOCK_LISTEN 0x14
1031
1039 #define SOCK_SYNSENT 0x15
1040
1047 #define SOCK_SYNRECV 0x16
1048
1056 #define SOCK_ESTABLISHED 0x17
1057
1064 #define SOCK_FIN_WAIT 0x18
1065
1072 #define SOCK_CLOSING 0x1A
1073
1080 #define SOCK_TIME_WAIT 0x1B
1081
1088 #define SOCK_CLOSE_WAIT 0x1C
1089
1095 #define SOCK_LAST_ACK 0x1D
1096
1103 #define SOCK_UDP 0x22
1104
1105
1111 #define SOCK_IPRAW 0x32
1112
1113
1119 #define SOCK_MACRAW 0x42
1120
1121
1128 #define SOCK_PPPOE 0x5F
1129
1130 // IP PROTOCOL
1131 #define IPPROTO_IP 0
1132 #define IPPROTO_ICMP 1
1133 #define IPPROTO_IGMP 2
1134 #define IPPROTO_GGP 3
1135 #define IPPROTO_TCP 6
1136 #define IPPROTO_PUP 12
1137 #define IPPROTO_UDP 17
1138 #define IPPROTO_IDP 22
1139 #define IPPROTO_ND 77
1140 #define IPPROTO_RAW 255
1141
1142
1153 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1154
1155 #ifdef _exit
1156 #undef _exit
1157 #endif
1158
1170 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1171
1172
1173
1175 // Basic I/O Function //
1177
1183 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1184
1192 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1193
1201 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1202
1210 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1211
1212
1214 // Common Register IO function //
1216
1223 #define setMR(mr) \
1224 WIZCHIP_WRITE(MR,mr)
1225
1232 #define getMR() \
1233 WIZCHIP_READ(MR)
1234
1241 #define setGAR(gar) \
1242 WIZCHIP_WRITE_BUF(GAR,gar,4)
1243
1250 #define getGAR(gar) \
1251 WIZCHIP_READ_BUF(GAR,gar,4)
1252
1262 #define setSUBR(subr) \
1263 WIZCHIP_WRITE_BUF(SUBR, subr,4)
1264
1271 #define getSUBR(subr) \
1272 WIZCHIP_READ_BUF(SUBR, subr, 4)
1273
1280 #define setSHAR(shar) \
1281 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1282
1289 #define getSHAR(shar) \
1290 WIZCHIP_READ_BUF(SHAR, shar, 6)
1291
1298 #define setSIPR(sipr) \
1299 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1300
1307 #define getSIPR(sipr) \
1308 WIZCHIP_READ_BUF(SIPR, sipr, 4)
1309
1316 #define setIR(ir) \
1317 WIZCHIP_WRITE(IR, (ir & 0xA0))
1318
1324 #define getIR() \
1325 (WIZCHIP_READ(IR) & 0xA0)
1326
1333 #define setIMR(imr) \
1334 WIZCHIP_WRITE(_IMR_, imr)
1335
1342 #define getIMR() \
1343 WIZCHIP_READ(_IMR_)
1344
1351 #define setRTR(rtr) {\
1352 WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
1353 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1354 }
1355
1362 #define getRTR() \
1363 (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1364
1371 #define setRCR(rcr) \
1372 WIZCHIP_WRITE(_RCR_, rcr)
1373
1380 #define getRCR() \
1381 WIZCHIP_READ(_RCR_)
1382
1388 #define getPATR() \
1389 (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
1390
1396 #define getPPPALGO() \
1397 WIZCHIP_READ(PPPALGO)
1398
1399
1405 #define getVERSIONR() \
1406 WIZCHIP_READ(VERSIONR)
1407
1414 #define setPTIMER(ptimer) \
1415 WIZCHIP_WRITE(PTIMER, ptimer)
1416
1423 #define getPTIMER() \
1424 WIZCHIP_READ(PTIMER)
1425
1432 #define setPMAGIC(pmagic) \
1433 WIZCHIP_WRITE(PMAGIC, pmagic)
1434
1441 #define getPMAGIC() \
1442 WIZCHIP_READ(PMAGIC)
1443
1450 #define setINTLEVEL(intlevel) {\
1451 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1452 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1453 }
1454
1460 #define getINTLEVEL() \
1461 (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1462
1469 #define setIR2(ir2) \
1470 WIZCHIP_WRITE(IR2, ir2)
1471 #define setSIR(ir2) setIR2(ir2)
1472
1479 #define getIR2() \
1480 WIZCHIP_READ(IR2)
1481 #define getSIR() getIR2()
1482
1488 #define getPHYSTATUS() \
1489 WIZCHIP_READ(PHYSTATUS)
1490
1497 #define setIMR2(imr2) \
1498 WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))
1499 #define setSIMR(imr2) setIMR2(imr2)
1500
1507 #define getIMR2() \
1508 (WIZCHIP_READ(IMR2) & 0xA0)
1509 #define getSIMR() getIMR2()
1510 // Socket N register I/O function //
1513
1520 #define setSn_MR(sn, mr) \
1521 WIZCHIP_WRITE(Sn_MR(sn),mr)
1522
1530 #define getSn_MR(sn) \
1531 WIZCHIP_READ(Sn_MR(sn))
1532
1540 #define setSn_CR(sn, cr) \
1541 WIZCHIP_WRITE(Sn_CR(sn), cr)
1542
1550 #define getSn_CR(sn) \
1551 WIZCHIP_READ(Sn_CR(sn))
1552
1560 #define setSn_IR(sn, ir) \
1561 WIZCHIP_WRITE(Sn_IR(sn), ir)
1562
1570 #define getSn_IR(sn) \
1571 WIZCHIP_READ(Sn_IR(sn))
1572
1580 #define setSn_IMR(sn, imr) \
1581 WIZCHIP_WRITE(Sn_IMR(sn), imr)
1582
1590 #define getSn_IMR(sn) \
1591 WIZCHIP_READ(Sn_IMR(sn))
1592
1599 #define getSn_SR(sn) \
1600 WIZCHIP_READ(Sn_SR(sn))
1601
1609 #define setSn_PORT(sn, port) { \
1610 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1611 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1612 }
1613
1621 #define getSn_PORT(sn) \
1622 (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1623
1631 #define setSn_DHAR(sn, dhar) \
1632 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1633
1641 #define getSn_DHAR(sn, dhar) \
1642 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1643
1651 #define setSn_DIPR(sn, dipr) \
1652 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1653
1661 #define getSn_DIPR(sn, dipr) \
1662 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1663
1671 #define setSn_DPORT(sn, dport) { \
1672 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1673 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1674 }
1675
1683 #define getSn_DPORT(sn) \
1684 (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1685
1693 #define setSn_MSSR(sn, mss) { \
1694 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1695 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1696 }
1697
1705 #define getSn_MSSR(sn) \
1706 (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1707
1715 #define setSn_PROTO(sn, proto) \
1716 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1717
1725 #define getSn_PROTO(sn) \
1726 WIZCHIP_READ(Sn_TOS(sn))
1727
1735 #define setSn_TOS(sn, tos) \
1736 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1737
1745 #define getSn_TOS(sn) \
1746 WIZCHIP_READ(Sn_TOS(sn))
1747
1755 #define setSn_TTL(sn, ttl) \
1756 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1757
1765 #define getSn_TTL(sn) \
1766 WIZCHIP_READ(Sn_TTL(sn))
1767
1775 #define setSn_RXMEM_SIZE(sn, rxmemsize) \
1776 WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)
1777
1778 #define setSn_RXBUF_SIZE(sn,rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
1779
1787 #define getSn_RXMEM_SIZE(sn) \
1788 WIZCHIP_READ(Sn_RXMEM_SIZE(sn))
1789
1790 #define getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
1791
1799 #define setSn_TXMEM_SIZE(sn, txmemsize) \
1800 WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)
1801
1802 #define setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
1803
1811 #define getSn_TXMEM_SIZE(sn) \
1812 WIZCHIP_READ(Sn_TXMEM_SIZE(sn))
1813
1814 #define getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
1815
1822 uint16_t getSn_TX_FSR(uint8_t sn);
1823
1830 #define getSn_TX_RD(sn) \
1831 (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1832
1840 #define setSn_TX_WR(sn, txwr) { \
1841 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1842 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1843 }
1844
1852 #define getSn_TX_WR(sn) \
1853 (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1854
1861 uint16_t getSn_RX_RSR(uint8_t sn);
1862
1870 #define setSn_RX_RD(sn, rxrd) { \
1871 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1872 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1873 }
1874
1882 #define getSn_RX_RD(sn) \
1883 (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1884
1892 #define setSn_RX_WR(sn, rxwr) { \
1893 WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
1894 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
1895 }
1896
1897
1904 #define getSn_RX_WR(sn) \
1905 (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1906
1914 #define setSn_IMR(sn ,imr) \
1915 WIZCHIP_WRITE(Sn_IMR(sn), imr)
1916
1924 #define getSn_IMR(sn) \
1925 WIZCHIP_READ(Sn_IMR(sn))
1926
1934 #define setSn_FRAG(sn, frag) { \
1935 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1936 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1937 }
1938
1946 #define getSn_FRAG(sn) \
1947 (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1948
1955 #define getSn_RxMAX(sn) \
1956 ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)
1957
1964 #define getSn_TxMAX(sn) \
1965 ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)
1966
1973 #define getSn_RxMASK(sn) \
1974 ((uint16_t)getSn_RxMAX(sn) - 1)
1975
1982 #define getSn_TxMASK(sn) \
1983 ((uint16_t)getSn_TxMAX(sn) - 1)
1984
1991 uint16_t getSn_RxBASE(uint8_t sn);
1992
1999 uint16_t getSn_TxBASE(uint8_t sn);
2000
2002 // Sn_TXBUF & Sn_RXBUF IO function //
2004
2019 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2020
2036 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2037
2045 void wiz_recv_ignore(uint8_t sn, uint16_t len);
2046
2047 #endif //_W5200_H_
2048
2049
2050
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5500/w5500.c Source File

  • Ethernet
  • W5500
w5500.c
Go to the documentation of this file.
1 //*****************************************************************************
2 //
52 //
53 //*****************************************************************************
54 //#include <stdio.h>
55 #include "w5500.h"
56
57 #define _W5500_SPI_VDM_OP_ 0x00
58 #define _W5500_SPI_FDM_OP_LEN1_ 0x01
59 #define _W5500_SPI_FDM_OP_LEN2_ 0x02
60 #define _W5500_SPI_FDM_OP_LEN4_ 0x03
61
63
64 uint8_t WIZCHIP_READ(uint32_t AddrSel)
65 {
66 uint8_t ret;
67 uint8_t spi_data[3];
68
69 WIZCHIP_CRITICAL_ENTER();
70 WIZCHIP.CS._select();
71
72 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
73
74 if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
75 {
76 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
77 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
78 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
79 }
80 else // burst operation
81 {
82 spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
83 spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
84 spi_data[2] = (AddrSel & 0x000000FF) >> 0;
85 WIZCHIP.IF.SPI._write_burst(spi_data, 3);
86 }
87 ret = WIZCHIP.IF.SPI._read_byte();
88
89 WIZCHIP.CS._deselect();
90 WIZCHIP_CRITICAL_EXIT();
91 return ret;
92 }
93
94 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb )
95 {
96 uint8_t spi_data[4];
97
98 WIZCHIP_CRITICAL_ENTER();
99 WIZCHIP.CS._select();
100
101 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
102
103 //if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
104 if(!WIZCHIP.IF.SPI._write_burst) // byte operation
105 {
106 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
107 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
108 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
109 WIZCHIP.IF.SPI._write_byte(wb);
110 }
111 else // burst operation
112 {
113 spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
114 spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
115 spi_data[2] = (AddrSel & 0x000000FF) >> 0;
116 spi_data[3] = wb;
117 WIZCHIP.IF.SPI._write_burst(spi_data, 4);
118 }
119
120 WIZCHIP.CS._deselect();
121 WIZCHIP_CRITICAL_EXIT();
122 }
123
124 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
125 {
126 uint8_t spi_data[3];
127 uint16_t i;
128
129 WIZCHIP_CRITICAL_ENTER();
130 WIZCHIP.CS._select();
131
132 AddrSel |= (_W5500_SPI_READ_ | _W5500_SPI_VDM_OP_);
133
134 if(!WIZCHIP.IF.SPI._read_burst || !WIZCHIP.IF.SPI._write_burst) // byte operation
135 {
136 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
137 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
138 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
139 for(i = 0; i < len; i++)
140 pBuf[i] = WIZCHIP.IF.SPI._read_byte();
141 }
142 else // burst operation
143 {
144 spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
145 spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
146 spi_data[2] = (AddrSel & 0x000000FF) >> 0;
147 WIZCHIP.IF.SPI._write_burst(spi_data, 3);
148 WIZCHIP.IF.SPI._read_burst(pBuf, len);
149 }
150
151 WIZCHIP.CS._deselect();
152 WIZCHIP_CRITICAL_EXIT();
153 }
154
155 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len)
156 {
157 uint8_t spi_data[3];
158 uint16_t i;
159
160 WIZCHIP_CRITICAL_ENTER();
161 WIZCHIP.CS._select();
162
163 AddrSel |= (_W5500_SPI_WRITE_ | _W5500_SPI_VDM_OP_);
164
165 if(!WIZCHIP.IF.SPI._write_burst) // byte operation
166 {
167 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x00FF0000) >> 16);
168 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x0000FF00) >> 8);
169 WIZCHIP.IF.SPI._write_byte((AddrSel & 0x000000FF) >> 0);
170 for(i = 0; i < len; i++)
171 WIZCHIP.IF.SPI._write_byte(pBuf[i]);
172 }
173 else // burst operation
174 {
175 spi_data[0] = (AddrSel & 0x00FF0000) >> 16;
176 spi_data[1] = (AddrSel & 0x0000FF00) >> 8;
177 spi_data[2] = (AddrSel & 0x000000FF) >> 0;
178 WIZCHIP.IF.SPI._write_burst(spi_data, 3);
179 WIZCHIP.IF.SPI._write_burst(pBuf, len);
180 }
181
182 WIZCHIP.CS._deselect();
183 WIZCHIP_CRITICAL_EXIT();
184 }
185
186
187 uint16_t getSn_TX_FSR(uint8_t sn)
188 {
189 uint16_t val=0,val1=0;
190
191 do
192 {
193 val1 = WIZCHIP_READ(Sn_TX_FSR(sn));
194 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
195 if (val1 != 0)
196 {
197 val = WIZCHIP_READ(Sn_TX_FSR(sn));
198 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_FSR(sn),1));
199 }
200 }while (val != val1);
201 return val;
202 }
203
204
205 uint16_t getSn_RX_RSR(uint8_t sn)
206 {
207 uint16_t val=0,val1=0;
208
209 do
210 {
211 val1 = WIZCHIP_READ(Sn_RX_RSR(sn));
212 val1 = (val1 << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
213 if (val1 != 0)
214 {
215 val = WIZCHIP_READ(Sn_RX_RSR(sn));
216 val = (val << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RSR(sn),1));
217 }
218 }while (val != val1);
219 return val;
220 }
221
222 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
223 {
224 uint16_t ptr = 0;
225 uint32_t addrsel = 0;
226
227 if(len == 0) return;
228 ptr = getSn_TX_WR(sn);
229 //M20140501 : implict type casting -> explict type casting
230 //addrsel = (ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
231 addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_TXBUF_BLOCK(sn) << 3);
232 //
233 WIZCHIP_WRITE_BUF(addrsel,wizdata, len);
234
235 ptr += len;
236 setSn_TX_WR(sn,ptr);
237 }
238
239 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
240 {
241 uint16_t ptr = 0;
242 uint32_t addrsel = 0;
243
244 if(len == 0) return;
245 ptr = getSn_RX_RD(sn);
246 //M20140501 : implict type casting -> explict type casting
247 //addrsel = ((ptr << 8) + (WIZCHIP_RXBUF_BLOCK(sn) << 3);
248 addrsel = ((uint32_t)ptr << 8) + (WIZCHIP_RXBUF_BLOCK(sn) << 3);
249 //
250 WIZCHIP_READ_BUF(addrsel, wizdata, len);
251 ptr += len;
252
253 setSn_RX_RD(sn,ptr);
254 }
255
256
257 void wiz_recv_ignore(uint8_t sn, uint16_t len)
258 {
259 uint16_t ptr = 0;
260
261 ptr = getSn_RX_RD(sn);
262 ptr += len;
263 setSn_RX_RD(sn,ptr);
264 }
265
Generated on Thu Apr 9 2015 14:44:00 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/W5500/w5500.h Source File

  • Ethernet
  • W5500
w5500.h
Go to the documentation of this file.
1 //*****************************************************************************
2 //
43 //
44 //*****************************************************************************
45
46 //
47
48 #ifndef _W5500_H_
49 #define _W5500_H_
50
51 #include <stdint.h>
52 #include "wizchip_conf.h"
53
54 #define _W5500_IO_BASE_ 0x00000000
55
56 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
57 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
58
59 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
60 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
61 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
62 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
63
64 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
65
66
68 // Definition For Legacy Chip Driver //
70 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
71 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
72 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
73 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
74
75 //-------------------------- defgroup ---------------------------------
193 //------------------------------- defgroup end --------------------------------------------
194 //----------------------------- W5500 Common Registers IOMAP -----------------------------
210 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
211
217 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
218
224 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
225
231 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
232
238 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
239
245 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
246
262 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
263
280 //M20150401 : Rename SYMBOE ( Re-define error in a compile)
281 //#define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
282 #define _IMR_ (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
283
290 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
291
299 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
300
309 //M20150401 : Rename SYMBOE ( Re-define error in a compile)
310 //#define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
311 #define _RTR_ (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
312
319 //M20150401 : Rename SYMBOE ( Re-define error in a compile)
320 //#define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
321 #define _RCR_ (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
322
328 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
329
335 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
336
342 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
343
349 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
350
356 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
357
365 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
366
374 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
375
381 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
382
383 // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
384 // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
385 // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
386 // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
387 // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
388 // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
389 // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
390 // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
391 // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
392 // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
393
399 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
400
401
402 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
433 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
434
452 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
453
470 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
471
493 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
494
501 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
502
509 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
510
519 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
520
529 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
530
536 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
537
538 // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
539
546 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
547
553 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
554 // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
555 // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
556 // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
557 // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
558 // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
559 // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
560 // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
561
572 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
573
583 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
584
594 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
595
606 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
607
620 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
621
629 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
630
642 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
643
651 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
652
661 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
662
668 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
669
681 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
682
683 //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
684
685
686 //----------------------------- W5500 Register values -----------------------------
687
688 /* MODE register values */
693 #define MR_RST 0x80
694
704 #define MR_WOL 0x20
705
712 #define MR_PB 0x10
713
720 #define MR_PPPOE 0x08
721
728 #define MR_FARP 0x02
729
730 /* IR register values */
735 #define IR_CONFLICT 0x80
736
742 #define IR_UNREACH 0x40
743
748 #define IR_PPPoE 0x20
749
754 #define IR_MP 0x10
755
756
757 /* PHYCFGR register value */
758 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
759 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
760 #define PHYCFGR_OPMDC_ALLA (7<<3)
761 #define PHYCFGR_OPMDC_PDOWN (6<<3)
762 #define PHYCFGR_OPMDC_NA (5<<3)
763 #define PHYCFGR_OPMDC_100FA (4<<3)
764 #define PHYCFGR_OPMDC_100F (3<<3)
765 #define PHYCFGR_OPMDC_100H (2<<3)
766 #define PHYCFGR_OPMDC_10F (1<<3)
767 #define PHYCFGR_OPMDC_10H (0<<3)
768 #define PHYCFGR_DPX_FULL (1<<2)
769 #define PHYCFGR_DPX_HALF (0<<2)
770 #define PHYCFGR_SPD_100 (1<<1)
771 #define PHYCFGR_SPD_10 (0<<1)
772 #define PHYCFGR_LNK_ON (1<<0)
773 #define PHYCFGR_LNK_OFF (0<<0)
774
775 /* IMR register values */
781 #define IM_IR7 0x80
782
788 #define IM_IR6 0x40
789
795 #define IM_IR5 0x20
796
802 #define IM_IR4 0x10
803
804 /* Sn_MR Default values */
813 #define Sn_MR_MULTI 0x80
814
822 #define Sn_MR_BCASTB 0x40
823
832 #define Sn_MR_ND 0x20
833
840 #define Sn_MR_UCASTB 0x10
841
847 #define Sn_MR_MACRAW 0x04
848
849 //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
850
855 #define Sn_MR_UDP 0x02
856
861 #define Sn_MR_TCP 0x01
862
867 #define Sn_MR_CLOSE 0x00
868
869 /* Sn_MR values used with Sn_MR_MACRAW */
880 #define Sn_MR_MFEN Sn_MR_MULTI
881
889 #define Sn_MR_MMB Sn_MR_ND
890
897 #define Sn_MR_MIP6B Sn_MR_UCASTB
898
899 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
906 #define Sn_MR_MC Sn_MR_ND
907
908 /* Sn_MR alternate values */
912 #define SOCK_STREAM Sn_MR_TCP
913
917 #define SOCK_DGRAM Sn_MR_UDP
918
919
920 /* Sn_CR values */
933 #define Sn_CR_OPEN 0x01
934
944 #define Sn_CR_LISTEN 0x02
945
956 #define Sn_CR_CONNECT 0x04
957
969 #define Sn_CR_DISCON 0x08
970
975 #define Sn_CR_CLOSE 0x10
976
983 #define Sn_CR_SEND 0x20
984
993 #define Sn_CR_SEND_MAC 0x21
994
1001 #define Sn_CR_SEND_KEEP 0x22
1002
1009 #define Sn_CR_RECV 0x40
1010
1011 /* Sn_IR values */
1016 #define Sn_IR_SENDOK 0x10
1017
1022 #define Sn_IR_TIMEOUT 0x08
1023
1028 #define Sn_IR_RECV 0x04
1029
1034 #define Sn_IR_DISCON 0x02
1035
1040 #define Sn_IR_CON 0x01
1041
1042 /* Sn_SR values */
1048 #define SOCK_CLOSED 0x00
1049
1056 #define SOCK_INIT 0x13
1057
1064 #define SOCK_LISTEN 0x14
1065
1073 #define SOCK_SYNSENT 0x15
1074
1081 #define SOCK_SYNRECV 0x16
1082
1090 #define SOCK_ESTABLISHED 0x17
1091
1098 #define SOCK_FIN_WAIT 0x18
1099
1106 #define SOCK_CLOSING 0x1A
1107
1114 #define SOCK_TIME_WAIT 0x1B
1115
1122 #define SOCK_CLOSE_WAIT 0x1C
1123
1129 #define SOCK_LAST_ACK 0x1D
1130
1137 #define SOCK_UDP 0x22
1138
1139 //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */
1140
1147 #define SOCK_MACRAW 0x42
1148
1149 //#define SOCK_PPPOE 0x5F
1150
1151 /* IP PROTOCOL */
1152 #define IPPROTO_IP 0 //< Dummy for IP
1153 #define IPPROTO_ICMP 1 //< Control message protocol
1154 #define IPPROTO_IGMP 2 //< Internet group management protocol
1155 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1156 #define IPPROTO_TCP 6 //< TCP
1157 #define IPPROTO_PUP 12 //< PUP
1158 #define IPPROTO_UDP 17 //< UDP
1159 #define IPPROTO_IDP 22 //< XNS idp
1160 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1161 #define IPPROTO_RAW 255 //< Raw IP packet
1162
1163
1175 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1176
1177 #ifdef _exit
1178 #undef _exit
1179 #endif
1180
1192 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1193
1194
1196 // Basic I/O Function //
1198
1205 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1206
1214 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1215
1223 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1224
1232 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1233
1235 // Common Register I/O function //
1237
1243 #define setMR(mr) \
1244 WIZCHIP_WRITE(MR,mr)
1245
1246
1253 #define getMR() \
1254 WIZCHIP_READ(MR)
1255
1262 #define setGAR(gar) \
1263 WIZCHIP_WRITE_BUF(GAR,gar,4)
1264
1271 #define getGAR(gar) \
1272 WIZCHIP_READ_BUF(GAR,gar,4)
1273
1280 #define setSUBR(subr) \
1281 WIZCHIP_WRITE_BUF(SUBR, subr,4)
1282
1283
1290 #define getSUBR(subr) \
1291 WIZCHIP_READ_BUF(SUBR, subr, 4)
1292
1299 #define setSHAR(shar) \
1300 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1301
1308 #define getSHAR(shar) \
1309 WIZCHIP_READ_BUF(SHAR, shar, 6)
1310
1317 #define setSIPR(sipr) \
1318 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1319
1326 #define getSIPR(sipr) \
1327 WIZCHIP_READ_BUF(SIPR, sipr, 4)
1328
1335 #define setINTLEVEL(intlevel) {\
1336 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1337 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1338 }
1339
1340
1347 //M20150401 : Type explict declaration
1348 /*
1349 #define getINTLEVEL() \
1350 ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1351 */
1352 #define getINTLEVEL() \
1353 (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1354
1361 #define setIR(ir) \
1362 WIZCHIP_WRITE(IR, (ir & 0xF0))
1363
1370 #define getIR() \
1371 (WIZCHIP_READ(IR) & 0xF0)
1372
1378 #define setIMR(imr) \
1379 WIZCHIP_WRITE(_IMR_, imr)
1380
1387 #define getIMR() \
1388 WIZCHIP_READ(_IMR_)
1389
1396 #define setSIR(sir) \
1397 WIZCHIP_WRITE(SIR, sir)
1398
1405 #define getSIR() \
1406 WIZCHIP_READ(SIR)
1407
1413 #define setSIMR(simr) \
1414 WIZCHIP_WRITE(SIMR, simr)
1415
1422 #define getSIMR() \
1423 WIZCHIP_READ(SIMR)
1424
1431 #define setRTR(rtr) {\
1432 WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
1433 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1434 }
1435
1442 //M20150401 : Type explict declaration
1443 /*
1444 #define getRTR() \
1445 ((WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1446 */
1447 #define getRTR() \
1448 (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1449
1450
1457 #define setRCR(rcr) \
1458 WIZCHIP_WRITE(_RCR_, rcr)
1459
1466 #define getRCR() \
1467 WIZCHIP_READ(_RCR_)
1468
1469 //================================================== test done ===========================================================
1470
1477 #define setPTIMER(ptimer) \
1478 WIZCHIP_WRITE(PTIMER, ptimer)
1479
1486 #define getPTIMER() \
1487 WIZCHIP_READ(PTIMER)
1488
1495 #define setPMAGIC(pmagic) \
1496 WIZCHIP_WRITE(PMAGIC, pmagic)
1497
1504 #define getPMAGIC() \
1505 WIZCHIP_READ(PMAGIC)
1506
1513 #define setPHAR(phar) \
1514 WIZCHIP_WRITE_BUF(PHAR, phar, 6)
1515
1522 #define getPHAR(phar) \
1523 WIZCHIP_READ_BUF(PHAR, phar, 6)
1524
1531 #define setPSID(psid) {\
1532 WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
1533 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
1534 }
1535
1542 //uint16_t getPSID(void);
1543 //M20150401 : Type explict declaration
1544 /*
1545 #define getPSID() \
1546 ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1547 */
1548 #define getPSID() \
1549 (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1550
1557 #define setPMRU(pmru) { \
1558 WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
1559 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
1560 }
1561
1568 //M20150401 : Type explict declaration
1569 /*
1570 #define getPMRU() \
1571 ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1572 */
1573 #define getPMRU() \
1574 (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1575
1581 //M20150401 : Size Error of UIPR (6 -> 4)
1582 /*
1583 #define getUIPR(uipr) \
1584 WIZCHIP_READ_BUF(UIPR,uipr,6)
1585 */
1586 #define getUIPR(uipr) \
1587 WIZCHIP_READ_BUF(UIPR,uipr,4)
1588
1594 //M20150401 : Type explict declaration
1595 /*
1596 #define getUPORTR() \
1597 ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1598 */
1599 #define getUPORTR() \
1600 (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1601
1608 #define setPHYCFGR(phycfgr) \
1609 WIZCHIP_WRITE(PHYCFGR, phycfgr)
1610
1617 #define getPHYCFGR() \
1618 WIZCHIP_READ(PHYCFGR)
1619
1625 #define getVERSIONR() \
1626 WIZCHIP_READ(VERSIONR)
1627
1629
1631 // Socket N register I/O function //
1633
1640 #define setSn_MR(sn, mr) \
1641 WIZCHIP_WRITE(Sn_MR(sn),mr)
1642
1650 #define getSn_MR(sn) \
1651 WIZCHIP_READ(Sn_MR(sn))
1652
1660 #define setSn_CR(sn, cr) \
1661 WIZCHIP_WRITE(Sn_CR(sn), cr)
1662
1670 #define getSn_CR(sn) \
1671 WIZCHIP_READ(Sn_CR(sn))
1672
1680 #define setSn_IR(sn, ir) \
1681 WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
1682
1690 #define getSn_IR(sn) \
1691 (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
1692
1700 #define setSn_IMR(sn, imr) \
1701 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
1702
1710 #define getSn_IMR(sn) \
1711 (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
1712
1719 #define getSn_SR(sn) \
1720 WIZCHIP_READ(Sn_SR(sn))
1721
1729 #define setSn_PORT(sn, port) { \
1730 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1731 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1732 }
1733
1741 //M20150401 : Type explict declaration
1742 /*
1743 #define getSn_PORT(sn) \
1744 ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1745 */
1746 #define getSn_PORT(sn) \
1747 (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1748
1756 #define setSn_DHAR(sn, dhar) \
1757 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1758
1766 #define getSn_DHAR(sn, dhar) \
1767 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1768
1776 #define setSn_DIPR(sn, dipr) \
1777 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1778
1786 #define getSn_DIPR(sn, dipr) \
1787 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1788
1796 #define setSn_DPORT(sn, dport) { \
1797 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1798 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1799 }
1800
1808 //M20150401 : Type explict declaration
1809 /*
1810 #define getSn_DPORT(sn) \
1811 ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1812 */
1813 #define getSn_DPORT(sn) \
1814 (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1815
1823 #define setSn_MSSR(sn, mss) { \
1824 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1825 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1826 }
1827
1835 //M20150401 : Type explict declaration
1836 /*
1837 #define getSn_MSSR(sn) \
1838 ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1839 */
1840 #define getSn_MSSR(sn) \
1841 (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1842
1850 #define setSn_TOS(sn, tos) \
1851 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1852
1860 #define getSn_TOS(sn) \
1861 WIZCHIP_READ(Sn_TOS(sn))
1862
1870 #define setSn_TTL(sn, ttl) \
1871 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1872
1873
1881 #define getSn_TTL(sn) \
1882 WIZCHIP_READ(Sn_TTL(sn))
1883
1884
1892 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
1893 WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
1894
1895
1903 #define getSn_RXBUF_SIZE(sn) \
1904 WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
1905
1913 #define setSn_TXBUF_SIZE(sn, txbufsize) \
1914 WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
1915
1923 #define getSn_TXBUF_SIZE(sn) \
1924 WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
1925
1932 uint16_t getSn_TX_FSR(uint8_t sn);
1933
1940 //M20150401 : Type explict declaration
1941 /*
1942 #define getSn_TX_RD(sn) \
1943 ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1944 */
1945 #define getSn_TX_RD(sn) \
1946 (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1947
1955 #define setSn_TX_WR(sn, txwr) { \
1956 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1957 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1958 }
1959
1967 //M20150401 : Type explict declaration
1968 /*
1969 #define getSn_TX_WR(sn) \
1970 ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1971 */
1972 #define getSn_TX_WR(sn) \
1973 (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1974
1975
1982 uint16_t getSn_RX_RSR(uint8_t sn);
1983
1984
1992 #define setSn_RX_RD(sn, rxrd) { \
1993 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1994 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1995 }
1996
2004 //M20150401 : Type explict declaration
2005 /*
2006 #define getSn_RX_RD(sn) \
2007 ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
2008 */
2009 #define getSn_RX_RD(sn) \
2010 (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
2011
2018 //M20150401 : Type explict declaration
2019 /*
2020 #define getSn_RX_WR(sn) \
2021 ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
2022 */
2023 #define getSn_RX_WR(sn) \
2024 (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
2025
2033 #define setSn_FRAG(sn, frag) { \
2034 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
2035 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
2036 }
2037
2045 //M20150401 : Type explict declaration
2046 /*
2047 #define getSn_FRAG(sn) \
2048 ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
2049 */
2050 #define getSn_FRAG(sn) \
2051 (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
2052
2060 #define setSn_KPALVTR(sn, kpalvt) \
2061 WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
2062
2070 #define getSn_KPALVTR(sn) \
2071 WIZCHIP_READ(Sn_KPALVTR(sn))
2072
2074
2076 // Sn_TXBUF & Sn_RXBUF IO function //
2078
2083 //M20150401 : Type explict declaration
2084 /*
2085 #define getSn_RxMAX(sn) \
2086 (getSn_RXBUF_SIZE(sn) << 10)
2087 */
2088 #define getSn_RxMAX(sn) \
2089 (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)
2090
2096 //M20150401 : Type explict declaration
2097 /*
2098 #define getSn_TxMAX(sn) \
2099 (getSn_TXBUF_SIZE(sn) << 10)
2100 */
2101 #define getSn_TxMAX(sn) \
2102 (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)
2103
2119 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2120
2136 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2137
2145 void wiz_recv_ignore(uint8_t sn, uint16_t len);
2146
2147 #endif // _W5500_H_
Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/wizchip_conf.c Source File

  • Ethernet
wizchip_conf.c
Go to the documentation of this file.
1 //****************************************************************************/
14 // Issued by Mathias ClauBen.
49 //
50 //*****************************************************************************/
51 //A20140501 : for use the type - ptrdiff_t
52 #include <stddef.h>
53 //
54
55 #include "wizchip_conf.h"
56
58 //M20150401 : Remove ; in the default callback function such as wizchip_cris_enter(), wizchip_cs_select() and etc.
60
66 //void wizchip_cris_enter(void) {};
67 void wizchip_cris_enter(void) {}
68
74 //void wizchip_cris_exit(void) {};
75 void wizchip_cris_exit(void) {}
76
82 //void wizchip_cs_select(void) {};
83 void wizchip_cs_select(void) {}
84
90 //void wizchip_cs_deselect(void) {};
91 void wizchip_cs_deselect(void) {}
92
98 //M20140501 : Explict pointer type casting
99 //uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *) AddrSel); };
100 //uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *)((ptrdiff_t) AddrSel)); };
101 uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *)((ptrdiff_t) AddrSel)); }
102
109 //M20140501 : Explict pointer type casting
110 //void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*) AddrSel) = wb; };
111 //void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*)((ptrdiff_t)AddrSel)) = wb; };
112 void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*)((ptrdiff_t)AddrSel)) = wb; }
113
119 //uint8_t wizchip_spi_readbyte(void) {return 0;};
120 uint8_t wizchip_spi_readbyte(void) {return 0;}
121
127 //void wizchip_spi_writebyte(uint8_t wb) {};
128 void wizchip_spi_writebyte(uint8_t wb) {}
129
135 //void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {};
136 void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {}
137
143 //void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {};
144 void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {}
145
149 //
150 //M20150401 : For a compiler didnot support a member of structure
151 // Replace the assignment of struct members with the assingment of array
152 //
153 /*
154 _WIZCHIP WIZCHIP =
155 {
156 .id = _WIZCHIP_ID_,
157 .if_mode = _WIZCHIP_IO_MODE_,
158 .CRIS._enter = wizchip_cris_enter,
159 .CRIS._exit = wizchip_cris_exit,
160 .CS._select = wizchip_cs_select,
161 .CS._deselect = wizchip_cs_deselect,
162 .IF.BUS._read_byte = wizchip_bus_readbyte,
163 .IF.BUS._write_byte = wizchip_bus_writebyte
164 // .IF.SPI._read_byte = wizchip_spi_readbyte,
165 // .IF.SPI._write_byte = wizchip_spi_writebyte
166 };
167 */
168 _WIZCHIP WIZCHIP =
169 {
170 _WIZCHIP_IO_MODE_,
171 _WIZCHIP_ID_ ,
172 wizchip_cris_enter,
173 wizchip_cris_exit,
174 wizchip_cs_select,
175 wizchip_cs_deselect,
176 wizchip_bus_readbyte,
177 wizchip_bus_writebyte
178 // wizchip_spi_readbyte,
179 // wizchip_spi_writebyte
180 };
181
182
183 static uint8_t _DNS_[4]; // DNS server ip address
184 static dhcp_mode _DHCP_; // DHCP mode
185
186 void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void))
187 {
188 if(!cris_en || !cris_ex)
189 {
190 WIZCHIP.CRIS._enter = wizchip_cris_enter;
191 WIZCHIP.CRIS._exit = wizchip_cris_exit;
192 }
193 else
194 {
195 WIZCHIP.CRIS._enter = cris_en;
196 WIZCHIP.CRIS._exit = cris_ex;
197 }
198 }
199
200 void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void))
201 {
202 if(!cs_sel || !cs_desel)
203 {
204 WIZCHIP.CS._select = wizchip_cs_select;
205 WIZCHIP.CS._deselect = wizchip_cs_deselect;
206 }
207 else
208 {
209 WIZCHIP.CS._select = cs_sel;
210 WIZCHIP.CS._deselect = cs_desel;
211 }
212 }
213
214 void reg_wizchip_bus_cbfunc(uint8_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb))
215 {
216 while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
217
218 if(!bus_rb || !bus_wb)
219 {
220 WIZCHIP.IF.BUS._read_byte = wizchip_bus_readbyte;
221 WIZCHIP.IF.BUS._write_byte = wizchip_bus_writebyte;
222 }
223 else
224 {
225 WIZCHIP.IF.BUS._read_byte = bus_rb;
226 WIZCHIP.IF.BUS._write_byte = bus_wb;
227 }
228 }
229
230 void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb))
231 {
232 while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
233
234 if(!spi_rb || !spi_wb)
235 {
236 WIZCHIP.IF.SPI._read_byte = wizchip_spi_readbyte;
237 WIZCHIP.IF.SPI._write_byte = wizchip_spi_writebyte;
238 }
239 else
240 {
241 WIZCHIP.IF.SPI._read_byte = spi_rb;
242 WIZCHIP.IF.SPI._write_byte = spi_wb;
243 }
244 }
245
246 // 20140626 Eric Added for SPI burst operations
247 void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len))
248 {
249 while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
250
251 if(!spi_rb || !spi_wb)
252 {
253 WIZCHIP.IF.SPI._read_burst = wizchip_spi_readburst;
254 WIZCHIP.IF.SPI._write_burst = wizchip_spi_writeburst;
255 }
256 else
257 {
258 WIZCHIP.IF.SPI._read_burst = spi_rb;
259 WIZCHIP.IF.SPI._write_burst = spi_wb;
260 }
261 }
262
263 int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg)
264 {
265 #if _WIZCHIP_ == 5200 || _WIZCHIP_ == 5500
266 uint8_t tmp = 0;
267 #endif
268 uint8_t* ptmp[2] = {0,0};
269 switch(cwtype)
270 {
271 case CW_RESET_WIZCHIP:
272 wizchip_sw_reset();
273 break;
274 case CW_INIT_WIZCHIP:
275 if(arg != 0)
276 {
277 ptmp[0] = (uint8_t*)arg;
278 ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
279 }
280 return wizchip_init(ptmp[0], ptmp[1]);
281 case CW_CLR_INTERRUPT:
282 wizchip_clrinterrupt(*((intr_kind*)arg));
283 break;
284 case CW_GET_INTERRUPT:
285 *((intr_kind*)arg) = wizchip_getinterrupt();
286 break;
287 case CW_SET_INTRMASK:
288 wizchip_setinterruptmask(*((intr_kind*)arg));
289 break;
290 case CW_GET_INTRMASK:
291 *((intr_kind*)arg) = wizchip_getinterruptmask();
292 break;
293 #if _WIZCHIP_ > 5100
294 case CW_SET_INTRTIME:
295 setINTLEVEL(*(uint16_t*)arg);
296 break;
297 case CW_GET_INTRTIME:
298 *(uint16_t*)arg = getINTLEVEL();
299 break;
300 #endif
301 case CW_GET_ID:
302 ((uint8_t*)arg)[0] = WIZCHIP.id[0];
303 ((uint8_t*)arg)[1] = WIZCHIP.id[1];
304 ((uint8_t*)arg)[2] = WIZCHIP.id[2];
305 ((uint8_t*)arg)[3] = WIZCHIP.id[3];
306 ((uint8_t*)arg)[4] = WIZCHIP.id[4];
307 ((uint8_t*)arg)[5] = 0;
308 break;
309 #if _WIZCHIP_ == 5500
310 case CW_RESET_PHY:
311 wizphy_reset();
312 break;
313 case CW_SET_PHYCONF:
314 wizphy_setphyconf((wiz_PhyConf*)arg);
315 break;
316 case CW_GET_PHYCONF:
317 wizphy_getphyconf((wiz_PhyConf*)arg);
318 break;
319 case CW_GET_PHYSTATUS:
320 break;
321 case CW_SET_PHYPOWMODE:
322 return wizphy_setphypmode(*(uint8_t*)arg);
323 #endif
324 #if _WIZCHIP_ == 5200 || _WIZCHIP_ == 5500
325 case CW_GET_PHYPOWMODE:
326 tmp = wizphy_getphypmode();
327 if((int8_t)tmp == -1) return -1;
328 *(uint8_t*)arg = tmp;
329 break;
330 case CW_GET_PHYLINK:
331 tmp = wizphy_getphylink();
332 if((int8_t)tmp == -1) return -1;
333 *(uint8_t*)arg = tmp;
334 break;
335 #endif
336 default:
337 return -1;
338 }
339 return 0;
340 }
341
342
343 int8_t ctlnetwork(ctlnetwork_type cntype, void* arg)
344 {
345
346 switch(cntype)
347 {
348 case CN_SET_NETINFO:
349 wizchip_setnetinfo((wiz_NetInfo*)arg);
350 break;
351 case CN_GET_NETINFO:
352 wizchip_getnetinfo((wiz_NetInfo*)arg);
353 break;
354 case CN_SET_NETMODE:
355 return wizchip_setnetmode(*(netmode_type*)arg);
356 case CN_GET_NETMODE:
357 *(netmode_type*)arg = wizchip_getnetmode();
358 break;
359 case CN_SET_TIMEOUT:
360 wizchip_settimeout((wiz_NetTimeout*)arg);
361 break;
362 case CN_GET_TIMEOUT:
363 wizchip_gettimeout((wiz_NetTimeout*)arg);
364 break;
365 default:
366 return -1;
367 }
368 return 0;
369 }
370
371 void wizchip_sw_reset(void)
372 {
373 uint8_t gw[4], sn[4], sip[4];
374 uint8_t mac[6];
375 getSHAR(mac);
376 getGAR(gw); getSUBR(sn); getSIPR(sip);
377 setMR(MR_RST);
378 getMR(); // for delay
379 setSHAR(mac);
380 setGAR(gw);
381 setSUBR(sn);
382 setSIPR(sip);
383 }
384
385 int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize)
386 {
387 int8_t i;
388 int8_t tmp = 0;
389 wizchip_sw_reset();
390 if(txsize)
391 {
392 tmp = 0;
393 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
394 tmp += txsize[i];
395 if(tmp > 16) return -1;
396 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
397 setSn_TXBUF_SIZE(i, txsize[i]);
398 }
399 if(rxsize)
400 {
401 tmp = 0;
402 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
403 tmp += rxsize[i];
404 if(tmp > 16) return -1;
405 for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
406 setSn_RXBUF_SIZE(i, rxsize[i]);
407 }
408 return 0;
409 }
410
411 void wizchip_clrinterrupt(intr_kind intr)
412 {
413 uint8_t ir = (uint8_t)intr;
414 uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
415 #if _WIZCHIP_ < 5500
416 ir |= (1<<4); // IK_WOL
417 #endif
418 #if _WIZCHIP_ == 5200
419 ir |= (1 << 6);
420 #endif
421
422 #if _WIZCHIP_ < 5200
423 sir &= 0x0F;
424 #endif
425
426 #if _WIZCHIP_ == 5100
427 ir |= sir;
428 setIR(ir);
429 #else
430 setIR(ir);
431 setSIR(sir);
432 #endif
433 }
434
435 intr_kind wizchip_getinterrupt(void)
436 {
437 uint8_t ir = 0;
438 uint8_t sir = 0;
439 uint16_t ret = 0;
440 #if _WIZCHIP_ == 5100
441 ir = getIR();
442 sir = ir & 0x0F;
443 #else
444 ir = getIR();
445 sir = getSIR();
446 #endif
447
448 #if _WIZCHIP_ < 5500
449 ir &= ~(1<<4); // IK_WOL
450 #endif
451 #if _WIZCHIP_ == 5200
452 ir &= ~(1 << 6);
453 #endif
454 ret = sir;
455 ret = (ret << 8) + ir;
456 return (intr_kind)ret;
457 }
458
459 void wizchip_setinterruptmask(intr_kind intr)
460 {
461 uint8_t imr = (uint8_t)intr;
462 uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
463 #if _WIZCHIP_ < 5500
464 imr &= ~(1<<4); // IK_WOL
465 #endif
466 #if _WIZCHIP_ == 5200
467 imr &= ~(1 << 6);
468 #endif
469
470 #if _WIZCHIP_ == 5100
471 simr &= 0x0F;
472 imr |= simr;
473 setIMR(imr);
474 #else
475 setIMR(imr);
476 setSIMR(simr);
477 #endif
478 }
479
480 intr_kind wizchip_getinterruptmask(void)
481 {
482 uint8_t imr = 0;
483 uint8_t simr = 0;
484 uint16_t ret = 0;
485 #if _WIZCHIP_ == 5100
486 imr = getIMR();
487 simr = imr & 0x0F;
488 #else
489 imr = getIMR();
490 simr = getSIMR();
491 #endif
492
493 #if _WIZCHIP_ < 5500
494 imr &= ~(1<<4); // IK_WOL
495 #endif
496 #if _WIZCHIP_ == 5200
497 imr &= ~(1 << 6); // IK_DEST_UNREACH
498 #endif
499 ret = simr;
500 ret = (ret << 8) + imr;
501 return (intr_kind)ret;
502 }
503
504 int8_t wizphy_getphylink(void)
505 {
506 int8_t tmp;
507 #if _WIZCHIP_ == 5200
508 if(getPHYSTATUS() & PHYSTATUS_LINK)
509 tmp = PHY_LINK_ON;
510 else
511 tmp = PHY_LINK_OFF;
512 #elif _WIZCHIP_ == 5500
513 if(getPHYCFGR() & PHYCFGR_LNK_ON)
514 tmp = PHY_LINK_ON;
515 else
516 tmp = PHY_LINK_OFF;
517 #else
518 tmp = -1;
519 #endif
520 return tmp;
521 }
522
523 #if _WIZCHIP_ > 5100
524
525 int8_t wizphy_getphypmode(void)
526 {
527 int8_t tmp = 0;
528 #if _WIZCHIP_ == 5200
529 if(getPHYSTATUS() & PHYSTATUS_POWERDOWN)
530 tmp = PHY_POWER_DOWN;
531 else
532 tmp = PHY_POWER_NORM;
533 #elif _WIZCHIP_ == 5500
534 if(getPHYCFGR() & PHYCFGR_OPMDC_PDOWN)
535 tmp = PHY_POWER_DOWN;
536 else
537 tmp = PHY_POWER_NORM;
538 #else
539 tmp = -1;
540 #endif
541 return tmp;
542 }
543 #endif
544
545 #if _WIZCHIP_ == 5500
546 void wizphy_reset(void)
547 {
548 uint8_t tmp = getPHYCFGR();
549 tmp &= PHYCFGR_RST;
550 setPHYCFGR(tmp);
551 tmp = getPHYCFGR();
552 tmp |= ~PHYCFGR_RST;
553 setPHYCFGR(tmp);
554 }
555
556 void wizphy_setphyconf(wiz_PhyConf* phyconf)
557 {
558 uint8_t tmp = 0;
559 if(phyconf->by == PHY_CONFBY_SW)
560 tmp |= PHYCFGR_OPMD;
561 else
562 tmp &= ~PHYCFGR_OPMD;
563 if(phyconf->mode == PHY_MODE_AUTONEGO)
564 tmp |= PHYCFGR_OPMDC_ALLA;
565 else
566 {
567 if(phyconf->duplex == PHY_DUPLEX_FULL)
568 {
569 if(phyconf->speed == PHY_SPEED_100)
570 tmp |= PHYCFGR_OPMDC_100F;
571 else
572 tmp |= PHYCFGR_OPMDC_10F;
573 }
574 else
575 {
576 if(phyconf->speed == PHY_SPEED_100)
577 tmp |= PHYCFGR_OPMDC_100H;
578 else
579 tmp |= PHYCFGR_OPMDC_10H;
580 }
581 }
582 setPHYCFGR(tmp);
583 wizphy_reset();
584 }
585
586 void wizphy_getphyconf(wiz_PhyConf* phyconf)
587 {
588 uint8_t tmp = 0;
589 tmp = getPHYCFGR();
590 phyconf->by = (tmp & PHYCFGR_OPMD) ? PHY_CONFBY_SW : PHY_CONFBY_HW;
591 switch(tmp & PHYCFGR_OPMDC_ALLA)
592 {
593 case PHYCFGR_OPMDC_ALLA:
594 case PHYCFGR_OPMDC_100FA:
595 phyconf->mode = PHY_MODE_AUTONEGO;
596 break;
597 default:
598 phyconf->mode = PHY_MODE_MANUAL;
599 break;
600 }
601 switch(tmp & PHYCFGR_OPMDC_ALLA)
602 {
603 case PHYCFGR_OPMDC_100FA:
604 case PHYCFGR_OPMDC_100F:
605 case PHYCFGR_OPMDC_100H:
606 phyconf->speed = PHY_SPEED_100;
607 break;
608 default:
609 phyconf->speed = PHY_SPEED_10;
610 break;
611 }
612 switch(tmp & PHYCFGR_OPMDC_ALLA)
613 {
614 case PHYCFGR_OPMDC_100FA:
615 case PHYCFGR_OPMDC_100F:
616 case PHYCFGR_OPMDC_10F:
617 phyconf->duplex = PHY_DUPLEX_FULL;
618 break;
619 default:
620 phyconf->duplex = PHY_DUPLEX_HALF;
621 break;
622 }
623 }
624
625 void wizphy_getphystat(wiz_PhyConf* phyconf)
626 {
627 uint8_t tmp = getPHYCFGR();
628 phyconf->duplex = (tmp & PHYCFGR_DPX_FULL) ? PHY_DUPLEX_FULL : PHY_DUPLEX_HALF;
629 phyconf->speed = (tmp & PHYCFGR_SPD_100) ? PHY_SPEED_100 : PHY_SPEED_10;
630 }
631
632 int8_t wizphy_setphypmode(uint8_t pmode)
633 {
634 uint8_t tmp = 0;
635 tmp = getPHYCFGR();
636 if((tmp & PHYCFGR_OPMD)== 0) return -1;
637 tmp &= ~PHYCFGR_OPMDC_ALLA;
638 if( pmode == PHY_POWER_DOWN)
639 tmp |= PHYCFGR_OPMDC_PDOWN;
640 else
641 tmp |= PHYCFGR_OPMDC_ALLA;
642 setPHYCFGR(tmp);
643 wizphy_reset();
644 tmp = getPHYCFGR();
645 if( pmode == PHY_POWER_DOWN)
646 {
647 if(tmp & PHYCFGR_OPMDC_PDOWN) return 0;
648 }
649 else
650 {
651 if(tmp & PHYCFGR_OPMDC_ALLA) return 0;
652 }
653 return -1;
654 }
655 #endif
656
657
658 void wizchip_setnetinfo(wiz_NetInfo* pnetinfo)
659 {
660 setSHAR(pnetinfo->mac);
661 setGAR(pnetinfo->gw);
662 setSUBR(pnetinfo->sn);
663 setSIPR(pnetinfo->ip);
664 _DNS_[0] = pnetinfo->dns[0];
665 _DNS_[1] = pnetinfo->dns[1];
666 _DNS_[2] = pnetinfo->dns[2];
667 _DNS_[3] = pnetinfo->dns[3];
668 _DHCP_ = pnetinfo->dhcp;
669 }
670
671 void wizchip_getnetinfo(wiz_NetInfo* pnetinfo)
672 {
673 getSHAR(pnetinfo->mac);
674 getGAR(pnetinfo->gw);
675 getSUBR(pnetinfo->sn);
676 getSIPR(pnetinfo->ip);
677 pnetinfo->dns[0]= _DNS_[0];
678 pnetinfo->dns[1]= _DNS_[1];
679 pnetinfo->dns[2]= _DNS_[2];
680 pnetinfo->dns[3]= _DNS_[3];
681 pnetinfo->dhcp = _DHCP_;
682 }
683
684 int8_t wizchip_setnetmode(netmode_type netmode)
685 {
686 uint8_t tmp = 0;
687 #if _WIZCHIP_ != 5500
688 if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK)) return -1;
689 #else
690 if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK | NM_FORCEARP)) return -1;
691 #endif
692 tmp = getMR();
693 tmp |= (uint8_t)netmode;
694 setMR(tmp);
695 return 0;
696 }
697
698 netmode_type wizchip_getnetmode(void)
699 {
700 return (netmode_type) getMR();
701 }
702
703 void wizchip_settimeout(wiz_NetTimeout* nettime)
704 {
705 setRCR(nettime->retry_cnt);
706 setRTR(nettime->time_100us);
707 }
708
709 void wizchip_gettimeout(wiz_NetTimeout* nettime)
710 {
711 nettime->retry_cnt = getRCR();
712 nettime->time_100us = getRTR();
713 }
Generated on Thu Apr 9 2015 14:44:01 for Socket APIs by doxygen 1.8.4


Socket APIs: Ethernet/wizchip_conf.h Source File

  • Ethernet
wizchip_conf.h
Go to the documentation of this file.
1 //*****************************************************************************
2 //
43 //
44 //*****************************************************************************
45
54 #ifndef _WIZCHIP_CONF_H_
55 #define _WIZCHIP_CONF_H_
56
57 #include <stdint.h>
63 #define _WIZCHIP_ 5500 // 5100, 5200, 5500
64
65 #define _WIZCHIP_IO_MODE_NONE_ 0x0000
66 #define _WIZCHIP_IO_MODE_BUS_ 0x0100
67 #define _WIZCHIP_IO_MODE_SPI_ 0x0200
68 //#define _WIZCHIP_IO_MODE_IIC_ 0x0400
69 //#define _WIZCHIP_IO_MODE_SDIO_ 0x0800
70 // Add to
71 //
72
73 #define _WIZCHIP_IO_MODE_BUS_DIR_ (_WIZCHIP_IO_MODE_BUS_ + 1)
74 #define _WIZCHIP_IO_MODE_BUS_INDIR_ (_WIZCHIP_IO_MODE_BUS_ + 2)
76 #define _WIZCHIP_IO_MODE_SPI_VDM_ (_WIZCHIP_IO_MODE_SPI_ + 1)
77 #define _WIZCHIP_IO_MODE_SPI_FDM_ (_WIZCHIP_IO_MODE_SPI_ + 2)
80 #if (_WIZCHIP_ == 5100)
81 #define _WIZCHIP_ID_ "W5100\0"
82
87 // #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_DIR_
88 // #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
89 #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_
90 //A20150401 : Indclude W5100.h file
91 #include "W5100/w5100.h"
92
93 #elif (_WIZCHIP_ == 5200)
94 #define _WIZCHIP_ID_ "W5200\0"
95
99 // #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_BUS_INDIR_
100 #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_
101 #include "W5200/w5200.h"
102 #elif (_WIZCHIP_ == 5500)
103 #define _WIZCHIP_ID_ "W5500\0"
104
118 //#define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_FDM_
119 #define _WIZCHIP_IO_MODE_ _WIZCHIP_IO_MODE_SPI_VDM_
120 #include "W5500/w5500.h"
121 #else
122 #error "Unknown defined _WIZCHIP_. You should define one of 5100, 5200, and 5500 !!!"
123 #endif
124
125 #ifndef _WIZCHIP_IO_MODE_
126 #error "Undefined _WIZCHIP_IO_MODE_. You should define it !!!"
127 #endif
128
135 #define _WIZCHIP_IO_BASE_ 0x00000000 //
136
137 //M20150401 : Typing Error
138 //#if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS
139 #if _WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_
140 #ifndef _WIZCHIP_IO_BASE_
141 #error "You should be define _WIZCHIP_IO_BASE to fit your system memory map."
142 #endif
143 #endif
144
145 #if _WIZCHIP_ > 5100
146 #define _WIZCHIP_SOCK_NUM_ 8
147 #else
148 #define _WIZCHIP_SOCK_NUM_ 4
149 #endif
150
151
152 /********************************************************
153 * WIZCHIP BASIC IF functions for SPI, SDIO, I2C , ETC.
154 *********************************************************/
159 typedef struct __WIZCHIP
160 {
161 uint16_t if_mode;
162 uint8_t id[6];
163
166 struct _CRIS
167 {
168 void (*_enter) (void);
169 void (*_exit) (void);
170 }CRIS;
174 struct _CS
175 {
176 void (*_select) (void);
177 void (*_deselect)(void);
178 }CS;
182 union _IF
183 {
187 struct
188 {
189 uint8_t (*_read_byte) (uint32_t AddrSel);
190 void (*_write_byte) (uint32_t AddrSel, uint8_t wb);
191 }BUS;
195 struct
196 {
197 uint8_t (*_read_byte) (void);
198 void (*_write_byte) (uint8_t wb);
199 void (*_read_burst) (uint8_t* pBuf, uint16_t len);
200 void (*_write_burst) (uint8_t* pBuf, uint16_t len);
201 }SPI;
202 // To be added
203 //
204 }IF;
205 }_WIZCHIP;
206
207 extern _WIZCHIP WIZCHIP;
208
213 typedef enum
214 {
215 CW_RESET_WIZCHIP,
216 CW_INIT_WIZCHIP,
217 CW_GET_INTERRUPT,
218 CW_CLR_INTERRUPT,
219 CW_SET_INTRMASK,
220 CW_GET_INTRMASK,
221 CW_SET_INTRTIME,
222 CW_GET_INTRTIME,
223 CW_GET_ID,
224
225 #if _WIZCHIP_ == 5500
226 CW_RESET_PHY,
227 CW_SET_PHYCONF,
228 CW_GET_PHYCONF,
229 CW_GET_PHYSTATUS,
230 CW_SET_PHYPOWMODE,
231 #endif
232 #if _WIZCHIP_ == 5200 || _WIZCHIP_ == 5500
233 CW_GET_PHYPOWMODE,
234 CW_GET_PHYLINK
235 #endif
236 }ctlwizchip_type;
237
242 typedef enum
243 {
244 CN_SET_NETINFO,
245 CN_GET_NETINFO,
246 CN_SET_NETMODE,
247 CN_GET_NETMODE,
248 CN_SET_TIMEOUT,
249 CN_GET_TIMEOUT,
250 }ctlnetwork_type;
251
258 typedef enum
259 {
260 #if _WIZCHIP_ == 5500
261 IK_WOL = (1 << 4),
262 #elif _WIZCHIP_ == 5300
263 IK_FMTU = (1 << 4),
264 #endif
265
266 IK_PPPOE_TERMINATED = (1 << 5),
267
268 #if _WIZCHIP_ != 5200
269 IK_DEST_UNREACH = (1 << 6),
270 #endif
271
272 IK_IP_CONFLICT = (1 << 7),
273
274 IK_SOCK_0 = (1 << 8),
275 IK_SOCK_1 = (1 << 9),
276 IK_SOCK_2 = (1 << 10),
277 IK_SOCK_3 = (1 << 11),
278 #if _WIZCHIP_ > 5100
279 IK_SOCK_4 = (1 << 12),
280 IK_SOCK_5 = (1 << 13),
281 IK_SOCK_6 = (1 << 14),
282 IK_SOCK_7 = (1 << 15),
283 #endif
284
285 #if _WIZCHIP_ > 5100
286 IK_SOCK_ALL = (0xFF << 8)
287 #else
288 IK_SOCK_ALL = (0x0F << 8)
289 #endif
290 }intr_kind;
291
292 #define PHY_CONFBY_HW 0
293 #define PHY_CONFBY_SW 1
294 #define PHY_MODE_MANUAL 0
295 #define PHY_MODE_AUTONEGO 1
296 #define PHY_SPEED_10 0
297 #define PHY_SPEED_100 1
298 #define PHY_DUPLEX_HALF 0
299 #define PHY_DUPLEX_FULL 1
300 #define PHY_LINK_OFF 0
301 #define PHY_LINK_ON 1
302 #define PHY_POWER_NORM 0
303 #define PHY_POWER_DOWN 1
304
305
306 #if _WIZCHIP_ == 5500
307
313 typedef struct wiz_PhyConf_t
314 {
315 uint8_t by;
316 uint8_t mode;
317 uint8_t speed;
318 uint8_t duplex;
319 //uint8_t power; ///< set by @ref PHY_POWER_NORM or @ref PHY_POWER_DOWN
320 //uint8_t link; ///< Valid only in CW_GET_PHYSTATUS. set by @ref PHY_LINK_ON or PHY_DUPLEX_OFF
321 }wiz_PhyConf;
322 #endif
323
328 typedef enum
329 {
330 NETINFO_STATIC = 1,
331 NETINFO_DHCP
332 }dhcp_mode;
333
338 typedef struct wiz_NetInfo_t
339 {
340 uint8_t mac[6];
341 uint8_t ip[4];
342 uint8_t sn[4];
343 uint8_t gw[4];
344 uint8_t dns[4];
345 dhcp_mode dhcp;
346 }wiz_NetInfo;
347
352 typedef enum
353 {
354 #if _WIZCHIP_ == 5500
355 NM_FORCEARP = (1<<1),
356 #endif
357 NM_WAKEONLAN = (1<<5),
358 NM_PINGBLOCK = (1<<4),
359 NM_PPPOE = (1<<3),
360 }netmode_type;
361
366 typedef struct wiz_NetTimeout_t
367 {
368 uint8_t retry_cnt;
369 uint16_t time_100us;
370 }wiz_NetTimeout;
371
380 void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void));
381
382
390 void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void));
391
400 void reg_wizchip_bus_cbfunc(uint8_t (*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb));
401
410 void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb));
411
420 void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len));
421
432 int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg);
433
443 int8_t ctlnetwork(ctlnetwork_type cntype, void* arg);
444
445
446 /*
447 * The following functions are implemented for internal use.
448 * but You can call these functions for code size reduction instead of ctlwizchip() and ctlnetwork().
449 */
450
455 void wizchip_sw_reset(void);
456
465 int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize);
466
472 void wizchip_clrinterrupt(intr_kind intr);
473
479 intr_kind wizchip_getinterrupt(void);
480
486 void wizchip_setinterruptmask(intr_kind intr);
487
493 intr_kind wizchip_getinterruptmask(void);
494
495 #if _WIZCHIP_ > 5100
496 int8_t wizphy_getphylink(void);
497 int8_t wizphy_getphypmode(void);
498 #endif
499
500 #if _WIZCHIP_ == 5500
501 void wizphy_reset(void);
502
507 void wizphy_setphyconf(wiz_PhyConf* phyconf);
513 void wizphy_getphyconf(wiz_PhyConf* phyconf);
519 void wizphy_getphystat(wiz_PhyConf* phyconf);
525 int8_t wizphy_setphypmode(uint8_t pmode);
526 #endif
527
533 void wizchip_setnetinfo(wiz_NetInfo* pnetinfo);
534
540 void wizchip_getnetinfo(wiz_NetInfo* pnetinfo);
541
547 int8_t wizchip_setnetmode(netmode_type netmode);
548
554 netmode_type wizchip_getnetmode(void);
555
562 void wizchip_settimeout(wiz_NetTimeout* nettime);
563
570 void wizchip_gettimeout(wiz_NetTimeout* nettime);
571
572 #endif // _WIZCHIP_CONF_H_
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