changes
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70
AD7190.h
70
AD7190.h
@ -76,30 +76,30 @@
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#define AD7190_REG_FULLSCALE 7 // Full-Scale Register (RW, 24-bit)
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/* Communications Register Bit Designations (AD7190_REG_COMM) */
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#define AD7190_COMM_WEN (1 << 7) // Write Enable.
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#define AD7190_COMM_WRITE (0 << 6) // Write Operation.
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#define AD7190_COMM_READ (1 << 6) // Read Operation.
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#define AD7190_COMM_ADDR(x) (((x) & 0x7) << 3) // Register Address.
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#define AD7190_COMM_CREAD (1 << 2) // Continuous Read of Data Register.
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#define AD7190_COMM_WEN (1L << 7) // Write Enable.
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#define AD7190_COMM_WRITE (0L << 6) // Write Operation.
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#define AD7190_COMM_READ (1L << 6) // Read Operation.
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#define AD7190_COMM_ADDR(x) ((((unsigned long)x) & 0x7) << 3) // Register Address.
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#define AD7190_COMM_CREAD (1L << 2) // Continuous Read of Data Register.
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/* Status Register Bit Designations (AD7190_REG_STAT) */
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#define AD7190_STAT_RDY (1 << 7) // Ready.
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#define AD7190_STAT_ERR (1 << 6) // ADC error bit.
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#define AD7190_STAT_NOREF (1 << 5) // Error no external reference.
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#define AD7190_STAT_PARITY (1 << 4) // Parity check of the data register.
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#define AD7190_STAT_CH2 (1 << 2) // Channel 2.
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#define AD7190_STAT_CH1 (1 << 1) // Channel 1.
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#define AD7190_STAT_CH0 (1 << 0) // Channel 0.
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#define AD7190_STAT_RDY (1L << 7) // Ready.
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#define AD7190_STAT_ERR (1L << 6) // ADC error bit.
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#define AD7190_STAT_NOREF (1L << 5) // Error no external reference.
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#define AD7190_STAT_PARITY (1L << 4) // Parity check of the data register.
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#define AD7190_STAT_CH2 (1L << 2) // Channel 2.
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#define AD7190_STAT_CH1 (1L << 1) // Channel 1.
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#define AD7190_STAT_CH0 (1L << 0) // Channel 0.
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/* Mode Register Bit Designations (AD7190_REG_MODE) */
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#define AD7190_MODE_SEL(x) (((x) & 0x7) << 21) // Operation Mode Select.
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#define AD7190_MODE_DAT_STA (1 << 20) // Status Register transmission.
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#define AD7190_MODE_CLKSRC(x) (((x) & 0x3) << 18) // Clock Source Select.
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#define AD7190_MODE_SINC3 (1 << 15) // SINC3 Filter Select.
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#define AD7190_MODE_ENPAR (1 << 13) // Parity Enable.
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#define AD7190_MODE_SCYCLE (1 << 11) // Single cycle conversion.
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#define AD7190_MODE_REJ60 (1 << 10) // 50/60Hz notch filter.
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#define AD7190_MODE_RATE(x) ((x) & 0x3FF) // Filter Update Rate Select.
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#define AD7190_MODE_SEL(x) ((((unsigned long)x) & 0x7) << 21) // Operation Mode Select.
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#define AD7190_MODE_DAT_STA (1L << 20) // Status Register transmission.
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#define AD7190_MODE_CLKSRC(x) ((((unsigned long)x) & 0x3) << 18) // Clock Source Select.
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#define AD7190_MODE_SINC3 (1L << 15) // SINC3 Filter Select.
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#define AD7190_MODE_ENPAR (1L << 13) // Parity Enable.
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#define AD7190_MODE_SCYCLE (1L << 11) // Single cycle conversion.
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#define AD7190_MODE_REJ60 (1L << 10) // 50/60Hz notch filter.
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#define AD7190_MODE_RATE(x) (((unsigned long)x) & 0x3FF) // Filter Update Rate Select.
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/* Mode Register: AD7190_MODE_SEL(x) options */
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#define AD7190_MODE_CONT 0 // Continuous Conversion Mode.
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@ -121,14 +121,14 @@
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// clock is available on MCLK2.
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/* Configuration Register Bit Designations (AD7190_REG_CONF) */
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#define AD7190_CONF_CHOP (1 << 23) // CHOP enable.
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#define AD7190_CONF_REFSEL (1 << 20) // REFIN1/REFIN2 Reference Select.
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#define AD7190_CONF_CHAN(x) (((x) & 0xFF) << 8) // Channel select.
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#define AD7190_CONF_BURN (1 << 7) // Burnout current enable.
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#define AD7190_CONF_REFDET (1 << 6) // Reference detect enable.
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#define AD7190_CONF_BUF (1 << 4) // Buffered Mode Enable.
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#define AD7190_CONF_UNIPOLAR (1 << 3) // Unipolar/Bipolar Enable.
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#define AD7190_CONF_GAIN(x) ((x) & 0x7) // Gain Select.
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#define AD7190_CONF_CHOP (1L << 23) // CHOP enable.
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#define AD7190_CONF_REFSEL (1L << 20) // REFIN1/REFIN2 Reference Select.
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#define AD7190_CONF_CHAN(x) ((((unsigned long)x) & 0xFF) << 8) // Channel select.
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#define AD7190_CONF_BURN (1L << 7) // Burnout current enable.
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#define AD7190_CONF_REFDET (1L << 6) // Reference detect enable.
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#define AD7190_CONF_BUF (1L << 4) // Buffered Mode Enable.
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#define AD7190_CONF_UNIPOLAR (1L << 3) // Unipolar/Bipolar Enable.
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#define AD7190_CONF_GAIN(x) (((unsigned long)x) & 0x7) // Gain Select.
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/* Configuration Register: AD7190_CONF_CHAN(x) options */
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#define AD7190_CH_AIN1P_AIN2M 0 // AIN1(+) - AIN2(-)
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@ -154,13 +154,13 @@
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#define AD7190_ID_MASK 0x0F
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/* GPOCON Register Bit Designations (AD7190_REG_GPOCON) */
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#define AD7190_GPOCON_BPDSW (1 << 6) // Bridge power-down switch enable
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#define AD7190_GPOCON_GP32EN (1 << 5) // Digital Output P3 and P2 enable
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#define AD7190_GPOCON_GP10EN (1 << 4) // Digital Output P1 and P0 enable
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#define AD7190_GPOCON_P3DAT (1 << 3) // P3 state
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#define AD7190_GPOCON_P2DAT (1 << 2) // P2 state
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#define AD7190_GPOCON_P1DAT (1 << 1) // P1 state
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#define AD7190_GPOCON_P0DAT (1 << 0) // P0 state
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#define AD7190_GPOCON_BPDSW (1L << 6) // Bridge power-down switch enable
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#define AD7190_GPOCON_GP32EN (1L << 5) // Digital Output P3 and P2 enable
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#define AD7190_GPOCON_GP10EN (1L << 4) // Digital Output P1 and P0 enable
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#define AD7190_GPOCON_P3DAT (1L << 3) // P3 state
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#define AD7190_GPOCON_P2DAT (1L << 2) // P2 state
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#define AD7190_GPOCON_P1DAT (1L << 1) // P1 state
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#define AD7190_GPOCON_P0DAT (1L << 0) // P0 state
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/******************************************************************************/
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