635 lines
17 KiB
C++
635 lines
17 KiB
C++
/*
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* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
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* SPI Master library for arduino.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of either the GNU General Public License version 2
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* or the GNU Lesser General Public License version 2.1, both as
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* published by the Free Software Foundation.
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*/
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#include "SPI.h"
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#include "pins_arduino.h"
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/**********************************************************/
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/* 8 bit AVR-based boards */
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/**********************************************************/
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#if defined(__AVR__)
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SPIClass SPI;
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uint8_t SPIClass::interruptMode = 0;
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uint8_t SPIClass::interruptMask = 0;
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uint8_t SPIClass::interruptSave = 0;
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#ifdef SPI_TRANSACTION_MISMATCH_LED
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uint8_t SPIClass::inTransactionFlag = 0;
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#endif
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void SPIClass::begin()
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{
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// Set SS to high so a connected chip will be "deselected" by default
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digitalWrite(SS, HIGH);
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// When the SS pin is set as OUTPUT, it can be used as
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// a general purpose output port (it doesn't influence
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// SPI operations).
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pinMode(SS, OUTPUT);
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// Warning: if the SS pin ever becomes a LOW INPUT then SPI
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// automatically switches to Slave, so the data direction of
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// the SS pin MUST be kept as OUTPUT.
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SPCR |= _BV(MSTR);
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SPCR |= _BV(SPE);
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// Set direction register for SCK and MOSI pin.
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// MISO pin automatically overrides to INPUT.
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// By doing this AFTER enabling SPI, we avoid accidentally
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// clocking in a single bit since the lines go directly
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// from "input" to SPI control.
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// http://code.google.com/p/arduino/issues/detail?id=888
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pinMode(SCK, OUTPUT);
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pinMode(MOSI, OUTPUT);
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}
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void SPIClass::end() {
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SPCR &= ~_BV(SPE);
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}
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// mapping of interrupt numbers to bits within SPI_AVR_EIMSK
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#if defined(__AVR_ATmega32U4__)
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#define SPI_INT0_MASK (1<<INT0)
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#define SPI_INT1_MASK (1<<INT1)
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#define SPI_INT2_MASK (1<<INT2)
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#define SPI_INT3_MASK (1<<INT3)
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#define SPI_INT4_MASK (1<<INT6)
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#elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
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#define SPI_INT0_MASK (1<<INT0)
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#define SPI_INT1_MASK (1<<INT1)
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#define SPI_INT2_MASK (1<<INT2)
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#define SPI_INT3_MASK (1<<INT3)
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#define SPI_INT4_MASK (1<<INT4)
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#define SPI_INT5_MASK (1<<INT5)
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#define SPI_INT6_MASK (1<<INT6)
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#define SPI_INT7_MASK (1<<INT7)
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#elif defined(EICRA) && defined(EICRB) && defined(EIMSK)
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#define SPI_INT0_MASK (1<<INT4)
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#define SPI_INT1_MASK (1<<INT5)
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#define SPI_INT2_MASK (1<<INT0)
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#define SPI_INT3_MASK (1<<INT1)
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#define SPI_INT4_MASK (1<<INT2)
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#define SPI_INT5_MASK (1<<INT3)
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#define SPI_INT6_MASK (1<<INT6)
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#define SPI_INT7_MASK (1<<INT7)
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#else
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#ifdef INT0
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#define SPI_INT0_MASK (1<<INT0)
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#endif
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#ifdef INT1
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#define SPI_INT1_MASK (1<<INT1)
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#endif
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#ifdef INT2
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#define SPI_INT2_MASK (1<<INT2)
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#endif
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#endif
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void SPIClass::usingInterrupt(uint8_t interruptNumber)
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{
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uint8_t stmp, mask;
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if (interruptMode > 1) return;
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stmp = SREG;
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noInterrupts();
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switch (interruptNumber) {
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#ifdef SPI_INT0_MASK
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case 0: mask = SPI_INT0_MASK; break;
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#endif
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#ifdef SPI_INT1_MASK
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case 1: mask = SPI_INT1_MASK; break;
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#endif
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#ifdef SPI_INT2_MASK
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case 2: mask = SPI_INT2_MASK; break;
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#endif
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#ifdef SPI_INT3_MASK
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case 3: mask = SPI_INT3_MASK; break;
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#endif
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#ifdef SPI_INT4_MASK
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case 4: mask = SPI_INT4_MASK; break;
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#endif
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#ifdef SPI_INT5_MASK
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case 5: mask = SPI_INT5_MASK; break;
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#endif
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#ifdef SPI_INT6_MASK
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case 6: mask = SPI_INT6_MASK; break;
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#endif
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#ifdef SPI_INT7_MASK
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case 7: mask = SPI_INT7_MASK; break;
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#endif
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default:
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interruptMode = 2;
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SREG = stmp;
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return;
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}
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interruptMode = 1;
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interruptMask |= mask;
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SREG = stmp;
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}
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/**********************************************************/
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/* 32 bit Teensy 3.0 and 3.1 */
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/**********************************************************/
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#elif defined(__arm__) && defined(TEENSYDUINO) && defined(KINETISK)
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SPIClass SPI;
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uint8_t SPIClass::interruptMasksUsed = 0;
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uint32_t SPIClass::interruptMask[(NVIC_NUM_INTERRUPTS+31)/32];
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uint32_t SPIClass::interruptSave[(NVIC_NUM_INTERRUPTS+31)/32];
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#ifdef SPI_TRANSACTION_MISMATCH_LED
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uint8_t SPIClass::inTransactionFlag = 0;
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#endif
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void SPIClass::begin()
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{
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SIM_SCGC6 |= SIM_SCGC6_SPI0;
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SPI0_MCR = SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
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SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);
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SPI0_CTAR1 = SPI_CTAR_FMSZ(15) | SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1);
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SPI0_MCR = SPI_MCR_MSTR | SPI_MCR_PCSIS(0x1F);
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SPCR.enable_pins(); // pins managed by SPCRemulation in avr_emulation.h
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}
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void SPIClass::end() {
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SPCR.disable_pins();
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SPI0_MCR = SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
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}
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void SPIClass::usingInterrupt(IRQ_NUMBER_t interruptName)
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{
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uint32_t n = (uint32_t)interruptName;
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if (n >= NVIC_NUM_INTERRUPTS) return;
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//Serial.print("usingInterrupt ");
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//Serial.println(n);
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interruptMasksUsed |= (1 << (n >> 5));
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interruptMask[n >> 5] |= (1 << (n & 0x1F));
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//Serial.printf("interruptMasksUsed = %d\n", interruptMasksUsed);
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//Serial.printf("interruptMask[0] = %08X\n", interruptMask[0]);
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//Serial.printf("interruptMask[1] = %08X\n", interruptMask[1]);
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//Serial.printf("interruptMask[2] = %08X\n", interruptMask[2]);
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}
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void SPIClass::notUsingInterrupt(IRQ_NUMBER_t interruptName)
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{
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uint32_t n = (uint32_t)interruptName;
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if (n >= NVIC_NUM_INTERRUPTS) return;
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interruptMask[n >> 5] &= ~(1 << (n & 0x1F));
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if (interruptMask[n >> 5] == 0) {
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interruptMasksUsed &= ~(1 << (n >> 5));
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}
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}
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const uint16_t SPISettings::ctar_div_table[23] = {
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2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40,
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56, 64, 96, 128, 192, 256, 384, 512, 640, 768
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};
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const uint32_t SPISettings::ctar_clock_table[23] = {
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_DBR | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_DBR | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_DBR | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1),
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(0) | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(1),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(2),
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(1) | SPI_CTAR_CSSCK(0),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(2),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(4) | SPI_CTAR_CSSCK(3),
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(2),
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SPI_CTAR_PBR(3) | SPI_CTAR_BR(3) | SPI_CTAR_CSSCK(2),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(5) | SPI_CTAR_CSSCK(4),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(5) | SPI_CTAR_CSSCK(4),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(5),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(6) | SPI_CTAR_CSSCK(5),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(6),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(6),
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(8) | SPI_CTAR_CSSCK(7),
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(7) | SPI_CTAR_CSSCK(6),
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(8) | SPI_CTAR_CSSCK(7)
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};
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static void updateCTAR(uint32_t ctar)
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{
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if (SPI0_CTAR0 != ctar) {
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uint32_t mcr = SPI0_MCR;
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if (mcr & SPI_MCR_MDIS) {
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SPI0_CTAR0 = ctar;
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SPI0_CTAR1 = ctar | SPI_CTAR_FMSZ(8);
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} else {
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SPI0_MCR = SPI_MCR_MDIS | SPI_MCR_HALT | SPI_MCR_PCSIS(0x1F);
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SPI0_CTAR0 = ctar;
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SPI0_CTAR1 = ctar | SPI_CTAR_FMSZ(8);
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SPI0_MCR = mcr;
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}
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}
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}
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void SPIClass::setBitOrder(uint8_t bitOrder)
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{
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SIM_SCGC6 |= SIM_SCGC6_SPI0;
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uint32_t ctar = SPI0_CTAR0;
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if (bitOrder == LSBFIRST) {
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ctar |= SPI_CTAR_LSBFE;
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} else {
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ctar &= ~SPI_CTAR_LSBFE;
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}
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updateCTAR(ctar);
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}
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void SPIClass::setDataMode(uint8_t dataMode)
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{
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SIM_SCGC6 |= SIM_SCGC6_SPI0;
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// TODO: implement with native code
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SPCR = (SPCR & ~SPI_MODE_MASK) | dataMode;
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}
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void SPIClass::setClockDivider_noInline(uint32_t clk)
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{
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SIM_SCGC6 |= SIM_SCGC6_SPI0;
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uint32_t ctar = SPI0_CTAR0;
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ctar &= (SPI_CTAR_CPOL | SPI_CTAR_CPHA | SPI_CTAR_LSBFE);
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if (ctar & SPI_CTAR_CPHA) {
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clk = (clk & 0xFFFF0FFF) | ((clk & 0xF000) >> 4);
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}
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ctar |= clk;
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updateCTAR(ctar);
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}
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bool SPIClass::pinIsChipSelect(uint8_t pin)
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{
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if (pin == 10 || pin == 9 || pin == 6 || pin == 2 || pin == 15) return true;
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if (pin >= 20 && pin <= 23) return true;
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return false;
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}
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bool SPIClass::pinIsChipSelect(uint8_t pin1, uint8_t pin2)
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{
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if (!pinIsChipSelect(pin1) || !pinIsChipSelect(pin2)) return false;
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if ((pin1 == 2 && pin2 == 10) || (pin1 == 10 && pin2 == 2)) return false;
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if ((pin1 == 6 && pin2 == 9) || (pin1 == 9 && pin2 == 6)) return false;
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if ((pin1 == 20 && pin2 == 23) || (pin1 == 23 && pin2 == 20)) return false;
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if ((pin1 == 21 && pin2 == 22) || (pin1 == 22 && pin2 == 21)) return false;
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return true;
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}
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uint8_t SPIClass::setCS(uint8_t pin)
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{
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switch (pin) {
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case 10: CORE_PIN10_CONFIG = PORT_PCR_MUX(2); return 0x01; // PTC4
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case 2: CORE_PIN2_CONFIG = PORT_PCR_MUX(2); return 0x01; // PTD0
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case 9: CORE_PIN9_CONFIG = PORT_PCR_MUX(2); return 0x02; // PTC3
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case 6: CORE_PIN6_CONFIG = PORT_PCR_MUX(2); return 0x02; // PTD4
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case 20: CORE_PIN20_CONFIG = PORT_PCR_MUX(2); return 0x04; // PTD5
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case 23: CORE_PIN23_CONFIG = PORT_PCR_MUX(2); return 0x04; // PTC2
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case 21: CORE_PIN21_CONFIG = PORT_PCR_MUX(2); return 0x08; // PTD6
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case 22: CORE_PIN22_CONFIG = PORT_PCR_MUX(2); return 0x08; // PTC1
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case 15: CORE_PIN15_CONFIG = PORT_PCR_MUX(2); return 0x10; // PTC0
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}
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return 0;
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}
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/**********************************************************/
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/* 32 bit Teensy-LC */
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/**********************************************************/
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#elif defined(__arm__) && defined(TEENSYDUINO) && defined(KINETISL)
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SPIClass SPI;
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SPI1Class SPI1;
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uint32_t SPIClass::interruptMask = 0;
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uint32_t SPIClass::interruptSave = 0;
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uint32_t SPI1Class::interruptMask = 0;
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uint32_t SPI1Class::interruptSave = 0;
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#ifdef SPI_TRANSACTION_MISMATCH_LED
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uint8_t SPIClass::inTransactionFlag = 0;
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uint8_t SPI1Class::inTransactionFlag = 0;
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#endif
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void SPIClass::begin()
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{
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SIM_SCGC4 |= SIM_SCGC4_SPI0;
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SPI0_C1 = SPI_C1_SPE | SPI_C1_MSTR;
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SPI0_C2 = 0;
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uint8_t tmp __attribute__((unused)) = SPI0_S;
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SPCR.enable_pins(); // pins managed by SPCRemulation in avr_emulation.h
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}
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void SPIClass::end() {
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SPCR.disable_pins();
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SPI0_C1 = 0;
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}
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const uint16_t SPISettings::br_div_table[30] = {
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2, 4, 6, 8, 10, 12, 14, 16, 20, 24,
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28, 32, 40, 48, 56, 64, 80, 96, 112, 128,
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160, 192, 224, 256, 320, 384, 448, 512, 640, 768,
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};
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const uint8_t SPISettings::br_clock_table[30] = {
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SPI_BR_SPPR(0) | SPI_BR_SPR(0),
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SPI_BR_SPPR(1) | SPI_BR_SPR(0),
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SPI_BR_SPPR(2) | SPI_BR_SPR(0),
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SPI_BR_SPPR(3) | SPI_BR_SPR(0),
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SPI_BR_SPPR(4) | SPI_BR_SPR(0),
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SPI_BR_SPPR(5) | SPI_BR_SPR(0),
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SPI_BR_SPPR(6) | SPI_BR_SPR(0),
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SPI_BR_SPPR(7) | SPI_BR_SPR(0),
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SPI_BR_SPPR(4) | SPI_BR_SPR(1),
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SPI_BR_SPPR(5) | SPI_BR_SPR(1),
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SPI_BR_SPPR(6) | SPI_BR_SPR(1),
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SPI_BR_SPPR(7) | SPI_BR_SPR(1),
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SPI_BR_SPPR(4) | SPI_BR_SPR(2),
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SPI_BR_SPPR(5) | SPI_BR_SPR(2),
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SPI_BR_SPPR(6) | SPI_BR_SPR(2),
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SPI_BR_SPPR(7) | SPI_BR_SPR(2),
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SPI_BR_SPPR(4) | SPI_BR_SPR(3),
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SPI_BR_SPPR(5) | SPI_BR_SPR(3),
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SPI_BR_SPPR(6) | SPI_BR_SPR(3),
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SPI_BR_SPPR(7) | SPI_BR_SPR(3),
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SPI_BR_SPPR(4) | SPI_BR_SPR(4),
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SPI_BR_SPPR(5) | SPI_BR_SPR(4),
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SPI_BR_SPPR(6) | SPI_BR_SPR(4),
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SPI_BR_SPPR(7) | SPI_BR_SPR(4),
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SPI_BR_SPPR(4) | SPI_BR_SPR(5),
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SPI_BR_SPPR(5) | SPI_BR_SPR(5),
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SPI_BR_SPPR(6) | SPI_BR_SPR(5),
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SPI_BR_SPPR(7) | SPI_BR_SPR(5),
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SPI_BR_SPPR(4) | SPI_BR_SPR(6),
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SPI_BR_SPPR(5) | SPI_BR_SPR(6)
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};
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uint8_t SPIClass::setCS(uint8_t pin)
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{
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switch (pin) {
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case 10: CORE_PIN10_CONFIG = PORT_PCR_MUX(2); return 0x01; // PTC4
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case 2: CORE_PIN2_CONFIG = PORT_PCR_MUX(2); return 0x01; // PTD0
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}
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return 0;
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}
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void SPI1Class::begin()
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{
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SIM_SCGC4 |= SIM_SCGC4_SPI1;
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SPI1_C1 = SPI_C1_SPE | SPI_C1_MSTR;
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SPI1_C2 = 0;
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uint8_t tmp __attribute__((unused)) = SPI1_S;
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SPCR1.enable_pins(); // pins managed by SPCRemulation in avr_emulation.h
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}
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void SPI1Class::end() {
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SPCR1.disable_pins();
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SPI1_C1 = 0;
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}
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uint8_t SPI1Class::setCS(uint8_t pin)
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{
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switch (pin) {
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case 6: CORE_PIN6_CONFIG = PORT_PCR_MUX(2); return 0x01; // PTD4
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}
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return 0;
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}
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/**********************************************************/
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/* 32 bit Arduino Due */
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/**********************************************************/
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#elif defined(__arm__) && defined(__SAM3X8E__)
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#include "SPI.h"
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SPIClass::SPIClass(Spi *_spi, uint32_t _id, void(*_initCb)(void)) :
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spi(_spi), id(_id), initCb(_initCb), initialized(false)
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{
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// Empty
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}
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void SPIClass::begin() {
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init();
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// NPCS control is left to the user
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// Default speed set to 4Mhz
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setClockDivider(BOARD_SPI_DEFAULT_SS, 21);
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setDataMode(BOARD_SPI_DEFAULT_SS, SPI_MODE0);
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setBitOrder(BOARD_SPI_DEFAULT_SS, MSBFIRST);
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}
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void SPIClass::begin(uint8_t _pin) {
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init();
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uint32_t spiPin = BOARD_PIN_TO_SPI_PIN(_pin);
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PIO_Configure(
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g_APinDescription[spiPin].pPort,
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g_APinDescription[spiPin].ulPinType,
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g_APinDescription[spiPin].ulPin,
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g_APinDescription[spiPin].ulPinConfiguration);
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// Default speed set to 4Mhz
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setClockDivider(_pin, 21);
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setDataMode(_pin, SPI_MODE0);
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setBitOrder(_pin, MSBFIRST);
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}
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void SPIClass::init() {
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if (initialized)
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return;
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interruptMode = 0;
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interruptMask = 0;
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interruptSave = 0;
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initCb();
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SPI_Configure(spi, id, SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS);
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SPI_Enable(spi);
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initialized = true;
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}
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#ifndef interruptsStatus
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#define interruptsStatus() __interruptsStatus()
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static inline unsigned char __interruptsStatus(void) __attribute__((always_inline, unused));
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static inline unsigned char __interruptsStatus(void) {
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unsigned int primask;
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asm volatile ("mrs %0, primask" : "=r" (primask));
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if (primask) return 0;
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return 1;
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}
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#endif
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void SPIClass::usingInterrupt(uint8_t interruptNumber)
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{
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uint8_t irestore;
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irestore = interruptsStatus();
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noInterrupts();
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if (interruptMode < 2) {
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if (interruptNumber > NUM_DIGITAL_PINS) {
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interruptMode = 2;
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} else {
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uint8_t imask = interruptMask;
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Pio *pio = g_APinDescription[interruptNumber].pPort;
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if (pio == PIOA) {
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imask |= 1;
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} else if (pio == PIOB) {
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imask |= 2;
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} else if (pio == PIOC) {
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imask |= 4;
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} else if (pio == PIOD) {
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imask |= 8;
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}
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interruptMask = imask;
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interruptMode = 1;
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}
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}
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if (irestore) interrupts();
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}
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void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
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{
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if (interruptMode > 0) {
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if (interruptMode == 1) {
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uint8_t imask = interruptMask;
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if (imask & 1) NVIC_DisableIRQ(PIOA_IRQn);
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if (imask & 2) NVIC_DisableIRQ(PIOB_IRQn);
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if (imask & 4) NVIC_DisableIRQ(PIOC_IRQn);
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if (imask & 8) NVIC_DisableIRQ(PIOD_IRQn);
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} else {
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interruptSave = interruptsStatus();
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noInterrupts();
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}
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}
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uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(pin);
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bitOrder[ch] = settings.border;
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SPI_ConfigureNPCS(spi, ch, settings.config);
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}
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void SPIClass::endTransaction(void)
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{
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if (interruptMode > 0) {
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if (interruptMode == 1) {
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uint8_t imask = interruptMask;
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if (imask & 1) NVIC_EnableIRQ(PIOA_IRQn);
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if (imask & 2) NVIC_EnableIRQ(PIOB_IRQn);
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if (imask & 4) NVIC_EnableIRQ(PIOC_IRQn);
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if (imask & 8) NVIC_EnableIRQ(PIOD_IRQn);
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} else {
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if (interruptSave) interrupts();
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}
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}
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}
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void SPIClass::end(uint8_t _pin) {
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uint32_t spiPin = BOARD_PIN_TO_SPI_PIN(_pin);
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// Setting the pin as INPUT will disconnect it from SPI peripheral
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pinMode(spiPin, INPUT);
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}
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void SPIClass::end() {
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SPI_Disable(spi);
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initialized = false;
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}
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void SPIClass::setBitOrder(uint8_t _pin, BitOrder _bitOrder) {
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uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
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bitOrder[ch] = _bitOrder;
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}
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void SPIClass::setDataMode(uint8_t _pin, uint8_t _mode) {
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uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
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mode[ch] = _mode | SPI_CSR_CSAAT;
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// SPI_CSR_DLYBCT(1) keeps CS enabled for 32 MCLK after a completed
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// transfer. Some device needs that for working properly.
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SPI_ConfigureNPCS(spi, ch, mode[ch] | SPI_CSR_SCBR(divider[ch]) | SPI_CSR_DLYBCT(1));
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}
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void SPIClass::setClockDivider(uint8_t _pin, uint8_t _divider) {
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uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
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divider[ch] = _divider;
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// SPI_CSR_DLYBCT(1) keeps CS enabled for 32 MCLK after a completed
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// transfer. Some device needs that for working properly.
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SPI_ConfigureNPCS(spi, ch, mode[ch] | SPI_CSR_SCBR(divider[ch]) | SPI_CSR_DLYBCT(1));
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}
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byte SPIClass::transfer(byte _pin, uint8_t _data, SPITransferMode _mode) {
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uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(_pin);
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// Reverse bit order
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if (bitOrder[ch] == LSBFIRST)
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_data = __REV(__RBIT(_data));
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uint32_t d = _data | SPI_PCS(ch);
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if (_mode == SPI_LAST)
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d |= SPI_TDR_LASTXFER;
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// SPI_Write(spi, _channel, _data);
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while ((spi->SPI_SR & SPI_SR_TDRE) == 0)
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;
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spi->SPI_TDR = d;
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// return SPI_Read(spi);
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while ((spi->SPI_SR & SPI_SR_RDRF) == 0)
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;
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d = spi->SPI_RDR;
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// Reverse bit order
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if (bitOrder[ch] == LSBFIRST)
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d = __REV(__RBIT(d));
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return d & 0xFF;
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}
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void SPIClass::attachInterrupt(void) {
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// Should be enableInterrupt()
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}
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void SPIClass::detachInterrupt(void) {
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// Should be disableInterrupt()
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}
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#if SPI_INTERFACES_COUNT > 0
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static void SPI_0_Init(void) {
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PIO_Configure(
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g_APinDescription[PIN_SPI_MOSI].pPort,
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g_APinDescription[PIN_SPI_MOSI].ulPinType,
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g_APinDescription[PIN_SPI_MOSI].ulPin,
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g_APinDescription[PIN_SPI_MOSI].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[PIN_SPI_MISO].pPort,
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g_APinDescription[PIN_SPI_MISO].ulPinType,
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g_APinDescription[PIN_SPI_MISO].ulPin,
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g_APinDescription[PIN_SPI_MISO].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[PIN_SPI_SCK].pPort,
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g_APinDescription[PIN_SPI_SCK].ulPinType,
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g_APinDescription[PIN_SPI_SCK].ulPin,
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g_APinDescription[PIN_SPI_SCK].ulPinConfiguration);
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}
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SPIClass SPI(SPI_INTERFACE, SPI_INTERFACE_ID, SPI_0_Init);
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#endif
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#endif
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