This commit is contained in:
hg 2014-06-05 20:45:12 +02:00
parent 2a621fbaf9
commit b4c4cd44a3
2 changed files with 25 additions and 12 deletions

View File

@ -46,7 +46,7 @@ int main() {
uartWrite('W');
while (1) {
__bis_status_register(LPM0_bits);
// __bis_status_register(LPM0_bits);
}
}

View File

@ -27,6 +27,9 @@ static inline void disableDataRegisterEmptyInterrupt() {
void uartInit() {
UCA0CTL1 |= UCSWRST;
P1SEL = BIT1 + BIT2;
P1SEL2 = BIT1 + BIT2;
UCA0CTL1 |= UCSSEL0; // ACLK
UCA0BR0 = 13;
@ -43,7 +46,24 @@ void uartInit() {
// stdout = mystdout;
}
inline void _realUartTx() {
if ((IFG2 | UCA0TXIE) != 0) {
if (txBufferReadIdx != txBufferWriteIdx) {
UCA0TXBUF = txBuffer[txBufferReadIdx];
txBufferReadIdx++;
if (txBufferReadIdx > UART_TX_BUFFER_SIZE) {
txBufferReadIdx = 0;
}
} else {
disableDataRegisterEmptyInterrupt();
}
}
}
void uartWrite(uint8_t o) {
#if 0
UCA0TXBUF = o;
#else
if (txBufferWriteIdx == (UART_TX_BUFFER_SIZE - 1)) {
while (txBufferReadIdx == UART_TX_BUFFER_SIZE);
} else {
@ -58,6 +78,8 @@ void uartWrite(uint8_t o) {
}
enableDataRegisterEmptyInterrupt();
_realUartTx();
#endif
}
@ -69,18 +91,9 @@ void uartWrite(uint8_t o) {
//}
ISR(USCIAB0TX, UART_TX_ISR) {
if ((IFG2 | UCA0TXIE) != 0) {
if (txBufferReadIdx != txBufferWriteIdx) {
UCA0TXBUF = txBuffer[txBufferReadIdx];
txBufferReadIdx++;
if (txBufferReadIdx > UART_TX_BUFFER_SIZE) {
txBufferReadIdx = 0;
}
} else {
disableDataRegisterEmptyInterrupt();
}
}
_realUartTx();
}
ISR(USCIAB0RX, UART_RX_ISR) {